oxnas: pcie: model shared resource as external pcie-phy driver
Refactor pcie-oxnas to have shared resources in syscon and new pcie-phy driver. Hopefully this revives PCIe... Signed-off-by: Daniel Golle <daniel@makrotopia.org>v19.07.3_mercusys_ac12_duma
Daniel Golle
5 years ago
parent
3bb9dcf446
commit
e7aa4c0db7
@ -0,0 +1,150 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 Daniel Golle <daniel@makrotopia.org>
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*
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*/
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#include <dt-bindings/phy/phy.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/mfd/syscon.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#define ADDR_VAL(val) ((val) & 0xFFFF)
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#define DATA_VAL(val) ((val) & 0xFFFF)
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#define SYS_CTRL_HCSL_CTRL_REGOFFSET 0x114
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enum {
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HCSL_BIAS_ON = BIT(0),
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HCSL_PCIE_EN = BIT(1),
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HCSL_PCIEA_EN = BIT(2),
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HCSL_PCIEB_EN = BIT(3),
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};
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enum {
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/* pcie phy reg offset */
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PHY_ADDR = 0,
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PHY_DATA = 4,
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/* phy data reg bits */
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READ_EN = BIT(16),
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WRITE_EN = BIT(17),
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CAP_DATA = BIT(18),
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};
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struct oxnas_pcie_phy {
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struct device *dev;
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void __iomem *membase;
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const struct phy_ops *ops;
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struct regmap *sys_ctrl;
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};
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static int oxnas_pcie_phy_init(struct phy *phy)
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{
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struct oxnas_pcie_phy *pciephy = phy_get_drvdata(phy);
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struct reset_control *rstc;
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int ret;
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/* generate clocks from HCSL buffers, shared parts */
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regmap_write(pciephy->sys_ctrl, SYS_CTRL_HCSL_CTRL_REGOFFSET, HCSL_BIAS_ON|HCSL_PCIE_EN);
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/* Ensure PCIe PHY is properly reset */
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rstc = reset_control_get(pciephy->dev, "phy");
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if (IS_ERR(rstc)) {
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ret = PTR_ERR(rstc);
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} else {
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ret = reset_control_reset(rstc);
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reset_control_put(rstc);
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}
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if (ret) {
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dev_err(pciephy->dev, "phy reset failed %d\n", ret);
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return ret;
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}
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return 0;
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}
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static int oxnas_pcie_phy_power_on(struct phy *phy)
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{
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struct oxnas_pcie_phy *pciephy = phy_get_drvdata(phy);
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/* Enable PCIe Pre-Emphasis: What these value means? */
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writel(ADDR_VAL(0x0014), pciephy->membase + PHY_ADDR);
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writel(DATA_VAL(0xce10) | CAP_DATA, pciephy->membase + PHY_DATA);
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writel(DATA_VAL(0xce10) | WRITE_EN, pciephy->membase + PHY_DATA);
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writel(ADDR_VAL(0x2004), pciephy->membase + PHY_ADDR);
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writel(DATA_VAL(0x82c7) | CAP_DATA, pciephy->membase + PHY_DATA);
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writel(DATA_VAL(0x82c7) | WRITE_EN, pciephy->membase + PHY_DATA);
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return 0;
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}
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static const struct phy_ops ops = {
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.init = oxnas_pcie_phy_init,
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.power_on = oxnas_pcie_phy_power_on,
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.owner = THIS_MODULE,
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};
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static int oxnas_pcie_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = pdev->dev.of_node;
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struct phy *generic_phy;
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struct phy_provider *phy_provider;
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struct oxnas_pcie_phy *pciephy;
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struct regmap *sys_ctrl;
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void __iomem *membase;
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membase = of_iomap(np, 0);
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if (IS_ERR(membase))
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return PTR_ERR(membase);
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sys_ctrl = syscon_regmap_lookup_by_compatible("oxsemi,ox820-sys-ctrl");
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if (IS_ERR(sys_ctrl)) {
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dev_err(dev, "Cannot find OX820 SYSCRTL\n");
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return PTR_ERR(sys_ctrl);
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}
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pciephy = devm_kzalloc(dev, sizeof(*pciephy), GFP_KERNEL);
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if (!pciephy)
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return -ENOMEM;
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pciephy->sys_ctrl = sys_ctrl;
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pciephy->membase = membase;
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pciephy->dev = dev;
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pciephy->ops = &ops;
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generic_phy = devm_phy_create(dev, dev->of_node, pciephy->ops);
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if (IS_ERR(generic_phy)) {
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dev_err(dev, "failed to create PHY\n");
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return PTR_ERR(generic_phy);
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}
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phy_set_drvdata(generic_phy, pciephy);
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static const struct of_device_id oxnas_pcie_phy_id_table[] = {
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{ .compatible = "oxsemi,ox820-pcie-phy" },
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{ },
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};
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static struct platform_driver oxnas_pcie_phy_driver = {
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.probe = oxnas_pcie_phy_probe,
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.driver = {
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.name = "ox820-pcie-phy",
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.of_match_table = oxnas_pcie_phy_id_table,
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},
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};
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builtin_platform_driver(oxnas_pcie_phy_driver);
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@ -0,0 +1,44 @@
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--- a/arch/arm/boot/dts/ox820.dtsi
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+++ b/arch/arm/boot/dts/ox820.dtsi
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@@ -246,6 +246,15 @@
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};
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};
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+ pcie_phy: pcie-phy@a00000 {
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+ compatible = "oxsemi,ox820-pcie-phy";
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+ reg = <0xa00000 0x10>;
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+ #phy-cells = <0>;
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+ resets = <&reset RESET_PCIEPHY>;
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+ reset-names = "phy";
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+ status = "disabled";
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+ };
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+
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sys: sys-ctrl@e00000 {
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compatible = "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd";
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reg = <0xe00000 0x200000>;
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--- a/drivers/phy/Kconfig
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+++ b/drivers/phy/Kconfig
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@@ -26,6 +26,13 @@ config PHY_LPC18XX_USB_OTG
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This driver is need for USB0 support on LPC18xx/43xx and takes
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care of enabling and clock setup.
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+config PHY_OXNAS
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+ tristate "Oxford Semi. OX820 PCI-E PHY support"
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+ depends on HAS_IOMEM && OF && (ARM || COMPILE_TEST)
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+ select GENERIC_PHY
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+ help
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+ This option enables support for OXNAS OX820 SoC PCIE PHY.
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+
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config PHY_PISTACHIO_USB
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tristate "IMG Pistachio USB2.0 PHY driver"
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depends on MACH_PISTACHIO
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--- a/drivers/phy/Makefile
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+++ b/drivers/phy/Makefile
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@@ -5,6 +5,7 @@
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obj-$(CONFIG_GENERIC_PHY) += phy-core.o
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obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
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+obj-$(CONFIG_PHY_OXNAS) += phy-oxnas-pcie.o
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obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
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obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
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obj-$(CONFIG_ARCH_SUNXI) += allwinner/
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