kernel: bump 4.14 to 4.14.48
Remove upstreamed patches: generic/pending/101-clocksource-mips-gic-timer-fix-clocksource-counter-w.patch generic/pending/103-MIPS-c-r4k-fix-data-corruption-related-to-cache-coherence.patch generic/pending/182-net-qmi_wwan-add-BroadMobi-BM806U-2020-2033.patch lantiq/0025-MIPS-lantiq-gphy-Remove-reboot-remove-reset-asserts.patch Update patches that no longer apply: generic/pending/811-pci_disable_usb_common_quirks.patch ath79/0009-MIPS-ath79-add-lots-of-missing-registers.patch Fixes CVE-2018-6412. Compile-tested: octeon, x86/64. Runtime-tested: octeon, x86/64. Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>v19.07.3_mercusys_ac12_duma
Stijn Tintel
6 years ago
parent
7590c3c58f
commit
e52f3e9b13
@ -1,23 +0,0 @@
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From: Felix Fietkau <nbd@nbd.name>
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Date: Wed, 21 Feb 2018 13:40:12 +0100
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Subject: [PATCH] clocksource: mips-gic-timer: fix clocksource counter width
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This code needs to use ffs instead of fls on the mask to determine the
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shift for reading the GIC_CONFIG_COUNTBITS field.
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Fixes: e07127a077c7 ("clocksource: mips-gic-timer: Use new GIC accessor functions")
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Cc: Paul Burton <paul.burton@imgtec.com>
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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---
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--- a/drivers/clocksource/mips-gic-timer.c
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+++ b/drivers/clocksource/mips-gic-timer.c
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@@ -164,7 +164,7 @@ static int __init __gic_clocksource_init
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/* Set clocksource mask. */
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count_width = read_gic_config() & GIC_CONFIG_COUNTBITS;
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- count_width >>= __fls(GIC_CONFIG_COUNTBITS);
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+ count_width >>= __ffs(GIC_CONFIG_COUNTBITS);
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count_width *= 4;
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count_width += 32;
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gic_clocksource.mask = CLOCKSOURCE_MASK(count_width);
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@ -1,90 +0,0 @@
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From patchwork Thu Apr 26 23:28:34 2018
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [v2] MIPS: c-r4k: fix data corruption related to cache coherence.
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X-Patchwork-Submitter: NeilBrown <neil@brown.name>
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X-Patchwork-Id: 19259
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Message-Id: <87vacdlf8d.fsf@notabene.neil.brown.name>
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To: James Hogan <jhogan@kernel.org>
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Cc: Ralf Baechle <ralf@linux-mips.org>,
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Paul Burton <paul.burton@mips.com>, linux-mips@linux-mips.org,
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linux-kernel@vger.kernel.org
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Date: Fri, 27 Apr 2018 09:28:34 +1000
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From: NeilBrown <neil@brown.name>
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List-Id: linux-mips <linux-mips.eddie.linux-mips.org>
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When DMA will be performed to a MIPS32 1004K CPS, the
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L1-cache for the range needs to be flushed and invalidated
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first.
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The code currently takes one of two approaches.
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1/ If the range is less than the size of the dcache, then
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HIT type requests flush/invalidate cache lines for the
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particular addresses. HIT-type requests a globalised
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by the CPS so this is safe on SMP.
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2/ If the range is larger than the size of dcache, then
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INDEX type requests flush/invalidate the whole cache.
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INDEX type requests affect the local cache only. CPS
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does not propagate them in any way. So this invalidation
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is not safe on SMP CPS systems.
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Data corruption due to '2' can quite easily be demonstrated by
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repeatedly "echo 3 > /proc/sys/vm/drop_caches" and then sha1sum
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a file that is several times the size of available memory.
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Dropping caches means that large contiguous extents (large than
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dcache) are more likely.
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This was not a problem before Linux-4.8 because option 2 was
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never used if CONFIG_MIPS_CPS was defined. The commit
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which removed that apparently didn't appreciate the full
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consequence of the change.
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We could, in theory, globalize the INDEX based flush by sending an IPI
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to other cores. These cache invalidation routines can be called with
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interrupts disabled and synchronous IPI require interrupts to be
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enabled. Asynchronous IPI may not trigger writeback soon enough.
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So we cannot use IPI in practice.
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We can already test is IPI would be needed for an INDEX operation
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with r4k_op_needs_ipi(R4K_INDEX). If this is True then we mustn't try
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the INDEX approach as we cannot use IPI. If this is False (e.g. when
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there is only one core and hence one L1 cache) then it is safe to
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use the INDEX approach without IPI.
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This patch avoids options 2 if r4k_op_needs_ipi(R4K_INDEX), and so
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eliminates the corruption.
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Fixes: c00ab4896ed5 ("MIPS: Remove cpu_has_safe_index_cacheops")
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Cc: stable@vger.kernel.org # v4.8+
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Signed-off-by: NeilBrown <neil@brown.name>
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---
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arch/mips/mm/c-r4k.c | 9 ++++++---
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1 file changed, 6 insertions(+), 3 deletions(-)
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--- a/arch/mips/mm/c-r4k.c
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+++ b/arch/mips/mm/c-r4k.c
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@@ -851,9 +851,12 @@ static void r4k_dma_cache_wback_inv(unsi
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/*
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* Either no secondary cache or the available caches don't have the
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* subset property so we have to flush the primary caches
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- * explicitly
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+ * explicitly.
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+ * If we would need IPI to perform an INDEX-type operation, then
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+ * we have to use the HIT-type alternative as IPI cannot be used
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+ * here due to interrupts possibly being disabled.
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*/
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- if (size >= dcache_size) {
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+ if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
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r4k_blast_dcache();
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} else {
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R4600_HIT_CACHEOP_WAR_IMPL;
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@@ -890,7 +893,7 @@ static void r4k_dma_cache_inv(unsigned l
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return;
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}
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- if (size >= dcache_size) {
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+ if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
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r4k_blast_dcache();
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} else {
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R4600_HIT_CACHEOP_WAR_IMPL;
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@ -1,28 +0,0 @@
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From 743989254ea9f132517806d8893ca9b6cf9dc86b Mon Sep 17 00:00:00 2001
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From: Pawel Dembicki <paweldembicki@gmail.com>
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Date: Sat, 24 Mar 2018 22:08:14 +0100
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Subject: [PATCH] net: qmi_wwan: add BroadMobi BM806U 2020:2033
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BroadMobi BM806U is an Qualcomm MDM9225 based 3G/4G modem.
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Tested hardware BM806U is mounted on D-Link DWR-921-C3 router.
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The USB id is added to qmi_wwan.c to allow QMI communication with
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the BM806U.
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Tested on 4.14 kernel and OpenWRT.
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Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/usb/qmi_wwan.c | 1 +
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1 file changed, 1 insertion(+)
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--- a/drivers/net/usb/qmi_wwan.c
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+++ b/drivers/net/usb/qmi_wwan.c
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@@ -1184,6 +1184,7 @@ static const struct usb_device_id produc
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{QMI_FIXED_INTF(0x19d2, 0x2002, 4)}, /* ZTE (Vodafone) K3765-Z */
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{QMI_FIXED_INTF(0x2001, 0x7e19, 4)}, /* D-Link DWM-221 B1 */
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{QMI_FIXED_INTF(0x2001, 0x7e35, 4)}, /* D-Link DWM-222 */
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+ {QMI_FIXED_INTF(0x2020, 0x2033, 4)}, /* BroadMobi BM806U */
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{QMI_FIXED_INTF(0x0f3d, 0x68a2, 8)}, /* Sierra Wireless MC7700 */
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{QMI_FIXED_INTF(0x114f, 0x68a2, 8)}, /* Sierra Wireless MC7750 */
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{QMI_FIXED_INTF(0x1199, 0x68a2, 8)}, /* Sierra Wireless MC7710 in QMI mode */
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@ -1,86 +0,0 @@
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From ae14aba7fc748b2da282b59a2f516a311ed1f6eb Mon Sep 17 00:00:00 2001
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From: Mathias Kresin <dev@kresin.me>
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Date: Tue, 27 Mar 2018 23:15:07 +0200
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Subject: [PATCH] MIPS: lantiq: gphy: Remove reboot/remove reset asserts
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While doing a global software reset, these bits are not cleared and let
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some bootloader fail to initialise the GPHYs. The bootloader don't expect
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these bits to be set, as they aren't during power on.
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The asserts were a workaround for a wrong syscon-reboot mask. With a mask
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set which includes the GPHY resets of the first reset register, the
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resets of the second reset register arn't required any more.
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Signed-off-by: Mathias Kresin <dev@kresin.me>
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---
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drivers/soc/lantiq/gphy.c | 34 ----------------------------------
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1 file changed, 34 deletions(-)
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--- a/drivers/soc/lantiq/gphy.c
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+++ b/drivers/soc/lantiq/gphy.c
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@@ -30,7 +30,6 @@ struct xway_gphy_priv {
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struct clk *gphy_clk_gate;
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struct reset_control *gphy_reset;
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struct reset_control *gphy_reset2;
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- struct notifier_block gphy_reboot_nb;
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void __iomem *membase;
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char *fw_name;
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};
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@@ -65,24 +64,6 @@ static const struct of_device_id xway_gp
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};
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MODULE_DEVICE_TABLE(of, xway_gphy_match);
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-static struct xway_gphy_priv *to_xway_gphy_priv(struct notifier_block *nb)
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-{
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- return container_of(nb, struct xway_gphy_priv, gphy_reboot_nb);
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-}
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-
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-static int xway_gphy_reboot_notify(struct notifier_block *reboot_nb,
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- unsigned long code, void *unused)
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-{
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- struct xway_gphy_priv *priv = to_xway_gphy_priv(reboot_nb);
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-
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- if (priv) {
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- reset_control_assert(priv->gphy_reset);
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- reset_control_assert(priv->gphy_reset2);
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- }
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-
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- return NOTIFY_DONE;
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-}
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-
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static int xway_gphy_load(struct device *dev, struct xway_gphy_priv *priv,
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dma_addr_t *dev_addr)
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{
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@@ -216,14 +197,6 @@ static int xway_gphy_probe(struct platfo
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reset_control_deassert(priv->gphy_reset);
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reset_control_deassert(priv->gphy_reset2);
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- /* assert the gphy reset because it can hang after a reboot: */
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- priv->gphy_reboot_nb.notifier_call = xway_gphy_reboot_notify;
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- priv->gphy_reboot_nb.priority = -1;
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-
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- ret = register_reboot_notifier(&priv->gphy_reboot_nb);
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- if (ret)
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- dev_warn(dev, "Failed to register reboot notifier\n");
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-
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platform_set_drvdata(pdev, priv);
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return ret;
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@@ -235,17 +208,10 @@ static int xway_gphy_remove(struct platf
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struct xway_gphy_priv *priv = platform_get_drvdata(pdev);
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int ret;
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- reset_control_assert(priv->gphy_reset);
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- reset_control_assert(priv->gphy_reset2);
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-
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iowrite32be(0, priv->membase);
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clk_disable_unprepare(priv->gphy_clk_gate);
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- ret = unregister_reboot_notifier(&priv->gphy_reboot_nb);
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- if (ret)
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- dev_warn(dev, "Failed to unregister reboot notifier\n");
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-
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return 0;
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}
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