ar71xx: add support for the D-Link DIR-825 rev. B1 board (thanks to ValXdater)
SVN-Revision: 18621v19.07.3_mercusys_ac12_duma
Gabor Juhos
15 years ago
parent
8a7e19e7db
commit
e4d21e0399
@ -0,0 +1,16 @@
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config interface loopback
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option ifname lo
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option proto static
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option ipaddr 127.0.0.1
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option netmask 255.0.0.0
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config interface lan
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option ifname eth0
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option type bridge
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option proto static
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option ipaddr 192.168.1.1
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option netmask 255.255.255.0
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config interface wan
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option ifname eth1
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option proto dhcp
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@ -0,0 +1,317 @@
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/*
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* D-Link DIR-825 rev. B1 board support
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*
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* Copyright (C) 2009 Lukas Kuna, Evkanet, s.r.o.
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*
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* based on mach-wndr3700.c
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/platform_device.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/flash.h>
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#include <linux/input.h>
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#include <asm/mips_machine.h>
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#include <asm/mach-ar71xx/ar71xx.h>
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#include <asm/mach-ar71xx/pci.h>
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#include <linux/pci.h>
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#include <linux/ath9k_platform.h>
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#include <linux/delay.h>
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#include "devices.h"
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#define DIR825B1_GPIO_LED_BLUE_USB 0
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#define DIR825B1_GPIO_LED_ORANGE_POWER 1
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#define DIR825B1_GPIO_LED_BLUE_POWER 2
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#define DIR825B1_GPIO_LED_BLUE_POWERSAVE 4
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#define DIR825B1_GPIO_LED_ORANGE_PLANET 6
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#define DIR825B1_GPIO_LED_BLUE_PLANET 11
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#define DIR825B1_GPIO_BTN_RESET 3
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#define DIR825B1_GPIO_BTN_POWERSAVE 8
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#define DIR825B1_BUTTONS_POLL_INTERVAL 20
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#define DIR825B1_CAL_LOCATION_0 0xbf661000
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#define DIR825B1_CAL_LOCATION_1 0xbf665000
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#define DIR825B1_MAC_LOCATION_0 0x2ffa81b8
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#define DIR825B1_MAC_LOCATION_1 0x2ffa8370
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static struct ath9k_platform_data dir825b1_wmac0_data;
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static struct ath9k_platform_data dir825b1_wmac1_data;
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static char dir825b1_wmac0_mac[6];
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static char dir825b1_wmac1_mac[6];
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#ifdef CONFIG_MTD_PARTITIONS
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static struct mtd_partition dir825b1_partitions[] = {
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{
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.name = "uboot",
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.offset = 0,
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.size = 0x040000,
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.mask_flags = MTD_WRITEABLE,
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} , {
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.name = "config",
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.offset = 0x040000,
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.size = 0x010000,
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.mask_flags = MTD_WRITEABLE,
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} , {
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.name = "firmware",
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.offset = 0x050000,
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.size = 0x610000,
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} , {
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.name = "caldata",
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.offset = 0x660000,
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.size = 0x010000,
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.mask_flags = MTD_WRITEABLE,
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}
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};
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#endif /* CONFIG_MTD_PARTITIONS */
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static struct flash_platform_data dir825b1_flash_data = {
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#ifdef CONFIG_MTD_PARTITIONS
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.parts = dir825b1_partitions,
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.nr_parts = ARRAY_SIZE(dir825b1_partitions),
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#endif
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};
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static struct spi_board_info dir825b1_spi_info[] = {
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{
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.bus_num = 0,
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.chip_select = 0,
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.max_speed_hz = 25000000,
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.modalias = "m25p80",
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.platform_data = &dir825b1_flash_data,
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}
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};
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static struct gpio_led dir825b1_leds_gpio[] __initdata = {
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{
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.name = "dir825b1:blue:usb",
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.gpio = DIR825B1_GPIO_LED_BLUE_USB,
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.active_low = 1,
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}, {
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.name = "dir825b1:orange:power",
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.gpio = DIR825B1_GPIO_LED_ORANGE_POWER,
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.active_low = 1,
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}, {
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.name = "dir825b1:blue:power",
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.gpio = DIR825B1_GPIO_LED_BLUE_POWER,
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.active_low = 1,
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}, {
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.name = "dir825b1:blue:powersave",
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.gpio = DIR825B1_GPIO_LED_BLUE_POWERSAVE,
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.active_low = 1,
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}, {
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.name = "dir825b1:orange:planet",
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.gpio = DIR825B1_GPIO_LED_ORANGE_PLANET,
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.active_low = 1,
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}, {
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.name = "dir825b1:blue:planet",
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.gpio = DIR825B1_GPIO_LED_BLUE_PLANET,
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.active_low = 1,
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}
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};
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static struct gpio_button dir825b1_gpio_buttons[] __initdata = {
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{
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.desc = "reset",
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.type = EV_KEY,
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.code = BTN_0,
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.threshold = 5,
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.gpio = DIR825B1_GPIO_BTN_RESET,
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.active_low = 1,
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} , {
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.desc = "powersave",
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.type = EV_KEY,
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.code = BTN_1,
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.threshold = 5,
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.gpio = DIR825B1_GPIO_BTN_POWERSAVE,
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.active_low = 1,
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}
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};
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#ifdef CONFIG_PCI
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static struct ar71xx_pci_irq dir825b1_pci_irqs[] __initdata = {
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{
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.slot = 0,
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.pin = 1,
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.irq = AR71XX_PCI_IRQ_DEV0,
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}, {
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.slot = 1,
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.pin = 1,
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.irq = AR71XX_PCI_IRQ_DEV1,
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}
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};
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static int dir825b1_pci_plat_dev_init(struct pci_dev *dev)
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{
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switch(PCI_SLOT(dev->devfn))
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{
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case 17:
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dev->dev.platform_data = &dir825b1_wmac0_data;
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break;
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case 18:
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dev->dev.platform_data = &dir825b1_wmac1_data;
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break;
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}
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return(0);
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}
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static void dir825b1_pci_fixup(struct pci_dev *dev)
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{
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void __iomem *mem;
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u16 *cal_data;
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u16 cmd;
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u32 bar0;
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u32 val;
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if (ar71xx_mach != AR71XX_MACH_DIR825B1) return;
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dir825b1_pci_plat_dev_init(dev);
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cal_data = dev->dev.platform_data;
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if (*cal_data != 0xa55a)
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{
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printk(KERN_ERR "PCI: no calibration data found for %s\n",
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pci_name(dev));
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return;
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}
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mem = ioremap(AR71XX_PCI_MEM_BASE, 0x10000);
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if (!mem)
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{
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printk(KERN_ERR "PCI: ioremap error for device %s\n",
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pci_name(dev));
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return;
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}
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printk(KERN_INFO "PCI: fixup device %s\n", pci_name(dev));
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pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0);
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/* Setup the PCI device to allow access to the internal registers */
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, AR71XX_PCI_MEM_BASE);
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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/* set pointer to first reg address */
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cal_data += 3;
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while (*cal_data != 0xffff)
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{
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u32 reg;
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reg = *cal_data++;
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val = *cal_data++;
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val |= (*cal_data++) << 16;
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__raw_writel(val, mem + reg);
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udelay(100);
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}
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pci_read_config_dword(dev, PCI_VENDOR_ID, &val);
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dev->vendor = val & 0xffff;
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dev->device = (val >> 16) & 0xffff;
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pci_read_config_dword(dev, PCI_CLASS_REVISION, &val);
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dev->revision = val & 0xff;
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dev->class = val >> 8; /* upper 3 bytes */
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
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iounmap(mem);
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID,
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dir825b1_pci_fixup);
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static void __init dir825b1_pci_init(void)
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{
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memcpy(dir825b1_wmac0_data.eeprom_data,
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(u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_0),
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sizeof(dir825b1_wmac0_data.eeprom_data));
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memcpy(dir825b1_wmac1_data.eeprom_data,
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(u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_1),
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sizeof(dir825b1_wmac1_data.eeprom_data));
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memcpy(dir825b1_wmac0_mac, (u8 *)KSEG1ADDR(DIR825B1_MAC_LOCATION_0), 6);
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dir825b1_wmac0_data.macaddr = dir825b1_wmac0_mac;
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memcpy(dir825b1_wmac1_mac, (u8 *)KSEG1ADDR(DIR825B1_MAC_LOCATION_1), 6);
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dir825b1_wmac1_data.macaddr = dir825b1_wmac1_mac;
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ar71xx_pci_plat_dev_init = dir825b1_pci_plat_dev_init;
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ar71xx_pci_init(ARRAY_SIZE(dir825b1_pci_irqs), dir825b1_pci_irqs);
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}
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#else
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static void __init dir825b1_pci_init(void) { }
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#endif /* CONFIG_PCI */
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static void __init dir825b1_setup(void)
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{
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u8 mac[6], i;
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memcpy(mac, (u8*)KSEG1ADDR(DIR825B1_MAC_LOCATION_1), 6);
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for(i = 5; i >= 3; i--)
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if(++mac[i] != 0x00) break;
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ar71xx_set_mac_base(mac);
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ar71xx_add_device_mdio(0x0);
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ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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ar71xx_eth0_data.phy_mask = 0x1E;
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ar71xx_eth0_data.speed = SPEED_1000;
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ar71xx_eth0_data.duplex = DUPLEX_FULL;
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ar71xx_eth0_pll_data.pll_1000 = 0x11110000;
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ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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ar71xx_eth1_data.phy_mask = 0xC0;
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ar71xx_eth1_data.speed = SPEED_1000;
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ar71xx_eth1_data.duplex = DUPLEX_FULL;
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ar71xx_eth1_pll_data.pll_1000 = 0x11110000;
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ar71xx_add_device_eth(0);
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ar71xx_add_device_eth(1);
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ar71xx_add_device_spi(NULL, dir825b1_spi_info,
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ARRAY_SIZE(dir825b1_spi_info));
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ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(dir825b1_leds_gpio),
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dir825b1_leds_gpio);
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ar71xx_add_device_gpio_buttons(-1, DIR825B1_BUTTONS_POLL_INTERVAL,
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ARRAY_SIZE(dir825b1_gpio_buttons),
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dir825b1_gpio_buttons);
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ar71xx_add_device_usb();
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dir825b1_pci_init();
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}
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MIPS_MACHINE(AR71XX_MACH_DIR825B1, "D-Link DIR825B1", dir825b1_setup);
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