ipq806x: replace patches with upstream version
Replace all the custom patches with the backported upstream version Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> [refresh patches] Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>master
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@ -1,79 +0,0 @@
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From 2034addc7e193dc81d7ca60d8884832751b76758 Mon Sep 17 00:00:00 2001
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From: Ajay Kishore <akisho@codeaurora.org>
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Date: Tue, 24 Jan 2017 14:14:16 +0530
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Subject: pinctrl: qcom: use scm_call to route GPIO irq to Apps
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For IPQ806x targets, TZ protects the registers that are used to
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configure the routing of interrupts to a target processor.
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To resolve this, this patch uses scm call to route GPIO interrupts
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to application processor. Also the scm call interface is changed.
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Change-Id: Ib6c06829d04bc8c20483c36e63da92e26cdef9ce
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Signed-off-by: Ajay Kishore <akisho@codeaurora.org>
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---
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--- a/drivers/pinctrl/qcom/pinctrl-msm.c
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+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
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@@ -22,7 +22,8 @@
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#include <linux/reboot.h>
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#include <linux/pm.h>
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#include <linux/log2.h>
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-
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+#include <linux/qcom_scm.h>
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+#include <linux/io.h>
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#include "../core.h"
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#include "../pinconf.h"
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#include "pinctrl-msm.h"
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@@ -706,6 +707,9 @@ static void msm_gpio_irq_mask(struct irq
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const struct msm_pingroup *g;
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unsigned long flags;
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u32 val;
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+ u32 addr;
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+ int ret;
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+ const __be32 *reg;
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g = &pctrl->soc->groups[d->hwirq];
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@@ -819,6 +823,7 @@ static int msm_gpio_irq_set_type(struct
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const struct msm_pingroup *g;
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unsigned long flags;
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u32 val;
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+ int ret;
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g = &pctrl->soc->groups[d->hwirq];
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@@ -832,11 +837,30 @@ static int msm_gpio_irq_set_type(struct
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else
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clear_bit(d->hwirq, pctrl->dual_edge_irqs);
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+ ret = of_device_is_compatible(pctrl->dev->of_node,
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+ "qcom,ipq8064-pinctrl");
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/* Route interrupts to application cpu */
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- val = msm_readl_intr_target(pctrl, g);
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- val &= ~(7 << g->intr_target_bit);
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- val |= g->intr_target_kpss_val << g->intr_target_bit;
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- msm_writel_intr_target(val, pctrl, g);
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+ if (!ret) {
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+ val = msm_readl_intr_target(pctrl, g);
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+ val &= ~(7 << g->intr_target_bit);
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+ val |= g->intr_target_kpss_val << g->intr_target_bit;
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+ msm_writel_intr_target(val, pctrl, g);
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+ } else {
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+ const __be32 *reg = of_get_property(pctrl->dev->of_node, "reg", NULL);
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+ if (reg) {
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+ u32 addr = be32_to_cpup(reg) + g->intr_target_reg;
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+ qcom_scm_io_readl(addr, &val);
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+ __iormb();
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+
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+ val &= ~(7 << g->intr_target_bit);
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+ val |= g->intr_target_kpss_val << g->intr_target_bit;
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+
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+ __iowmb();
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+ ret = qcom_scm_io_writel(addr, val);
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+ if (ret)
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+ pr_err("\n Routing interrupts to Apps proc failed");
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+ }
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+ }
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/* Update configuration for gpio.
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* RAW_STATUS_EN is left on for all gpio irqs. Due to the
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@ -0,0 +1,104 @@
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From 13bec8d49bdf10aab4e1570ef42417f6bfbb6126 Mon Sep 17 00:00:00 2001
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From: Ajay Kishore <akisho@codeaurora.org>
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Date: Fri, 27 Mar 2020 23:32:08 +0100
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Subject: pinctrl: qcom: use scm_call to route GPIO irq to Apps
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For IPQ806x targets, TZ protects the registers that are used to
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configure the routing of interrupts to a target processor.
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To resolve this, this patch uses scm call to route GPIO interrupts
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to application processor. Also the scm call interface is changed.
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Signed-off-by: Ajay Kishore <akisho@codeaurora.org>
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Link: https://lore.kernel.org/r/20200327223209.20409-1-ansuelsmth@gmail.com
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Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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---
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drivers/pinctrl/qcom/pinctrl-msm.c | 43 ++++++++++++++++++++++++++++++++------
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1 file changed, 37 insertions(+), 6 deletions(-)
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(limited to 'drivers/pinctrl/qcom/pinctrl-msm.c')
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--- a/drivers/pinctrl/qcom/pinctrl-msm.c
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+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
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@@ -22,6 +22,8 @@
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#include <linux/reboot.h>
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#include <linux/pm.h>
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#include <linux/log2.h>
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+#include <linux/qcom_scm.h>
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+#include <linux/io.h>
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#include "../core.h"
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#include "../pinconf.h"
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@@ -57,6 +59,8 @@ struct msm_pinctrl {
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struct irq_chip irq_chip;
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int irq;
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+ bool intr_target_use_scm;
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+
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raw_spinlock_t lock;
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DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
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@@ -64,6 +68,7 @@ struct msm_pinctrl {
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const struct msm_pinctrl_soc_data *soc;
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void __iomem *regs[MAX_NR_TILES];
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+ u32 phys_base[MAX_NR_TILES];
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};
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#define MSM_ACCESSOR(name) \
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@@ -832,11 +837,30 @@ static int msm_gpio_irq_set_type(struct
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else
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clear_bit(d->hwirq, pctrl->dual_edge_irqs);
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- /* Route interrupts to application cpu */
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- val = msm_readl_intr_target(pctrl, g);
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- val &= ~(7 << g->intr_target_bit);
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- val |= g->intr_target_kpss_val << g->intr_target_bit;
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- msm_writel_intr_target(val, pctrl, g);
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+ /* Route interrupts to application cpu.
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+ * With intr_target_use_scm interrupts are routed to
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+ * application cpu using scm calls.
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+ */
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+ if (pctrl->intr_target_use_scm) {
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+ u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
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+ int ret;
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+
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+ qcom_scm_io_readl(addr, &val);
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+
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+ val &= ~(7 << g->intr_target_bit);
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+ val |= g->intr_target_kpss_val << g->intr_target_bit;
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+
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+ ret = qcom_scm_io_writel(addr, val);
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+ if (ret)
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+ dev_err(pctrl->dev,
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+ "Failed routing %lu interrupt to Apps proc",
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+ d->hwirq);
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+ } else {
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+ val = msm_readl_intr_target(pctrl, g);
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+ val &= ~(7 << g->intr_target_bit);
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+ val |= g->intr_target_kpss_val << g->intr_target_bit;
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+ msm_writel_intr_target(val, pctrl, g);
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+ }
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/* Update configuration for gpio.
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* RAW_STATUS_EN is left on for all gpio irqs. Due to the
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@@ -1138,6 +1162,9 @@ int msm_pinctrl_probe(struct platform_de
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pctrl->dev = &pdev->dev;
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pctrl->soc = soc_data;
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pctrl->chip = msm_gpio_template;
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+ pctrl->intr_target_use_scm = of_device_is_compatible(
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+ pctrl->dev->of_node,
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+ "qcom,ipq8064-pinctrl");
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raw_spin_lock_init(&pctrl->lock);
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@@ -1154,6 +1181,8 @@ int msm_pinctrl_probe(struct platform_de
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pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(pctrl->regs[0]))
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return PTR_ERR(pctrl->regs[0]);
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+
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+ pctrl->phys_base[0] = res->start;
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}
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msm_pinctrl_setup_pm_reset(pctrl);
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@ -1,9 +1,15 @@
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From a3488aa9bed37c56e405967d44e821c484b5d6b9 Mon Sep 17 00:00:00 2001
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From: Ram Chandra Jangir <rjangir@codeaurora.org>
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Date: Fri, 28 Sep 2018 15:19:50 +0530
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Subject: [PATCH] ipq8064: pinctrl: Fixed missing RGMII pincontrol definitions
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From 8d8cec9bf6e9260397872785f249dfb59a417d08 Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Wed, 19 Feb 2020 18:59:39 +0100
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Subject: ipq8064: pinctrl: Fixed missing RGMII pincontrol definitions
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Add missing gpio definition for mdio and rgmii2.
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Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Link: https://lore.kernel.org/r/20200219175940.744-1-ansuelsmth@gmail.com
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Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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---
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drivers/pinctrl/qcom/pinctrl-ipq8064.c | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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@ -1,13 +1,16 @@
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From a16fcf911a020e46439a3bb3e702463fc3159831 Mon Sep 17 00:00:00 2001
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From 1aec193ea41d672d11592714cdda8167eb3b38fc Mon Sep 17 00:00:00 2001
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From: Abhishek Sahu <absahu@codeaurora.org>
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Date: Wed, 18 Nov 2015 12:38:56 +0530
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Subject: [PATCH 62/69] ipq806x: gcc: Added the enable regs and mask for PRNG
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Date: Wed, 18 Mar 2020 14:16:56 +0100
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Subject: ipq806x: gcc: Added the enable regs and mask for PRNG
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kernel got hanged while reading from /dev/hwrng at the
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Kernel got hanged while reading from /dev/hwrng at the
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time of PRNG clock enable
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Change-Id: I89856c7e19e6639508e6a2774304583a3ec91172
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Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global clock controller (GCC)"
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Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Link: https://lkml.kernel.org/r/20200318131657.345-1-ansuelsmth@gmail.com
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/qcom/gcc-ipq806x.c | 2 ++
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1 file changed, 2 insertions(+)
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@ -1,9 +1,17 @@
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From ef10381ca4d01848ebedb4afb2c78feb8052f103 Mon Sep 17 00:00:00 2001
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From: Adrian Panella <ianchi74@outlook.com>
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Date: Thu, 9 Mar 2017 08:26:54 +0100
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Subject: [PATCH 53/69] regulator: add smb208 support
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From b5f25304aece9f2e7eaab275bbb5461c666bf38c Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Wed, 19 Feb 2020 17:37:11 +0100
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Subject: regulator: add smb208 support
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Smb208 regulators are used on some ipq806x soc.
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Add support for it to make it avaiable on some routers
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that use it.
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Signed-off-by: Adrian Panella <ianchi74@outlook.com>
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Acked-by: Lee Jones <lee.jones@linaro.org>
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Link: https://lore.kernel.org/r/20200219163711.479-1-ansuelsmth@gmail.com
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Signed-off-by: Mark Brown <broonie@kernel.org>
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---
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Documentation/devicetree/bindings/mfd/qcom-rpm.txt | 4 ++++
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drivers/regulator/qcom_rpm-regulator.c | 9 +++++++++
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