fix up remaining parts for the brcm47xx-2.6 port (tested on wgt634u), nuke the old brcm-2.6 port, close #1312, #1451
SVN-Revision: 6564v19.07.3_mercusys_ac12_duma
Felix Fietkau
17 years ago
parent
53a5d4131f
commit
dcfbd5f656
@ -1,25 +0,0 @@
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#
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# Copyright (C) 2006 OpenWrt.org
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#
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# This is free software, licensed under the GNU General Public License v2.
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# See /LICENSE for more information.
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#
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include $(TOPDIR)/rules.mk
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ARCH:=mipsel
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BOARD:=brcm
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BOARDNAME:=Broadcom BCM947xx/953xx
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FEATURES:=squashfs
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define Target/Description
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Build firmware images for Broadcom based routers
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(e.g. Netgear WGT634U)
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endef
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include $(INCLUDE_DIR)/kernel-build.mk
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DEFAULT_PACKAGES += kmod-switch kmod-diag
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# include the profiles
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-include profiles/*.mk
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$(eval $(call BuildKernel))
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@ -1 +0,0 @@
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../brcm-2.4/base-files
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@ -1 +0,0 @@
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../brcm-2.4/base-files.mk
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@ -1,323 +0,0 @@
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CONFIG_32BIT=y
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# CONFIG_64BIT is not set
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# CONFIG_64BIT_PHYS_ADDR is not set
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# CONFIG_8139TOO is not set
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# CONFIG_ARPD is not set
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# CONFIG_ATMEL is not set
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CONFIG_B44=y
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CONFIG_BASE_SMALL=0
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CONFIG_BCM947XX=y
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# CONFIG_BONDING is not set
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# CONFIG_BRIDGE_NETFILTER is not set
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# CONFIG_BSD_DISKLABEL is not set
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# CONFIG_BSD_PROCESS_ACCT is not set
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# CONFIG_BT_HCIBCM203X is not set
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# CONFIG_BT_HCIBFUSB is not set
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# CONFIG_BT_HCIBPA10X is not set
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# CONFIG_BT_HCIVHCI is not set
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# CONFIG_CIFS_STATS is not set
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# CONFIG_CLS_U32_MARK is not set
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# CONFIG_CLS_U32_PERF is not set
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CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 init=/etc/preinit noinitrd console=ttyS0,115200"
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# CONFIG_CONFIGFS_FS is not set
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CONFIG_CONNECTOR=m
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# CONFIG_CPU_BIG_ENDIAN is not set
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CONFIG_CPU_HAS_LLSC=y
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CONFIG_CPU_HAS_PREFETCH=y
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CONFIG_CPU_HAS_SYNC=y
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CONFIG_CPU_LITTLE_ENDIAN=y
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CONFIG_CPU_MIPS32=y
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CONFIG_CPU_MIPS32_R1=y
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# CONFIG_CPU_MIPS32_R2 is not set
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# CONFIG_CPU_MIPS64_R1 is not set
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# CONFIG_CPU_MIPS64_R2 is not set
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CONFIG_CPU_MIPSR1=y
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# CONFIG_CPU_NEVADA is not set
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# CONFIG_CPU_R10000 is not set
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# CONFIG_CPU_R3000 is not set
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# CONFIG_CPU_R4300 is not set
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# CONFIG_CPU_R4X00 is not set
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# CONFIG_CPU_R5000 is not set
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# CONFIG_CPU_R5432 is not set
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# CONFIG_CPU_R6000 is not set
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# CONFIG_CPU_R8000 is not set
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# CONFIG_CPU_RM7000 is not set
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# CONFIG_CPU_RM9000 is not set
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# CONFIG_CPU_SB1 is not set
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CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
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CONFIG_CPU_SUPPORTS_HIGHMEM=y
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# CONFIG_CPU_TX39XX is not set
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# CONFIG_CPU_TX49XX is not set
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# CONFIG_CPU_VR41XX is not set
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# CONFIG_CRYPTO_ANUBIS is not set
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CONFIG_CRYPTO_BLKCIPHER=m
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# CONFIG_CRYPTO_BLOWFISH is not set
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# CONFIG_CRYPTO_CAST5 is not set
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# CONFIG_CRYPTO_CAST6 is not set
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CONFIG_CRYPTO_CBC=m
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# CONFIG_CRYPTO_CRC32C is not set
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CONFIG_CRYPTO_DES=m
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CONFIG_CRYPTO_HASH=y
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CONFIG_CRYPTO_HMAC=y
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# CONFIG_CRYPTO_KHAZAD is not set
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# CONFIG_CRYPTO_MD4 is not set
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CONFIG_CRYPTO_MD5=m
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# CONFIG_CRYPTO_NULL is not set
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# CONFIG_CRYPTO_SERPENT is not set
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# CONFIG_CRYPTO_SHA256 is not set
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# CONFIG_CRYPTO_SHA512 is not set
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# CONFIG_CRYPTO_TEA is not set
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# CONFIG_CRYPTO_TEST is not set
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# CONFIG_CRYPTO_TGR192 is not set
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# CONFIG_CRYPTO_TWOFISH is not set
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# CONFIG_CRYPTO_WP512 is not set
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# CONFIG_DDB5477 is not set
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# CONFIG_DM9000 is not set
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CONFIG_DMA_NEED_PCI_MAP_STATE=y
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CONFIG_DMA_NONCOHERENT=y
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# CONFIG_E100 is not set
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# CONFIG_FIRMWARE_EDID is not set
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CONFIG_GENERIC_FIND_NEXT_BIT=y
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# CONFIG_GEN_RTC is not set
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CONFIG_HW_HAS_PCI=y
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CONFIG_HW_RANDOM=y
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CONFIG_HZ=250
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# CONFIG_HZ_100 is not set
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# CONFIG_HZ_1024 is not set
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# CONFIG_HZ_128 is not set
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CONFIG_HZ_250=y
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# CONFIG_HZ_256 is not set
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# CONFIG_HZ_48 is not set
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# CONFIG_I2C is not set
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# CONFIG_IDE is not set
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# CONFIG_IKCONFIG is not set
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CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
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CONFIG_INITRAMFS_SOURCE=""
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CONFIG_INPUT=m
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# CONFIG_IP6_NF_MATCH_FRAG is not set
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# CONFIG_IP6_NF_MATCH_HL is not set
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# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set
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# CONFIG_IP6_NF_MATCH_OPTS is not set
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# CONFIG_IP6_NF_MATCH_RT is not set
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# CONFIG_IP6_NF_RAW is not set
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# CONFIG_IP6_NF_TARGET_HL is not set
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# CONFIG_IP6_NF_TARGET_LOG is not set
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CONFIG_IPW2200_QOS=y
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# CONFIG_IP_DCCP is not set
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# CONFIG_IP_NF_ARPTABLES is not set
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# CONFIG_IP_NF_CT_PROTO_SCTP is not set
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# CONFIG_IP_NF_MATCH_ADDRTYPE is not set
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# CONFIG_IP_NF_MATCH_HASHLIMIT is not set
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# CONFIG_IP_NF_TARGET_LOG is not set
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# CONFIG_IP_NF_TARGET_NETMAP is not set
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# CONFIG_IP_NF_TARGET_SAME is not set
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# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set
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# CONFIG_IP_ROUTE_VERBOSE is not set
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CONFIG_IRQ_CPU=y
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CONFIG_JFFS2_FS_DEBUG=0
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# CONFIG_LAN_SAA9730 is not set
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# CONFIG_LIBCRC32C is not set
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# CONFIG_LLC2 is not set
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# CONFIG_MACH_DECSTATION is not set
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# CONFIG_MACH_JAZZ is not set
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# CONFIG_MACH_VR41XX is not set
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CONFIG_MINI_FO=y
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CONFIG_MIPS=y
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# CONFIG_MIPS_ATLAS is not set
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# CONFIG_MIPS_BOSPORUS is not set
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# CONFIG_MIPS_COBALT is not set
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# CONFIG_MIPS_DB1000 is not set
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# CONFIG_MIPS_DB1100 is not set
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# CONFIG_MIPS_DB1200 is not set
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# CONFIG_MIPS_DB1500 is not set
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# CONFIG_MIPS_DB1550 is not set
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# CONFIG_MIPS_EV64120 is not set
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CONFIG_MIPS_L1_CACHE_SHIFT=5
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# CONFIG_MIPS_MALTA is not set
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# CONFIG_MIPS_MIRAGE is not set
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# CONFIG_MIPS_MTX1 is not set
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CONFIG_MIPS_MT_DISABLED=y
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# CONFIG_MIPS_MT_SMP is not set
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# CONFIG_MIPS_MT_SMTC is not set
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# CONFIG_MIPS_PB1000 is not set
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# CONFIG_MIPS_PB1100 is not set
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# CONFIG_MIPS_PB1200 is not set
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# CONFIG_MIPS_PB1500 is not set
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# CONFIG_MIPS_PB1550 is not set
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# CONFIG_MIPS_SEAD is not set
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# CONFIG_MIPS_SIM is not set
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# CONFIG_MIPS_VPE_LOADER is not set
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# CONFIG_MIPS_XXS1500 is not set
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# CONFIG_MOMENCO_JAGUAR_ATX is not set
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# CONFIG_MOMENCO_OCELOT is not set
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# CONFIG_MOMENCO_OCELOT_3 is not set
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# CONFIG_MOMENCO_OCELOT_C is not set
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# CONFIG_MOMENCO_OCELOT_G is not set
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CONFIG_MTD=y
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# CONFIG_MTD_ABSENT is not set
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CONFIG_MTD_BCM47XX=y
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CONFIG_MTD_BLOCK=y
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# CONFIG_MTD_BLOCK2MTD is not set
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CONFIG_MTD_CFI=y
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# CONFIG_MTD_CFI_ADV_OPTIONS is not set
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CONFIG_MTD_CFI_AMDSTD=y
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CONFIG_MTD_CFI_I1=y
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CONFIG_MTD_CFI_I2=y
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# CONFIG_MTD_CFI_I4 is not set
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# CONFIG_MTD_CFI_I8 is not set
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CONFIG_MTD_CFI_INTELEXT=y
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# CONFIG_MTD_CFI_STAA is not set
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CONFIG_MTD_CFI_UTIL=y
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CONFIG_MTD_CHAR=y
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# CONFIG_MTD_CMDLINE_PARTS is not set
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CONFIG_MTD_COMPLEX_MAPPINGS=y
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# CONFIG_MTD_CONCAT is not set
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# CONFIG_MTD_DEBUG is not set
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# CONFIG_MTD_DOC2000 is not set
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# CONFIG_MTD_DOC2001 is not set
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# CONFIG_MTD_DOC2001PLUS is not set
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CONFIG_MTD_GEN_PROBE=y
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# CONFIG_MTD_JEDECPROBE is not set
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CONFIG_MTD_MAP_BANK_WIDTH_1=y
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# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
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CONFIG_MTD_MAP_BANK_WIDTH_2=y
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# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
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CONFIG_MTD_MAP_BANK_WIDTH_4=y
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# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
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# CONFIG_MTD_MTDRAM is not set
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# CONFIG_MTD_NAND is not set
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# CONFIG_MTD_OBSOLETE_CHIPS is not set
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# CONFIG_MTD_ONENAND is not set
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CONFIG_MTD_PARTITIONS=y
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# CONFIG_MTD_PCI is not set
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# CONFIG_MTD_PHRAM is not set
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# CONFIG_MTD_PHYSMAP is not set
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# CONFIG_MTD_PLATRAM is not set
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# CONFIG_MTD_PMC551 is not set
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# CONFIG_MTD_RAM is not set
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# CONFIG_MTD_REDBOOT_PARTS is not set
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# CONFIG_MTD_ROM is not set
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# CONFIG_MTD_SLRAM is not set
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# CONFIG_MTD_SPLIT_ROOTFS is not set
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# CONFIG_NATSEMI is not set
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# CONFIG_NE2K_PCI is not set
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# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
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# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
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# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
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# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
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# CONFIG_NETFILTER_XT_MATCH_REALM is not set
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# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
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# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
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# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
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# CONFIG_NET_CLS_ACT is not set
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# CONFIG_NET_CLS_IND is not set
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# CONFIG_NET_EMATCH is not set
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# CONFIG_NET_IPGRE_BROADCAST is not set
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# CONFIG_NET_PKTGEN is not set
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# CONFIG_NET_SCH_NETEM is not set
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# CONFIG_NET_VENDOR_3COM is not set
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# CONFIG_NFSD is not set
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# CONFIG_NTFS_FS is not set
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# CONFIG_PAGE_SIZE_16KB is not set
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CONFIG_PAGE_SIZE_4KB=y
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# CONFIG_PAGE_SIZE_64KB is not set
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# CONFIG_PAGE_SIZE_8KB is not set
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CONFIG_PCMCIA=m
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# CONFIG_PMC_YOSEMITE is not set
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# CONFIG_PNX8550_JBS is not set
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# CONFIG_PNX8550_V2PCI is not set
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# CONFIG_PPP_MULTILINK is not set
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# CONFIG_PPP_SYNC_TTY is not set
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# CONFIG_PROC_KCORE is not set
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# CONFIG_ROMFS_FS is not set
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# CONFIG_RTC is not set
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CONFIG_RWSEM_GENERIC_SPINLOCK=y
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CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
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# CONFIG_SCSI_MULTI_LUN is not set
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# CONFIG_SERIAL_8250_DETECT_IRQ is not set
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CONFIG_SERIAL_8250_EXTENDED=y
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# CONFIG_SERIAL_8250_MANY_PORTS is not set
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# CONFIG_SERIAL_8250_RSA is not set
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CONFIG_SERIAL_8250_SHARE_IRQ=y
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# CONFIG_SGI_IP22 is not set
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# CONFIG_SGI_IP27 is not set
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# CONFIG_SGI_IP32 is not set
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# CONFIG_SIBYTE_BIGSUR is not set
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# CONFIG_SIBYTE_CARMEL is not set
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# CONFIG_SIBYTE_CRHINE is not set
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# CONFIG_SIBYTE_CRHONE is not set
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# CONFIG_SIBYTE_LITTLESUR is not set
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# CONFIG_SIBYTE_PTSWARM is not set
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# CONFIG_SIBYTE_RHONE is not set
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# CONFIG_SIBYTE_SENTOSA is not set
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# CONFIG_SIBYTE_SWARM is not set
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# CONFIG_SND_MIXER_OSS is not set
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# CONFIG_SND_PCM_OSS is not set
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# CONFIG_SPARSEMEM_STATIC is not set
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CONFIG_SYS_HAS_CPU_MIPS32_R1=y
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CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
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CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
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CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
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# CONFIG_TOSHIBA_JMR3927 is not set
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# CONFIG_TOSHIBA_RBTX4927 is not set
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# CONFIG_TOSHIBA_RBTX4938 is not set
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CONFIG_TRAD_SIGNALS=y
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# CONFIG_UNUSED_SYMBOLS is not set
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# CONFIG_USB_CATC is not set
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CONFIG_USB_EHCI_HCD=m
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# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
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CONFIG_USB_EHCI_SPLIT_ISO=y
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# CONFIG_USB_EHCI_TT_NEWSCHED is not set
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# CONFIG_USB_KAWETH is not set
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CONFIG_USB_OHCI_HCD=m
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# CONFIG_USB_PEGASUS is not set
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# CONFIG_USB_RTL8150 is not set
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# CONFIG_USB_SERIAL_AIRCABLE is not set
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# CONFIG_USB_SERIAL_AIRPRIME is not set
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# CONFIG_USB_SERIAL_ARK3116 is not set
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# CONFIG_USB_SERIAL_CP2101 is not set
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# CONFIG_USB_SERIAL_CYBERJACK is not set
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# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
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# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
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# CONFIG_USB_SERIAL_EDGEPORT is not set
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# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
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# CONFIG_USB_SERIAL_EMPEG is not set
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# CONFIG_USB_SERIAL_FUNSOFT is not set
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# CONFIG_USB_SERIAL_GARMIN is not set
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# CONFIG_USB_SERIAL_GENERIC is not set
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# CONFIG_USB_SERIAL_HP4X is not set
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# CONFIG_USB_SERIAL_IPAQ is not set
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# CONFIG_USB_SERIAL_IPW is not set
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# CONFIG_USB_SERIAL_IR is not set
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# CONFIG_USB_SERIAL_KEYSPAN is not set
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# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
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# CONFIG_USB_SERIAL_KLSI is not set
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# CONFIG_USB_SERIAL_KOBIL_SCT is not set
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# CONFIG_USB_SERIAL_MCT_U232 is not set
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# CONFIG_USB_SERIAL_MOS7720 is not set
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# CONFIG_USB_SERIAL_MOS7840 is not set
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# CONFIG_USB_SERIAL_NAVMAN is not set
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# CONFIG_USB_SERIAL_OMNINET is not set
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# CONFIG_USB_SERIAL_OPTION is not set
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# CONFIG_USB_SERIAL_SAFE is not set
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# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
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# CONFIG_USB_SERIAL_TI is not set
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# CONFIG_USB_SERIAL_WHITEHEAT is not set
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# CONFIG_USB_SERIAL_XIRCOM is not set
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# CONFIG_USB_STORAGE_ALAUDA is not set
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# CONFIG_USB_STORAGE_DATAFAB is not set
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||||
# CONFIG_USB_STORAGE_DPCM is not set
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||||
# CONFIG_USB_STORAGE_FREECOM is not set
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||||
# CONFIG_USB_STORAGE_JUMPSHOT is not set
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# CONFIG_USB_STORAGE_KARMA is not set
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# CONFIG_USB_STORAGE_SDDR09 is not set
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# CONFIG_USB_STORAGE_SDDR55 is not set
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# CONFIG_USB_STORAGE_USBAT is not set
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CONFIG_USB_UHCI_HCD=m
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# CONFIG_USB_USBNET is not set
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# CONFIG_USB_USBNET_MII is not set
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# CONFIG_VIA_RHINE is not set
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# CONFIG_VIDEO_CX2341X is not set
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CONFIG_VIDEO_DEV=m
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# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
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# CONFIG_WATCHDOG is not set
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@ -1 +0,0 @@
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../brcm-2.4/image
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File diff suppressed because it is too large
Load Diff
@ -1,521 +0,0 @@
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diff -urN linux-2.6.19.ref/drivers/mtd/maps/bcm47xx-flash.c linux-2.6.19/drivers/mtd/maps/bcm47xx-flash.c
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--- linux-2.6.19.ref/drivers/mtd/maps/bcm47xx-flash.c 1970-01-01 01:00:00.000000000 +0100
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+++ linux-2.6.19/drivers/mtd/maps/bcm47xx-flash.c 2006-12-04 21:33:58.000000000 +0100
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@@ -0,0 +1,490 @@
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+/*
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+ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
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+ * Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
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+ * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
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+ *
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+ * original functions for finding root filesystem from Mike Baker
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
|
||||
+ * Free Software Foundation; either version 2 of the License, or (at your
|
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+ * option) any later version.
|
||||
+ *
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||||
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
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+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
+ *
|
||||
+ * You should have received a copy of the GNU General Public License along
|
||||
+ * with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
+ *
|
||||
+ * Copyright 2001-2003, Broadcom Corporation
|
||||
+ * All Rights Reserved.
|
||||
+ *
|
||||
+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
+ *
|
||||
+ * Flash mapping for BCM947XX boards
|
||||
+ */
|
||||
+
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/types.h>
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/wait.h>
|
||||
+#include <linux/autoconf.h>
|
||||
+#include <linux/mtd/mtd.h>
|
||||
+#include <linux/mtd/map.h>
|
||||
+#ifdef CONFIG_MTD_PARTITIONS
|
||||
+#include <linux/mtd/partitions.h>
|
||||
+#endif
|
||||
+#include <linux/squashfs_fs.h>
|
||||
+#include <linux/jffs2.h>
|
||||
+#include <linux/crc32.h>
|
||||
+#include <asm/io.h>
|
||||
+
|
||||
+#include <typedefs.h>
|
||||
+#include <osl.h>
|
||||
+#include <bcmnvram.h>
|
||||
+#include <bcmutils.h>
|
||||
+#include <sbconfig.h>
|
||||
+#include <sbchipc.h>
|
||||
+#include <sbutils.h>
|
||||
+#include <trxhdr.h>
|
||||
+
|
||||
+#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
|
||||
+#define NVRAM_SPACE 0x8000
|
||||
+#define WINDOW_ADDR 0x1fc00000
|
||||
+#define WINDOW_SIZE 0x400000
|
||||
+#define BUSWIDTH 2
|
||||
+
|
||||
+extern sb_t *sbh;
|
||||
+static struct mtd_info *bcm947xx_mtd;
|
||||
+
|
||||
+static void bcm947xx_map_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
|
||||
+{
|
||||
+#define MIPS_MEMCPY_ALIGN 4
|
||||
+ map_word ret;
|
||||
+ ssize_t transfer;
|
||||
+ ssize_t done = 0;
|
||||
+ if ((len >= MIPS_MEMCPY_ALIGN) && (!(from & (MIPS_MEMCPY_ALIGN - 1))) && (!(((unsigned int)to & (MIPS_MEMCPY_ALIGN - 1))))) {
|
||||
+ done = len & ~(MIPS_MEMCPY_ALIGN - 1);
|
||||
+ memcpy_fromio(to, map->virt + from, done);
|
||||
+ }
|
||||
+ while (done < len) {
|
||||
+ ret = map->read(map, from + done);
|
||||
+ transfer = len - done;
|
||||
+ if (transfer > map->bankwidth)
|
||||
+ transfer = map->bankwidth;
|
||||
+ memcpy((void *)((unsigned long)to + done), &ret.x[0], transfer);
|
||||
+ done += transfer;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static struct map_info bcm947xx_map = {
|
||||
+ name: "Physically mapped flash",
|
||||
+ size: WINDOW_SIZE,
|
||||
+ bankwidth: BUSWIDTH,
|
||||
+ phys: WINDOW_ADDR,
|
||||
+};
|
||||
+
|
||||
+#ifdef CONFIG_MTD_PARTITIONS
|
||||
+
|
||||
+static struct mtd_partition bcm947xx_parts[] = {
|
||||
+ { name: "cfe", offset: 0, size: 0, mask_flags: MTD_WRITEABLE, },
|
||||
+ { name: "linux", offset: 0, size: 0, },
|
||||
+ { name: "rootfs", offset: 0, size: 0, },
|
||||
+ { name: "nvram", offset: 0, size: 0, },
|
||||
+ { name: "OpenWrt", offset: 0, size: 0, },
|
||||
+ { name: NULL, },
|
||||
+};
|
||||
+
|
||||
+static int __init
|
||||
+find_cfe_size(struct mtd_info *mtd, size_t size)
|
||||
+{
|
||||
+ struct trx_header *trx;
|
||||
+ unsigned char buf[512];
|
||||
+ int off;
|
||||
+ size_t len;
|
||||
+ int blocksize;
|
||||
+
|
||||
+ trx = (struct trx_header *) buf;
|
||||
+
|
||||
+ blocksize = mtd->erasesize;
|
||||
+ if (blocksize < 0x10000)
|
||||
+ blocksize = 0x10000;
|
||||
+
|
||||
+ for (off = (128*1024); off < size; off += blocksize) {
|
||||
+ memset(buf, 0xe5, sizeof(buf));
|
||||
+
|
||||
+ /*
|
||||
+ * Read into buffer
|
||||
+ */
|
||||
+ if (mtd->read(mtd, off, sizeof(buf), &len, buf) ||
|
||||
+ len != sizeof(buf))
|
||||
+ continue;
|
||||
+
|
||||
+ /* found a TRX header */
|
||||
+ if (le32_to_cpu(trx->magic) == TRX_MAGIC) {
|
||||
+ goto found;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ printk(KERN_NOTICE
|
||||
+ "%s: Couldn't find bootloader size\n",
|
||||
+ mtd->name);
|
||||
+ return -1;
|
||||
+
|
||||
+ found:
|
||||
+ printk(KERN_NOTICE "bootloader size: %d\n", off);
|
||||
+ return off;
|
||||
+
|
||||
+}
|
||||
+
|
||||
+/*
|
||||
+ * Copied from mtdblock.c
|
||||
+ *
|
||||
+ * Cache stuff...
|
||||
+ *
|
||||
+ * Since typical flash erasable sectors are much larger than what Linux's
|
||||
+ * buffer cache can handle, we must implement read-modify-write on flash
|
||||
+ * sectors for each block write requests. To avoid over-erasing flash sectors
|
||||
+ * and to speed things up, we locally cache a whole flash sector while it is
|
||||
+ * being written to until a different sector is required.
|
||||
+ */
|
||||
+
|
||||
+static void erase_callback(struct erase_info *done)
|
||||
+{
|
||||
+ wait_queue_head_t *wait_q = (wait_queue_head_t *)done->priv;
|
||||
+ wake_up(wait_q);
|
||||
+}
|
||||
+
|
||||
+static int erase_write (struct mtd_info *mtd, unsigned long pos,
|
||||
+ int len, const char *buf)
|
||||
+{
|
||||
+ struct erase_info erase;
|
||||
+ DECLARE_WAITQUEUE(wait, current);
|
||||
+ wait_queue_head_t wait_q;
|
||||
+ size_t retlen;
|
||||
+ int ret;
|
||||
+
|
||||
+ /*
|
||||
+ * First, let's erase the flash block.
|
||||
+ */
|
||||
+
|
||||
+ init_waitqueue_head(&wait_q);
|
||||
+ erase.mtd = mtd;
|
||||
+ erase.callback = erase_callback;
|
||||
+ erase.addr = pos;
|
||||
+ erase.len = len;
|
||||
+ erase.priv = (u_long)&wait_q;
|
||||
+
|
||||
+ set_current_state(TASK_INTERRUPTIBLE);
|
||||
+ add_wait_queue(&wait_q, &wait);
|
||||
+
|
||||
+ ret = mtd->erase(mtd, &erase);
|
||||
+ if (ret) {
|
||||
+ set_current_state(TASK_RUNNING);
|
||||
+ remove_wait_queue(&wait_q, &wait);
|
||||
+ printk (KERN_WARNING "erase of region [0x%lx, 0x%x] "
|
||||
+ "on \"%s\" failed\n",
|
||||
+ pos, len, mtd->name);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ schedule(); /* Wait for erase to finish. */
|
||||
+ remove_wait_queue(&wait_q, &wait);
|
||||
+
|
||||
+ /*
|
||||
+ * Next, writhe data to flash.
|
||||
+ */
|
||||
+
|
||||
+ ret = mtd->write(mtd, pos, len, &retlen, buf);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+ if (retlen != len)
|
||||
+ return -EIO;
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+
|
||||
+
|
||||
+
|
||||
+static int __init
|
||||
+find_root(struct mtd_info *mtd, size_t size, struct mtd_partition *part)
|
||||
+{
|
||||
+ struct trx_header trx, *trx2;
|
||||
+ unsigned char buf[512], *block;
|
||||
+ int off, blocksize;
|
||||
+ u32 i, crc = ~0;
|
||||
+ size_t len;
|
||||
+ struct squashfs_super_block *sb = (struct squashfs_super_block *) buf;
|
||||
+
|
||||
+ blocksize = mtd->erasesize;
|
||||
+ if (blocksize < 0x10000)
|
||||
+ blocksize = 0x10000;
|
||||
+
|
||||
+ for (off = (128*1024); off < size; off += blocksize) {
|
||||
+ memset(&trx, 0xe5, sizeof(trx));
|
||||
+
|
||||
+ /*
|
||||
+ * Read into buffer
|
||||
+ */
|
||||
+ if (mtd->read(mtd, off, sizeof(trx), &len, (char *) &trx) ||
|
||||
+ len != sizeof(trx))
|
||||
+ continue;
|
||||
+
|
||||
+ /* found a TRX header */
|
||||
+ if (le32_to_cpu(trx.magic) == TRX_MAGIC) {
|
||||
+ part->offset = le32_to_cpu(trx.offsets[2]) ? :
|
||||
+ le32_to_cpu(trx.offsets[1]);
|
||||
+ part->size = le32_to_cpu(trx.len);
|
||||
+
|
||||
+ part->size -= part->offset;
|
||||
+ part->offset += off;
|
||||
+
|
||||
+ goto found;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ printk(KERN_NOTICE
|
||||
+ "%s: Couldn't find root filesystem\n",
|
||||
+ mtd->name);
|
||||
+ return -1;
|
||||
+
|
||||
+ found:
|
||||
+ if (part->size == 0)
|
||||
+ return 0;
|
||||
+
|
||||
+ if (mtd->read(mtd, part->offset, sizeof(buf), &len, buf) || len != sizeof(buf))
|
||||
+ return 0;
|
||||
+
|
||||
+ if (*((__u32 *) buf) == SQUASHFS_MAGIC) {
|
||||
+ printk(KERN_INFO "%s: Filesystem type: squashfs, size=0x%x\n", mtd->name, (u32) sb->bytes_used);
|
||||
+
|
||||
+ /* Update the squashfs partition size based on the superblock info */
|
||||
+ part->size = sb->bytes_used;
|
||||
+ len = part->offset + part->size;
|
||||
+ len += (mtd->erasesize - 1);
|
||||
+ len &= ~(mtd->erasesize - 1);
|
||||
+ part->size = len - part->offset;
|
||||
+ } else if (*((__u16 *) buf) == JFFS2_MAGIC_BITMASK) {
|
||||
+ printk(KERN_INFO "%s: Filesystem type: jffs2\n", mtd->name);
|
||||
+
|
||||
+ /* Move the squashfs outside of the trx */
|
||||
+ part->size = 0;
|
||||
+ } else {
|
||||
+ printk(KERN_INFO "%s: Filesystem type: unknown\n", mtd->name);
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
+ if (trx.len != part->offset + part->size - off) {
|
||||
+ /* Update the trx offsets and length */
|
||||
+ trx.len = part->offset + part->size - off;
|
||||
+
|
||||
+ /* Update the trx crc32 */
|
||||
+ for (i = (u32) &(((struct trx_header *)NULL)->flag_version); i <= trx.len; i += sizeof(buf)) {
|
||||
+ if (mtd->read(mtd, off + i, sizeof(buf), &len, buf) || len != sizeof(buf))
|
||||
+ return 0;
|
||||
+ crc = crc32_le(crc, buf, min(sizeof(buf), trx.len - i));
|
||||
+ }
|
||||
+ trx.crc32 = crc;
|
||||
+
|
||||
+ /* read first eraseblock from the trx */
|
||||
+ block = kmalloc(mtd->erasesize, GFP_KERNEL);
|
||||
+ trx2 = (struct trx_header *) block;
|
||||
+ if (mtd->read(mtd, off, mtd->erasesize, &len, block) || len != mtd->erasesize) {
|
||||
+ printk("Error accessing the first trx eraseblock\n");
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
+ printk("Updating TRX offsets and length:\n");
|
||||
+ printk("old trx = [0x%08x, 0x%08x, 0x%08x], len=0x%08x crc32=0x%08x\n", trx2->offsets[0], trx2->offsets[1], trx2->offsets[2], trx2->len, trx2->crc32);
|
||||
+ printk("new trx = [0x%08x, 0x%08x, 0x%08x], len=0x%08x crc32=0x%08x\n", trx.offsets[0], trx.offsets[1], trx.offsets[2], trx.len, trx.crc32);
|
||||
+
|
||||
+ /* Write updated trx header to the flash */
|
||||
+ memcpy(block, &trx, sizeof(trx));
|
||||
+ if (mtd->unlock)
|
||||
+ mtd->unlock(mtd, off, mtd->erasesize);
|
||||
+ erase_write(mtd, off, mtd->erasesize, block);
|
||||
+ if (mtd->sync)
|
||||
+ mtd->sync(mtd);
|
||||
+ kfree(block);
|
||||
+ printk("Done\n");
|
||||
+ }
|
||||
+
|
||||
+ return part->size;
|
||||
+}
|
||||
+
|
||||
+struct mtd_partition * __init
|
||||
+init_mtd_partitions(struct mtd_info *mtd, size_t size)
|
||||
+{
|
||||
+ int cfe_size;
|
||||
+
|
||||
+ if ((cfe_size = find_cfe_size(mtd,size)) < 0)
|
||||
+ return NULL;
|
||||
+
|
||||
+ /* boot loader */
|
||||
+ bcm947xx_parts[0].offset = 0;
|
||||
+ bcm947xx_parts[0].size = cfe_size;
|
||||
+
|
||||
+ /* nvram */
|
||||
+ if (cfe_size != 384 * 1024) {
|
||||
+ bcm947xx_parts[3].offset = size - ROUNDUP(NVRAM_SPACE, mtd->erasesize);
|
||||
+ bcm947xx_parts[3].size = ROUNDUP(NVRAM_SPACE, mtd->erasesize);
|
||||
+ } else {
|
||||
+ /* nvram (old 128kb config partition on netgear wgt634u) */
|
||||
+ bcm947xx_parts[3].offset = bcm947xx_parts[0].size;
|
||||
+ bcm947xx_parts[3].size = ROUNDUP(NVRAM_SPACE, mtd->erasesize);
|
||||
+ }
|
||||
+
|
||||
+ /* linux (kernel and rootfs) */
|
||||
+ if (cfe_size != 384 * 1024) {
|
||||
+ bcm947xx_parts[1].offset = bcm947xx_parts[0].size;
|
||||
+ bcm947xx_parts[1].size = bcm947xx_parts[3].offset -
|
||||
+ bcm947xx_parts[1].offset;
|
||||
+ } else {
|
||||
+ /* do not count the elf loader, which is on one block */
|
||||
+ bcm947xx_parts[1].offset = bcm947xx_parts[0].size +
|
||||
+ bcm947xx_parts[3].size + mtd->erasesize;
|
||||
+ bcm947xx_parts[1].size = size -
|
||||
+ bcm947xx_parts[0].size -
|
||||
+ (2*bcm947xx_parts[3].size) -
|
||||
+ mtd->erasesize;
|
||||
+ }
|
||||
+
|
||||
+ /* find and size rootfs */
|
||||
+ if (find_root(mtd,size,&bcm947xx_parts[2])==0) {
|
||||
+ /* entirely jffs2 */
|
||||
+ bcm947xx_parts[4].name = NULL;
|
||||
+ bcm947xx_parts[2].size = size - bcm947xx_parts[2].offset -
|
||||
+ bcm947xx_parts[3].size;
|
||||
+ } else {
|
||||
+ /* legacy setup */
|
||||
+ /* calculate leftover flash, and assign it to the jffs2 partition */
|
||||
+ if (cfe_size != 384 * 1024) {
|
||||
+ bcm947xx_parts[4].offset = bcm947xx_parts[2].offset +
|
||||
+ bcm947xx_parts[2].size;
|
||||
+ if ((bcm947xx_parts[4].offset % mtd->erasesize) > 0) {
|
||||
+ bcm947xx_parts[4].offset += mtd->erasesize -
|
||||
+ (bcm947xx_parts[4].offset % mtd->erasesize);
|
||||
+ }
|
||||
+ bcm947xx_parts[4].size = bcm947xx_parts[3].offset -
|
||||
+ bcm947xx_parts[4].offset;
|
||||
+ } else {
|
||||
+ bcm947xx_parts[4].offset = bcm947xx_parts[2].offset +
|
||||
+ bcm947xx_parts[2].size;
|
||||
+ if ((bcm947xx_parts[4].offset % mtd->erasesize) > 0) {
|
||||
+ bcm947xx_parts[4].offset += mtd->erasesize -
|
||||
+ (bcm947xx_parts[4].offset % mtd->erasesize);
|
||||
+ }
|
||||
+ bcm947xx_parts[4].size = size - bcm947xx_parts[3].size -
|
||||
+ bcm947xx_parts[4].offset;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ return bcm947xx_parts;
|
||||
+}
|
||||
+#endif
|
||||
+
|
||||
+int __init init_bcm947xx_map(void)
|
||||
+{
|
||||
+ uint coreidx;
|
||||
+ chipcregs_t *cc;
|
||||
+ uint32 fltype;
|
||||
+ uint window_addr = 0, window_size = 0;
|
||||
+ size_t size;
|
||||
+ int ret = 0;
|
||||
+#ifdef CONFIG_MTD_PARTITIONS
|
||||
+ struct mtd_partition *parts;
|
||||
+ int i;
|
||||
+#endif
|
||||
+
|
||||
+ coreidx = sb_coreidx(sbh);
|
||||
+
|
||||
+ /* Check strapping option if chipcommon exists */
|
||||
+ if ((cc = sb_setcore(sbh, SB_CC, 0))) {
|
||||
+ fltype = readl(&cc->capabilities) & CAP_FLASH_MASK;
|
||||
+ if (fltype == PFLASH) {
|
||||
+ bcm947xx_map.map_priv_2 = 1;
|
||||
+ window_addr = 0x1c000000;
|
||||
+ bcm947xx_map.size = window_size = 32 * 1024 * 1024;
|
||||
+ if ((readl(&cc->flash_config) & CC_CFG_DS) == 0)
|
||||
+ bcm947xx_map.bankwidth = 1;
|
||||
+ }
|
||||
+ } else {
|
||||
+ fltype = PFLASH;
|
||||
+ bcm947xx_map.map_priv_2 = 0;
|
||||
+ window_addr = WINDOW_ADDR;
|
||||
+ window_size = WINDOW_SIZE;
|
||||
+ }
|
||||
+
|
||||
+ sb_setcoreidx(sbh, coreidx);
|
||||
+
|
||||
+ if (fltype != PFLASH) {
|
||||
+ printk(KERN_ERR "pflash: found no supported devices\n");
|
||||
+ ret = -ENODEV;
|
||||
+ goto fail;
|
||||
+ }
|
||||
+ bcm947xx_map.virt = ioremap(window_addr, window_size);
|
||||
+
|
||||
+ if (!bcm947xx_map.virt) {
|
||||
+ printk("Failed to ioremap\n");
|
||||
+ return -EIO;
|
||||
+ }
|
||||
+ simple_map_init(&bcm947xx_map);
|
||||
+
|
||||
+ bcm947xx_map.copy_from = bcm947xx_map_copy_from;
|
||||
+
|
||||
+ if (!(bcm947xx_mtd = do_map_probe("cfi_probe", &bcm947xx_map))) {
|
||||
+ printk("Failed to do_map_probe\n");
|
||||
+ iounmap((void *)bcm947xx_map.virt);
|
||||
+ return -ENXIO;
|
||||
+ }
|
||||
+
|
||||
+ bcm947xx_mtd->owner = THIS_MODULE;
|
||||
+
|
||||
+ size = bcm947xx_mtd->size;
|
||||
+
|
||||
+ printk(KERN_NOTICE "Flash device: 0x%x at 0x%x\n", size, WINDOW_ADDR);
|
||||
+
|
||||
+#ifdef CONFIG_MTD_PARTITIONS
|
||||
+ parts = init_mtd_partitions(bcm947xx_mtd, size);
|
||||
+ for (i = 0; parts[i].name; i++);
|
||||
+ ret = add_mtd_partitions(bcm947xx_mtd, parts, i);
|
||||
+ if (ret) {
|
||||
+ printk(KERN_ERR "Flash: add_mtd_partitions failed\n");
|
||||
+ goto fail;
|
||||
+ }
|
||||
+#endif
|
||||
+ return 0;
|
||||
+
|
||||
+ fail:
|
||||
+ if (bcm947xx_mtd)
|
||||
+ map_destroy(bcm947xx_mtd);
|
||||
+ if (bcm947xx_map.virt)
|
||||
+ iounmap((void *)bcm947xx_map.virt);
|
||||
+ bcm947xx_map.virt = 0;
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+void __exit cleanup_bcm947xx_map(void)
|
||||
+{
|
||||
+#ifdef CONFIG_MTD_PARTITIONS
|
||||
+ del_mtd_partitions(bcm947xx_mtd);
|
||||
+#endif
|
||||
+ map_destroy(bcm947xx_mtd);
|
||||
+ iounmap((void *)bcm947xx_map.virt);
|
||||
+}
|
||||
+
|
||||
+module_init(init_bcm947xx_map);
|
||||
+module_exit(cleanup_bcm947xx_map);
|
||||
diff -urN linux-2.6.19.ref/drivers/mtd/maps/Kconfig linux-2.6.19/drivers/mtd/maps/Kconfig
|
||||
--- linux-2.6.19.ref/drivers/mtd/maps/Kconfig 2006-11-29 22:57:37.000000000 +0100
|
||||
+++ linux-2.6.19/drivers/mtd/maps/Kconfig 2006-12-04 21:33:58.000000000 +0100
|
||||
@@ -299,6 +299,12 @@
|
||||
Mapping for the Flaga digital module. If you don't have one, ignore
|
||||
this setting.
|
||||
|
||||
+config MTD_BCM47XX
|
||||
+ tristate "BCM47xx flash device"
|
||||
+ depends on MIPS && MTD_CFI && BCM947XX
|
||||
+ help
|
||||
+ Support for the flash chips on the BCM947xx board.
|
||||
+
|
||||
config MTD_BEECH
|
||||
tristate "CFI Flash device mapped on IBM 405LP Beech"
|
||||
depends on MTD_CFI && BEECH
|
||||
diff -urN linux-2.6.19.ref/drivers/mtd/maps/Makefile linux-2.6.19/drivers/mtd/maps/Makefile
|
||||
--- linux-2.6.19.ref/drivers/mtd/maps/Makefile 2006-11-29 22:57:37.000000000 +0100
|
||||
+++ linux-2.6.19/drivers/mtd/maps/Makefile 2006-12-04 21:33:58.000000000 +0100
|
||||
@@ -29,6 +29,7 @@
|
||||
obj-$(CONFIG_MTD_PCMCIA) += pcmciamtd.o
|
||||
obj-$(CONFIG_MTD_RPXLITE) += rpxlite.o
|
||||
obj-$(CONFIG_MTD_TQM8XXL) += tqm8xxl.o
|
||||
+obj-$(CONFIG_MTD_BCM47XX) += bcm47xx-flash.o
|
||||
obj-$(CONFIG_MTD_SA1100) += sa1100-flash.o
|
||||
obj-$(CONFIG_MTD_IPAQ) += ipaq-flash.o
|
||||
obj-$(CONFIG_MTD_SBC_GXX) += sbc_gxx.o
|
||||
@ -1,369 +0,0 @@
|
||||
diff -urN linux-2.6.19.ref/arch/mips/kernel/genex.S linux-2.6.19/arch/mips/kernel/genex.S
|
||||
--- linux-2.6.19.ref/arch/mips/kernel/genex.S 2006-11-29 22:57:37.000000000 +0100
|
||||
+++ linux-2.6.19/arch/mips/kernel/genex.S 2006-12-04 21:34:09.000000000 +0100
|
||||
@@ -73,6 +73,10 @@
|
||||
.set push
|
||||
.set mips3
|
||||
.set noat
|
||||
+#ifdef CONFIG_BCM947XX
|
||||
+ nop
|
||||
+ nop
|
||||
+#endif
|
||||
mfc0 k1, CP0_CAUSE
|
||||
li k0, 31<<2
|
||||
andi k1, k1, 0x7c
|
||||
diff -urN linux-2.6.19.ref/arch/mips/mm/c-r4k.c linux-2.6.19/arch/mips/mm/c-r4k.c
|
||||
--- linux-2.6.19.ref/arch/mips/mm/c-r4k.c 2006-12-04 21:34:04.000000000 +0100
|
||||
+++ linux-2.6.19/arch/mips/mm/c-r4k.c 2006-12-04 21:34:09.000000000 +0100
|
||||
@@ -13,6 +13,15 @@
|
||||
#include <linux/mm.h>
|
||||
#include <linux/bitops.h>
|
||||
|
||||
+#ifdef CONFIG_BCM947XX
|
||||
+#include "../bcm947xx/include/typedefs.h"
|
||||
+#include "../bcm947xx/include/sbconfig.h"
|
||||
+#include "../bcm947xx/include/mipsinc.h"
|
||||
+#undef MTC0
|
||||
+#undef MFC0
|
||||
+#undef cache_op
|
||||
+#include <asm/paccess.h>
|
||||
+#endif
|
||||
#include <asm/bcache.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/cache.h>
|
||||
@@ -29,6 +38,9 @@
|
||||
#include <asm/cacheflush.h> /* for run_uncached() */
|
||||
|
||||
|
||||
+/* For enabling BCM4710 cache workarounds */
|
||||
+int bcm4710 = 0;
|
||||
+
|
||||
/*
|
||||
* Special Variant of smp_call_function for use by cache functions:
|
||||
*
|
||||
@@ -93,6 +105,9 @@
|
||||
{
|
||||
unsigned long dc_lsize = cpu_dcache_line_size();
|
||||
|
||||
+ if (bcm4710)
|
||||
+ r4k_blast_dcache_page = blast_dcache_page;
|
||||
+ else
|
||||
if (dc_lsize == 0)
|
||||
r4k_blast_dcache_page = (void *)cache_noop;
|
||||
else if (dc_lsize == 16)
|
||||
@@ -107,6 +122,9 @@
|
||||
{
|
||||
unsigned long dc_lsize = cpu_dcache_line_size();
|
||||
|
||||
+ if (bcm4710)
|
||||
+ r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
|
||||
+ else
|
||||
if (dc_lsize == 0)
|
||||
r4k_blast_dcache_page_indexed = (void *)cache_noop;
|
||||
else if (dc_lsize == 16)
|
||||
@@ -121,6 +139,9 @@
|
||||
{
|
||||
unsigned long dc_lsize = cpu_dcache_line_size();
|
||||
|
||||
+ if (bcm4710)
|
||||
+ r4k_blast_dcache = blast_dcache;
|
||||
+ else
|
||||
if (dc_lsize == 0)
|
||||
r4k_blast_dcache = (void *)cache_noop;
|
||||
else if (dc_lsize == 16)
|
||||
@@ -538,6 +559,9 @@
|
||||
r4k_blast_icache();
|
||||
else
|
||||
protected_blast_icache_range(start, end);
|
||||
+
|
||||
+ if (bcm4710)
|
||||
+ r4k_flush_cache_all();
|
||||
}
|
||||
|
||||
static void r4k_flush_icache_range(unsigned long start, unsigned long end)
|
||||
@@ -618,6 +642,8 @@
|
||||
unsigned long addr = (unsigned long) arg;
|
||||
|
||||
R4600_HIT_CACHEOP_WAR_IMPL;
|
||||
+ BCM4710_PROTECTED_FILL_TLB(addr);
|
||||
+ BCM4710_PROTECTED_FILL_TLB(addr + 4);
|
||||
if (dc_lsize)
|
||||
protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
|
||||
if (!cpu_icache_snoops_remote_store && scache_size)
|
||||
@@ -1135,6 +1161,16 @@
|
||||
static void __init coherency_setup(void)
|
||||
{
|
||||
change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
|
||||
+#ifdef CONFIG_BCM947XX
|
||||
+ if (BCM330X(current_cpu_data.processor_id)) {
|
||||
+ __u32 cm = read_c0_diag();
|
||||
+ /* Enable icache */
|
||||
+ cm |= (1 << 31);
|
||||
+ /* Enable dcache */
|
||||
+ cm |= (1 << 30);
|
||||
+ write_c0_diag(cm);
|
||||
+ }
|
||||
+#endif
|
||||
|
||||
/*
|
||||
* c0_status.cu=0 specifies that updates by the sc instruction use
|
||||
@@ -1173,6 +1209,15 @@
|
||||
|
||||
/* Default cache error handler for R4000 and R5000 family */
|
||||
set_uncached_handler (0x100, &except_vec2_generic, 0x80);
|
||||
+
|
||||
+ /* Check if special workarounds are required */
|
||||
+#ifdef CONFIG_BCM947XX
|
||||
+ if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) {
|
||||
+ printk("Enabling BCM4710A0 cache workarounds.\n");
|
||||
+ bcm4710 = 1;
|
||||
+ } else
|
||||
+#endif
|
||||
+ bcm4710 = 0;
|
||||
|
||||
probe_pcache();
|
||||
setup_scache();
|
||||
diff -urN linux-2.6.19.ref/arch/mips/mm/tlbex.c linux-2.6.19/arch/mips/mm/tlbex.c
|
||||
--- linux-2.6.19.ref/arch/mips/mm/tlbex.c 2006-12-04 21:33:48.000000000 +0100
|
||||
+++ linux-2.6.19/arch/mips/mm/tlbex.c 2006-12-04 21:34:09.000000000 +0100
|
||||
@@ -1174,6 +1174,10 @@
|
||||
#endif
|
||||
}
|
||||
|
||||
+#ifdef CONFIG_BCM947XX
|
||||
+extern int bcm4710;
|
||||
+#endif
|
||||
+
|
||||
static void __init build_r4000_tlb_refill_handler(void)
|
||||
{
|
||||
u32 *p = tlb_handler;
|
||||
@@ -1188,6 +1192,12 @@
|
||||
memset(relocs, 0, sizeof(relocs));
|
||||
memset(final_handler, 0, sizeof(final_handler));
|
||||
|
||||
+#ifdef CONFIG_BCM947XX
|
||||
+ if (bcm4710) {
|
||||
+ i_nop(&p);
|
||||
+ }
|
||||
+#endif
|
||||
+
|
||||
/*
|
||||
* create the plain linear handler
|
||||
*/
|
||||
diff -urN linux-2.6.19.ref/include/asm-mips/r4kcache.h linux-2.6.19/include/asm-mips/r4kcache.h
|
||||
--- linux-2.6.19.ref/include/asm-mips/r4kcache.h 2006-11-29 22:57:37.000000000 +0100
|
||||
+++ linux-2.6.19/include/asm-mips/r4kcache.h 2006-12-04 21:34:09.000000000 +0100
|
||||
@@ -17,6 +17,18 @@
|
||||
#include <asm/cpu-features.h>
|
||||
#include <asm/mipsmtregs.h>
|
||||
|
||||
+#ifdef CONFIG_BCM947XX
|
||||
+#define BCM4710_DUMMY_RREG() (((sbconfig_t *)(KSEG1ADDR(SB_ENUM_BASE + SBCONFIGOFF)))->sbimstate)
|
||||
+
|
||||
+#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
|
||||
+#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
|
||||
+#else
|
||||
+#define BCM4710_DUMMY_RREG()
|
||||
+
|
||||
+#define BCM4710_FILL_TLB(addr)
|
||||
+#define BCM4710_PROTECTED_FILL_TLB(addr)
|
||||
+#endif
|
||||
+
|
||||
/*
|
||||
* This macro return a properly sign-extended address suitable as base address
|
||||
* for indexed cache operations. Two issues here:
|
||||
@@ -150,6 +162,7 @@
|
||||
static inline void flush_dcache_line_indexed(unsigned long addr)
|
||||
{
|
||||
__dflush_prologue
|
||||
+ BCM4710_DUMMY_RREG();
|
||||
cache_op(Index_Writeback_Inv_D, addr);
|
||||
__dflush_epilogue
|
||||
}
|
||||
@@ -169,6 +182,7 @@
|
||||
static inline void flush_dcache_line(unsigned long addr)
|
||||
{
|
||||
__dflush_prologue
|
||||
+ BCM4710_DUMMY_RREG();
|
||||
cache_op(Hit_Writeback_Inv_D, addr);
|
||||
__dflush_epilogue
|
||||
}
|
||||
@@ -176,6 +190,7 @@
|
||||
static inline void invalidate_dcache_line(unsigned long addr)
|
||||
{
|
||||
__dflush_prologue
|
||||
+ BCM4710_DUMMY_RREG();
|
||||
cache_op(Hit_Invalidate_D, addr);
|
||||
__dflush_epilogue
|
||||
}
|
||||
@@ -208,6 +223,7 @@
|
||||
*/
|
||||
static inline void protected_flush_icache_line(unsigned long addr)
|
||||
{
|
||||
+ BCM4710_DUMMY_RREG();
|
||||
protected_cache_op(Hit_Invalidate_I, addr);
|
||||
}
|
||||
|
||||
@@ -219,6 +235,7 @@
|
||||
*/
|
||||
static inline void protected_writeback_dcache_line(unsigned long addr)
|
||||
{
|
||||
+ BCM4710_DUMMY_RREG();
|
||||
protected_cache_op(Hit_Writeback_Inv_D, addr);
|
||||
}
|
||||
|
||||
@@ -339,8 +356,52 @@
|
||||
: "r" (base), \
|
||||
"i" (op));
|
||||
|
||||
+static inline void blast_dcache(void)
|
||||
+{
|
||||
+ unsigned long start = KSEG0;
|
||||
+ unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
|
||||
+ unsigned long end = (start + dcache_size);
|
||||
+
|
||||
+ do {
|
||||
+ BCM4710_DUMMY_RREG();
|
||||
+ cache_op(Index_Writeback_Inv_D, start);
|
||||
+ start += current_cpu_data.dcache.linesz;
|
||||
+ } while(start < end);
|
||||
+}
|
||||
+
|
||||
+static inline void blast_dcache_page(unsigned long page)
|
||||
+{
|
||||
+ unsigned long start = page;
|
||||
+ unsigned long end = start + PAGE_SIZE;
|
||||
+
|
||||
+ BCM4710_FILL_TLB(start);
|
||||
+ do {
|
||||
+ BCM4710_DUMMY_RREG();
|
||||
+ cache_op(Hit_Writeback_Inv_D, start);
|
||||
+ start += current_cpu_data.dcache.linesz;
|
||||
+ } while(start < end);
|
||||
+}
|
||||
+
|
||||
+static inline void blast_dcache_page_indexed(unsigned long page)
|
||||
+{
|
||||
+ unsigned long start = page;
|
||||
+ unsigned long end = start + PAGE_SIZE;
|
||||
+ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
|
||||
+ unsigned long ws_end = current_cpu_data.dcache.ways <<
|
||||
+ current_cpu_data.dcache.waybit;
|
||||
+ unsigned long ws, addr;
|
||||
+ for (ws = 0; ws < ws_end; ws += ws_inc) {
|
||||
+ start = page + ws;
|
||||
+ for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
|
||||
+ BCM4710_DUMMY_RREG();
|
||||
+ cache_op(Index_Writeback_Inv_D, addr);
|
||||
+ }
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+
|
||||
/* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
|
||||
-#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \
|
||||
+#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, war) \
|
||||
static inline void blast_##pfx##cache##lsize(void) \
|
||||
{ \
|
||||
unsigned long start = INDEX_BASE; \
|
||||
@@ -352,6 +413,7 @@
|
||||
\
|
||||
__##pfx##flush_prologue \
|
||||
\
|
||||
+ war \
|
||||
for (ws = 0; ws < ws_end; ws += ws_inc) \
|
||||
for (addr = start; addr < end; addr += lsize * 32) \
|
||||
cache##lsize##_unroll32(addr|ws,indexop); \
|
||||
@@ -366,6 +428,7 @@
|
||||
\
|
||||
__##pfx##flush_prologue \
|
||||
\
|
||||
+ war \
|
||||
do { \
|
||||
cache##lsize##_unroll32(start,hitop); \
|
||||
start += lsize * 32; \
|
||||
@@ -384,6 +447,8 @@
|
||||
current_cpu_data.desc.waybit; \
|
||||
unsigned long ws, addr; \
|
||||
\
|
||||
+ war \
|
||||
+ \
|
||||
__##pfx##flush_prologue \
|
||||
\
|
||||
for (ws = 0; ws < ws_end; ws += ws_inc) \
|
||||
@@ -393,28 +458,30 @@
|
||||
__##pfx##flush_epilogue \
|
||||
}
|
||||
|
||||
-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
|
||||
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
|
||||
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
|
||||
-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
|
||||
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
|
||||
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
|
||||
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
|
||||
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
|
||||
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
|
||||
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
|
||||
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, BCM4710_FILL_TLB(start);)
|
||||
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
|
||||
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
|
||||
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, BCM4710_FILL_TLB(start);)
|
||||
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
|
||||
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, BCM4710_FILL_TLB(start);)
|
||||
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
|
||||
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
|
||||
|
||||
/* build blast_xxx_range, protected_blast_xxx_range */
|
||||
-#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
|
||||
+#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, war, war2) \
|
||||
static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
|
||||
unsigned long end) \
|
||||
{ \
|
||||
unsigned long lsize = cpu_##desc##_line_size(); \
|
||||
unsigned long addr = start & ~(lsize - 1); \
|
||||
unsigned long aend = (end - 1) & ~(lsize - 1); \
|
||||
+ war \
|
||||
\
|
||||
__##pfx##flush_prologue \
|
||||
\
|
||||
while (1) { \
|
||||
+ war2 \
|
||||
prot##cache_op(hitop, addr); \
|
||||
if (addr == aend) \
|
||||
break; \
|
||||
@@ -424,13 +491,13 @@
|
||||
__##pfx##flush_epilogue \
|
||||
}
|
||||
|
||||
-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
|
||||
-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
|
||||
-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
|
||||
-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
|
||||
-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
|
||||
+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
|
||||
+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_,, )
|
||||
+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_,, )
|
||||
+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D,, BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
|
||||
+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD,,, )
|
||||
/* blast_inv_dcache_range */
|
||||
-__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
|
||||
-__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
|
||||
+__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D,,,BCM4710_DUMMY_RREG();)
|
||||
+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
|
||||
|
||||
#endif /* _ASM_R4KCACHE_H */
|
||||
diff -urN linux-2.6.19.ref/include/asm-mips/stackframe.h linux-2.6.19/include/asm-mips/stackframe.h
|
||||
--- linux-2.6.19.ref/include/asm-mips/stackframe.h 2006-11-29 22:57:37.000000000 +0100
|
||||
+++ linux-2.6.19/include/asm-mips/stackframe.h 2006-12-04 21:34:09.000000000 +0100
|
||||
@@ -334,6 +334,10 @@
|
||||
.macro RESTORE_SP_AND_RET
|
||||
LONG_L sp, PT_R29(sp)
|
||||
.set mips3
|
||||
+#ifdef CONFIG_BCM947XX
|
||||
+ nop
|
||||
+ nop
|
||||
+#endif
|
||||
eret
|
||||
.set mips0
|
||||
.endm
|
||||
@ -1,699 +0,0 @@
|
||||
diff -urN linux-2.6.19.ref/drivers/net/b44.c linux-2.6.19/drivers/net/b44.c
|
||||
--- linux-2.6.19.ref/drivers/net/b44.c 2006-11-29 22:57:37.000000000 +0100
|
||||
+++ linux-2.6.19/drivers/net/b44.c 2006-12-04 21:34:14.000000000 +0100
|
||||
@@ -1,7 +1,9 @@
|
||||
-/* b44.c: Broadcom 4400 device driver.
|
||||
+/* b44.c: Broadcom 4400/47xx device driver.
|
||||
*
|
||||
* Copyright (C) 2002 David S. Miller (davem@redhat.com)
|
||||
- * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
|
||||
+ * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
|
||||
+ * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
|
||||
+ * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
|
||||
* Copyright (C) 2006 Broadcom Corporation.
|
||||
*
|
||||
* Distribute under GPL.
|
||||
@@ -32,6 +34,28 @@
|
||||
#define DRV_MODULE_VERSION "1.01"
|
||||
#define DRV_MODULE_RELDATE "Jun 16, 2006"
|
||||
|
||||
+#ifdef CONFIG_BCM947XX
|
||||
+extern char *nvram_get(char *name);
|
||||
+static inline void e_aton(char *str, char *dest)
|
||||
+{
|
||||
+ int i = 0;
|
||||
+
|
||||
+ if (str == NULL) {
|
||||
+ memset(dest, 0, 6);
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
+ for (;;) {
|
||||
+ dest[i++] = (char) simple_strtoul(str, NULL, 16);
|
||||
+ str += 2;
|
||||
+ if (!*str++ || i == 6)
|
||||
+ break;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static int b44_4713_instance;
|
||||
+#endif
|
||||
+
|
||||
#define B44_DEF_MSG_ENABLE \
|
||||
(NETIF_MSG_DRV | \
|
||||
NETIF_MSG_PROBE | \
|
||||
@@ -87,8 +111,8 @@
|
||||
static char version[] __devinitdata =
|
||||
DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
|
||||
|
||||
-MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller");
|
||||
-MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
|
||||
+MODULE_AUTHOR("Felix Fietkau, Florian Schirmer, Pekka Pietikainen, David S. Miller");
|
||||
+MODULE_DESCRIPTION("Broadcom 4400/47xx 10/100 PCI ethernet driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_VERSION(DRV_MODULE_VERSION);
|
||||
|
||||
@@ -103,6 +127,10 @@
|
||||
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
|
||||
{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
|
||||
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
|
||||
+#ifdef CONFIG_BCM947XX
|
||||
+ { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4713,
|
||||
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
|
||||
+#endif
|
||||
{ } /* terminate list with empty entry */
|
||||
};
|
||||
|
||||
@@ -141,17 +169,6 @@
|
||||
dma_desc_sync_size, dir);
|
||||
}
|
||||
|
||||
-static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
|
||||
-{
|
||||
- return readl(bp->regs + reg);
|
||||
-}
|
||||
-
|
||||
-static inline void bw32(const struct b44 *bp,
|
||||
- unsigned long reg, unsigned long val)
|
||||
-{
|
||||
- writel(val, bp->regs + reg);
|
||||
-}
|
||||
-
|
||||
static int b44_wait_bit(struct b44 *bp, unsigned long reg,
|
||||
u32 bit, unsigned long timeout, const int clear)
|
||||
{
|
||||
@@ -278,6 +295,10 @@
|
||||
break;
|
||||
};
|
||||
#endif
|
||||
+#ifdef CONFIG_BCM947XX
|
||||
+ if (bp->pdev->device == PCI_DEVICE_ID_BCM4713)
|
||||
+ return b44_4713_instance++;
|
||||
+#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -287,6 +308,30 @@
|
||||
== SBTMSLOW_CLOCK);
|
||||
}
|
||||
|
||||
+#ifdef CONFIG_BCM947XX
|
||||
+static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
|
||||
+{
|
||||
+ u32 val;
|
||||
+
|
||||
+ bw32(bp, B44_CAM_CTRL, (CAM_CTRL_READ |
|
||||
+ (index << CAM_CTRL_INDEX_SHIFT)));
|
||||
+
|
||||
+ b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
|
||||
+
|
||||
+ val = br32(bp, B44_CAM_DATA_LO);
|
||||
+
|
||||
+ data[2] = (val >> 24) & 0xFF;
|
||||
+ data[3] = (val >> 16) & 0xFF;
|
||||
+ data[4] = (val >> 8) & 0xFF;
|
||||
+ data[5] = (val >> 0) & 0xFF;
|
||||
+
|
||||
+ val = br32(bp, B44_CAM_DATA_HI);
|
||||
+
|
||||
+ data[0] = (val >> 8) & 0xFF;
|
||||
+ data[1] = (val >> 0) & 0xFF;
|
||||
+}
|
||||
+#endif
|
||||
+
|
||||
static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
|
||||
{
|
||||
u32 val;
|
||||
@@ -323,14 +368,14 @@
|
||||
bw32(bp, B44_IMASK, bp->imask);
|
||||
}
|
||||
|
||||
-static int b44_readphy(struct b44 *bp, int reg, u32 *val)
|
||||
+static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
|
||||
{
|
||||
int err;
|
||||
|
||||
bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
|
||||
bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
|
||||
(MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
|
||||
- (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
|
||||
+ (phy_addr << MDIO_DATA_PMD_SHIFT) |
|
||||
(reg << MDIO_DATA_RA_SHIFT) |
|
||||
(MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
|
||||
err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
|
||||
@@ -339,18 +384,34 @@
|
||||
return err;
|
||||
}
|
||||
|
||||
-static int b44_writephy(struct b44 *bp, int reg, u32 val)
|
||||
+static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
|
||||
{
|
||||
bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
|
||||
bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
|
||||
(MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
|
||||
- (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
|
||||
+ (phy_addr << MDIO_DATA_PMD_SHIFT) |
|
||||
(reg << MDIO_DATA_RA_SHIFT) |
|
||||
(MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
|
||||
(val & MDIO_DATA_DATA)));
|
||||
return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
|
||||
}
|
||||
|
||||
+static inline int b44_readphy(struct b44 *bp, int reg, u32 *val)
|
||||
+{
|
||||
+ if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
|
||||
+ return 0;
|
||||
+
|
||||
+ return __b44_readphy(bp, bp->phy_addr, reg, val);
|
||||
+}
|
||||
+
|
||||
+static inline int b44_writephy(struct b44 *bp, int reg, u32 val)
|
||||
+{
|
||||
+ if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
|
||||
+ return 0;
|
||||
+
|
||||
+ return __b44_writephy(bp, bp->phy_addr, reg, val);
|
||||
+}
|
||||
+
|
||||
/* miilib interface */
|
||||
/* FIXME FIXME: phy_id is ignored, bp->phy_addr use is unconditional
|
||||
* due to code existing before miilib use was added to this driver.
|
||||
@@ -379,6 +440,8 @@
|
||||
u32 val;
|
||||
int err;
|
||||
|
||||
+ if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
|
||||
+ return 0;
|
||||
err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
|
||||
if (err)
|
||||
return err;
|
||||
@@ -442,6 +505,22 @@
|
||||
u32 val;
|
||||
int err;
|
||||
|
||||
+#ifdef CONFIG_BCM947XX
|
||||
+ /*
|
||||
+ * workaround for bad hardware design in Linksys WAP54G v1.0
|
||||
+ * see https://dev.openwrt.org/ticket/146
|
||||
+ * check and reset bit "isolate"
|
||||
+ */
|
||||
+ if ((bp->pdev->device == PCI_DEVICE_ID_BCM4713) &&
|
||||
+ (atoi(nvram_get("boardnum")) == 2) &&
|
||||
+ (__b44_readphy(bp, 0, MII_BMCR, &val) == 0) &&
|
||||
+ (val & BMCR_ISOLATE) &&
|
||||
+ (__b44_writephy(bp, 0, MII_BMCR, val & ~BMCR_ISOLATE) != 0)) {
|
||||
+ printk(KERN_WARNING PFX "PHY: cannot reset MII transceiver isolate bit.\n");
|
||||
+ }
|
||||
+#endif
|
||||
+ if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
|
||||
+ return 0;
|
||||
if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
|
||||
goto out;
|
||||
if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
|
||||
@@ -537,6 +616,19 @@
|
||||
{
|
||||
u32 bmsr, aux;
|
||||
|
||||
+ if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
|
||||
+ bp->flags |= B44_FLAG_100_BASE_T;
|
||||
+ bp->flags |= B44_FLAG_FULL_DUPLEX;
|
||||
+ if (!netif_carrier_ok(bp->dev)) {
|
||||
+ u32 val = br32(bp, B44_TX_CTRL);
|
||||
+ val |= TX_CTRL_DUPLEX;
|
||||
+ bw32(bp, B44_TX_CTRL, val);
|
||||
+ netif_carrier_on(bp->dev);
|
||||
+ b44_link_report(bp);
|
||||
+ }
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
|
||||
!b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
|
||||
(bmsr != 0xffff)) {
|
||||
@@ -1292,9 +1384,10 @@
|
||||
bw32(bp, B44_DMARX_CTRL, 0);
|
||||
bp->rx_prod = bp->rx_cons = 0;
|
||||
} else {
|
||||
- ssb_pci_setup(bp, (bp->core_unit == 0 ?
|
||||
- SBINTVEC_ENET0 :
|
||||
- SBINTVEC_ENET1));
|
||||
+ if (bp->pdev->device != PCI_DEVICE_ID_BCM4713)
|
||||
+ ssb_pci_setup(bp, (bp->core_unit == 0 ?
|
||||
+ SBINTVEC_ENET0 :
|
||||
+ SBINTVEC_ENET1));
|
||||
}
|
||||
|
||||
ssb_core_reset(bp);
|
||||
@@ -1302,8 +1395,14 @@
|
||||
b44_clear_stats(bp);
|
||||
|
||||
/* Make PHY accessible. */
|
||||
- bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
|
||||
+ if (bp->pdev->device == PCI_DEVICE_ID_BCM4713)
|
||||
+ bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
|
||||
+ (((100000000 + (B44_MDC_RATIO / 2)) / B44_MDC_RATIO)
|
||||
+ & MDIO_CTRL_MAXF_MASK)));
|
||||
+ else
|
||||
+ bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
|
||||
(0x0d & MDIO_CTRL_MAXF_MASK)));
|
||||
+
|
||||
br32(bp, B44_MDIO_CTRL);
|
||||
|
||||
if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
|
||||
@@ -2034,18 +2133,297 @@
|
||||
.get_perm_addr = ethtool_op_get_perm_addr,
|
||||
};
|
||||
|
||||
+static int b44_ethtool_ioctl (struct net_device *dev, void __user *useraddr)
|
||||
+{
|
||||
+ struct b44 *bp = dev->priv;
|
||||
+ struct pci_dev *pci_dev = bp->pdev;
|
||||
+ u32 ethcmd;
|
||||
+
|
||||
+ if (copy_from_user (ðcmd, useraddr, sizeof (ethcmd)))
|
||||
+ return -EFAULT;
|
||||
+
|
||||
+ switch (ethcmd) {
|
||||
+ case ETHTOOL_GDRVINFO: {
|
||||
+ struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
|
||||
+ strcpy (info.driver, DRV_MODULE_NAME);
|
||||
+ strcpy (info.version, DRV_MODULE_VERSION);
|
||||
+ memset(&info.fw_version, 0, sizeof(info.fw_version));
|
||||
+ strcpy (info.bus_info, pci_name(pci_dev));
|
||||
+ info.eedump_len = 0;
|
||||
+ info.regdump_len = 0;
|
||||
+ if (copy_to_user (useraddr, &info, sizeof (info)))
|
||||
+ return -EFAULT;
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
+ case ETHTOOL_GSET: {
|
||||
+ struct ethtool_cmd cmd = { ETHTOOL_GSET };
|
||||
+
|
||||
+ if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
|
||||
+ return -EAGAIN;
|
||||
+ cmd.supported = (SUPPORTED_Autoneg);
|
||||
+ cmd.supported |= (SUPPORTED_100baseT_Half |
|
||||
+ SUPPORTED_100baseT_Full |
|
||||
+ SUPPORTED_10baseT_Half |
|
||||
+ SUPPORTED_10baseT_Full |
|
||||
+ SUPPORTED_MII);
|
||||
+
|
||||
+ cmd.advertising = 0;
|
||||
+ if (bp->flags & B44_FLAG_ADV_10HALF)
|
||||
+ cmd.advertising |= ADVERTISE_10HALF;
|
||||
+ if (bp->flags & B44_FLAG_ADV_10FULL)
|
||||
+ cmd.advertising |= ADVERTISE_10FULL;
|
||||
+ if (bp->flags & B44_FLAG_ADV_100HALF)
|
||||
+ cmd.advertising |= ADVERTISE_100HALF;
|
||||
+ if (bp->flags & B44_FLAG_ADV_100FULL)
|
||||
+ cmd.advertising |= ADVERTISE_100FULL;
|
||||
+ cmd.advertising |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
|
||||
+ cmd.speed = (bp->flags & B44_FLAG_100_BASE_T) ?
|
||||
+ SPEED_100 : SPEED_10;
|
||||
+ cmd.duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
|
||||
+ DUPLEX_FULL : DUPLEX_HALF;
|
||||
+ cmd.port = 0;
|
||||
+ cmd.phy_address = bp->phy_addr;
|
||||
+ cmd.transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
|
||||
+ XCVR_INTERNAL : XCVR_EXTERNAL;
|
||||
+ cmd.autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
|
||||
+ AUTONEG_DISABLE : AUTONEG_ENABLE;
|
||||
+ cmd.maxtxpkt = 0;
|
||||
+ cmd.maxrxpkt = 0;
|
||||
+ if (copy_to_user(useraddr, &cmd, sizeof(cmd)))
|
||||
+ return -EFAULT;
|
||||
+ return 0;
|
||||
+ }
|
||||
+ case ETHTOOL_SSET: {
|
||||
+ struct ethtool_cmd cmd;
|
||||
+
|
||||
+ if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
|
||||
+ return -EAGAIN;
|
||||
+
|
||||
+ if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
|
||||
+ return -EFAULT;
|
||||
+
|
||||
+ /* We do not support gigabit. */
|
||||
+ if (cmd.autoneg == AUTONEG_ENABLE) {
|
||||
+ if (cmd.advertising &
|
||||
+ (ADVERTISED_1000baseT_Half |
|
||||
+ ADVERTISED_1000baseT_Full))
|
||||
+ return -EINVAL;
|
||||
+ } else if ((cmd.speed != SPEED_100 &&
|
||||
+ cmd.speed != SPEED_10) ||
|
||||
+ (cmd.duplex != DUPLEX_HALF &&
|
||||
+ cmd.duplex != DUPLEX_FULL)) {
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ spin_lock_irq(&bp->lock);
|
||||
+
|
||||
+ if (cmd.autoneg == AUTONEG_ENABLE) {
|
||||
+ bp->flags &= ~B44_FLAG_FORCE_LINK;
|
||||
+ bp->flags &= ~(B44_FLAG_ADV_10HALF |
|
||||
+ B44_FLAG_ADV_10FULL |
|
||||
+ B44_FLAG_ADV_100HALF |
|
||||
+ B44_FLAG_ADV_100FULL);
|
||||
+ if (cmd.advertising & ADVERTISE_10HALF)
|
||||
+ bp->flags |= B44_FLAG_ADV_10HALF;
|
||||
+ if (cmd.advertising & ADVERTISE_10FULL)
|
||||
+ bp->flags |= B44_FLAG_ADV_10FULL;
|
||||
+ if (cmd.advertising & ADVERTISE_100HALF)
|
||||
+ bp->flags |= B44_FLAG_ADV_100HALF;
|
||||
+ if (cmd.advertising & ADVERTISE_100FULL)
|
||||
+ bp->flags |= B44_FLAG_ADV_100FULL;
|
||||
+ } else {
|
||||
+ bp->flags |= B44_FLAG_FORCE_LINK;
|
||||
+ if (cmd.speed == SPEED_100)
|
||||
+ bp->flags |= B44_FLAG_100_BASE_T;
|
||||
+ if (cmd.duplex == DUPLEX_FULL)
|
||||
+ bp->flags |= B44_FLAG_FULL_DUPLEX;
|
||||
+ }
|
||||
+
|
||||
+ b44_setup_phy(bp);
|
||||
+
|
||||
+ spin_unlock_irq(&bp->lock);
|
||||
+
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
+ case ETHTOOL_GMSGLVL: {
|
||||
+ struct ethtool_value edata = { ETHTOOL_GMSGLVL };
|
||||
+ edata.data = bp->msg_enable;
|
||||
+ if (copy_to_user(useraddr, &edata, sizeof(edata)))
|
||||
+ return -EFAULT;
|
||||
+ return 0;
|
||||
+ }
|
||||
+ case ETHTOOL_SMSGLVL: {
|
||||
+ struct ethtool_value edata;
|
||||
+ if (copy_from_user(&edata, useraddr, sizeof(edata)))
|
||||
+ return -EFAULT;
|
||||
+ bp->msg_enable = edata.data;
|
||||
+ return 0;
|
||||
+ }
|
||||
+ case ETHTOOL_NWAY_RST: {
|
||||
+ u32 bmcr;
|
||||
+ int r;
|
||||
+
|
||||
+ spin_lock_irq(&bp->lock);
|
||||
+ b44_readphy(bp, MII_BMCR, &bmcr);
|
||||
+ b44_readphy(bp, MII_BMCR, &bmcr);
|
||||
+ r = -EINVAL;
|
||||
+ if (bmcr & BMCR_ANENABLE) {
|
||||
+ b44_writephy(bp, MII_BMCR,
|
||||
+ bmcr | BMCR_ANRESTART);
|
||||
+ r = 0;
|
||||
+ }
|
||||
+ spin_unlock_irq(&bp->lock);
|
||||
+
|
||||
+ return r;
|
||||
+ }
|
||||
+ case ETHTOOL_GLINK: {
|
||||
+ struct ethtool_value edata = { ETHTOOL_GLINK };
|
||||
+ edata.data = netif_carrier_ok(bp->dev) ? 1 : 0;
|
||||
+ if (copy_to_user(useraddr, &edata, sizeof(edata)))
|
||||
+ return -EFAULT;
|
||||
+ return 0;
|
||||
+ }
|
||||
+ case ETHTOOL_GRINGPARAM: {
|
||||
+ struct ethtool_ringparam ering = { ETHTOOL_GRINGPARAM };
|
||||
+
|
||||
+ ering.rx_max_pending = B44_RX_RING_SIZE - 1;
|
||||
+ ering.rx_pending = bp->rx_pending;
|
||||
+
|
||||
+ /* XXX ethtool lacks a tx_max_pending, oops... */
|
||||
+
|
||||
+ if (copy_to_user(useraddr, &ering, sizeof(ering)))
|
||||
+ return -EFAULT;
|
||||
+ return 0;
|
||||
+ }
|
||||
+ case ETHTOOL_SRINGPARAM: {
|
||||
+ struct ethtool_ringparam ering;
|
||||
+
|
||||
+ if (copy_from_user(&ering, useraddr, sizeof(ering)))
|
||||
+ return -EFAULT;
|
||||
+
|
||||
+ if ((ering.rx_pending > B44_RX_RING_SIZE - 1) ||
|
||||
+ (ering.rx_mini_pending != 0) ||
|
||||
+ (ering.rx_jumbo_pending != 0) ||
|
||||
+ (ering.tx_pending > B44_TX_RING_SIZE - 1))
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ spin_lock_irq(&bp->lock);
|
||||
+
|
||||
+ bp->rx_pending = ering.rx_pending;
|
||||
+ bp->tx_pending = ering.tx_pending;
|
||||
+
|
||||
+ b44_halt(bp);
|
||||
+ b44_init_rings(bp);
|
||||
+ b44_init_hw(bp, 1);
|
||||
+ netif_wake_queue(bp->dev);
|
||||
+ spin_unlock_irq(&bp->lock);
|
||||
+
|
||||
+ b44_enable_ints(bp);
|
||||
+
|
||||
+ return 0;
|
||||
+ }
|
||||
+ case ETHTOOL_GPAUSEPARAM: {
|
||||
+ struct ethtool_pauseparam epause = { ETHTOOL_GPAUSEPARAM };
|
||||
+
|
||||
+ epause.autoneg =
|
||||
+ (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
|
||||
+ epause.rx_pause =
|
||||
+ (bp->flags & B44_FLAG_RX_PAUSE) != 0;
|
||||
+ epause.tx_pause =
|
||||
+ (bp->flags & B44_FLAG_TX_PAUSE) != 0;
|
||||
+ if (copy_to_user(useraddr, &epause, sizeof(epause)))
|
||||
+ return -EFAULT;
|
||||
+ return 0;
|
||||
+ }
|
||||
+ case ETHTOOL_SPAUSEPARAM: {
|
||||
+ struct ethtool_pauseparam epause;
|
||||
+
|
||||
+ if (copy_from_user(&epause, useraddr, sizeof(epause)))
|
||||
+ return -EFAULT;
|
||||
+
|
||||
+ spin_lock_irq(&bp->lock);
|
||||
+ if (epause.autoneg)
|
||||
+ bp->flags |= B44_FLAG_PAUSE_AUTO;
|
||||
+ else
|
||||
+ bp->flags &= ~B44_FLAG_PAUSE_AUTO;
|
||||
+ if (epause.rx_pause)
|
||||
+ bp->flags |= B44_FLAG_RX_PAUSE;
|
||||
+ else
|
||||
+ bp->flags &= ~B44_FLAG_RX_PAUSE;
|
||||
+ if (epause.tx_pause)
|
||||
+ bp->flags |= B44_FLAG_TX_PAUSE;
|
||||
+ else
|
||||
+ bp->flags &= ~B44_FLAG_TX_PAUSE;
|
||||
+ if (bp->flags & B44_FLAG_PAUSE_AUTO) {
|
||||
+ b44_halt(bp);
|
||||
+ b44_init_rings(bp);
|
||||
+ b44_init_hw(bp, 1);
|
||||
+ } else {
|
||||
+ __b44_set_flow_ctrl(bp, bp->flags);
|
||||
+ }
|
||||
+ spin_unlock_irq(&bp->lock);
|
||||
+
|
||||
+ b44_enable_ints(bp);
|
||||
+
|
||||
+ return 0;
|
||||
+ }
|
||||
+ };
|
||||
+
|
||||
+ return -EOPNOTSUPP;
|
||||
+}
|
||||
+
|
||||
static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
|
||||
{
|
||||
struct mii_ioctl_data *data = if_mii(ifr);
|
||||
struct b44 *bp = netdev_priv(dev);
|
||||
int err = -EINVAL;
|
||||
|
||||
- if (!netif_running(dev))
|
||||
+ if (bp->pdev->device != PCI_DEVICE_ID_BCM4713) {
|
||||
+ if (!netif_running(dev))
|
||||
+ goto out;
|
||||
+
|
||||
+ spin_lock_irq(&bp->lock);
|
||||
+ err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
|
||||
+ spin_unlock_irq(&bp->lock);
|
||||
goto out;
|
||||
+ }
|
||||
|
||||
- spin_lock_irq(&bp->lock);
|
||||
- err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
|
||||
- spin_unlock_irq(&bp->lock);
|
||||
+ switch (cmd) {
|
||||
+ case SIOCETHTOOL:
|
||||
+ return b44_ethtool_ioctl(dev, (void __user*) ifr->ifr_data);
|
||||
+
|
||||
+ case SIOCGMIIPHY:
|
||||
+ data->phy_id = bp->phy_addr;
|
||||
+
|
||||
+ /* fallthru */
|
||||
+ case SIOCGMIIREG: {
|
||||
+ u32 mii_regval;
|
||||
+ spin_lock_irq(&bp->lock);
|
||||
+ err = __b44_readphy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
|
||||
+ spin_unlock_irq(&bp->lock);
|
||||
+
|
||||
+ data->val_out = mii_regval;
|
||||
+
|
||||
+ return err;
|
||||
+ }
|
||||
+
|
||||
+ case SIOCSMIIREG:
|
||||
+ if (!capable(CAP_NET_ADMIN))
|
||||
+ return -EPERM;
|
||||
+
|
||||
+ spin_lock_irq(&bp->lock);
|
||||
+ err = __b44_writephy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
|
||||
+ spin_unlock_irq(&bp->lock);
|
||||
+
|
||||
+ return err;
|
||||
+
|
||||
+ default:
|
||||
+ break;
|
||||
+ };
|
||||
+ return -EOPNOTSUPP;
|
||||
+
|
||||
out:
|
||||
return err;
|
||||
}
|
||||
@@ -2065,27 +2443,60 @@
|
||||
static int __devinit b44_get_invariants(struct b44 *bp)
|
||||
{
|
||||
u8 eeprom[128];
|
||||
- int err;
|
||||
+ u8 buf[32];
|
||||
+ int err = 0;
|
||||
+ unsigned long flags;
|
||||
+
|
||||
+#ifdef CONFIG_BCM947XX
|
||||
+ if (bp->pdev->device == PCI_DEVICE_ID_BCM4713) {
|
||||
+ /*
|
||||
+ * BCM47xx boards don't have a EEPROM. The MAC is stored in
|
||||
+ * a NVRAM area somewhere in the flash memory.
|
||||
+ */
|
||||
+ sprintf(buf, "et%dmacaddr", b44_4713_instance);
|
||||
+ if (nvram_get(buf)) {
|
||||
+ e_aton(nvram_get(buf), bp->dev->dev_addr);
|
||||
+ } else {
|
||||
+ /*
|
||||
+ * Getting the MAC out of NVRAM failed. To make it work
|
||||
+ * here, we simply rely on the bootloader to write the
|
||||
+ * MAC into the CAM.
|
||||
+ */
|
||||
+ spin_lock_irqsave(&bp->lock, flags);
|
||||
+ __b44_cam_read(bp, bp->dev->dev_addr, 0);
|
||||
+ spin_unlock_irqrestore(&bp->lock, flags);
|
||||
+ }
|
||||
|
||||
- err = b44_read_eeprom(bp, &eeprom[0]);
|
||||
- if (err)
|
||||
- goto out;
|
||||
+ /*
|
||||
+ * BCM47xx boards don't have a PHY. Usually there is a switch
|
||||
+ * chip with multiple PHYs connected to the PHY port.
|
||||
+ */
|
||||
+ bp->phy_addr = B44_PHY_ADDR_NO_PHY;
|
||||
+ bp->dma_offset = 0;
|
||||
+ } else
|
||||
+#endif
|
||||
+ {
|
||||
+ err = b44_read_eeprom(bp, &eeprom[0]);
|
||||
+ if (err)
|
||||
+ goto out;
|
||||
|
||||
- bp->dev->dev_addr[0] = eeprom[79];
|
||||
- bp->dev->dev_addr[1] = eeprom[78];
|
||||
- bp->dev->dev_addr[2] = eeprom[81];
|
||||
- bp->dev->dev_addr[3] = eeprom[80];
|
||||
- bp->dev->dev_addr[4] = eeprom[83];
|
||||
- bp->dev->dev_addr[5] = eeprom[82];
|
||||
+ bp->dev->dev_addr[0] = eeprom[79];
|
||||
+ bp->dev->dev_addr[1] = eeprom[78];
|
||||
+ bp->dev->dev_addr[2] = eeprom[81];
|
||||
+ bp->dev->dev_addr[3] = eeprom[80];
|
||||
+ bp->dev->dev_addr[4] = eeprom[83];
|
||||
+ bp->dev->dev_addr[5] = eeprom[82];
|
||||
|
||||
- if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
|
||||
- printk(KERN_ERR PFX "Invalid MAC address found in EEPROM\n");
|
||||
- return -EINVAL;
|
||||
- }
|
||||
+ if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
|
||||
+ printk(KERN_ERR PFX "Invalid MAC address found in EEPROM\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
|
||||
- memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
|
||||
+ memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
|
||||
|
||||
- bp->phy_addr = eeprom[90] & 0x1f;
|
||||
+ bp->phy_addr = eeprom[90] & 0x1f;
|
||||
+ bp->dma_offset = SB_PCI_DMA;
|
||||
+ }
|
||||
|
||||
/* With this, plus the rx_header prepended to the data by the
|
||||
* hardware, we'll land the ethernet header on a 2-byte boundary.
|
||||
@@ -2095,7 +2506,6 @@
|
||||
bp->imask = IMASK_DEF;
|
||||
|
||||
bp->core_unit = ssb_core_unit(bp);
|
||||
- bp->dma_offset = SB_PCI_DMA;
|
||||
|
||||
/* XXX - really required?
|
||||
bp->flags |= B44_FLAG_BUGGY_TXPTR;
|
||||
@@ -2246,11 +2656,17 @@
|
||||
*/
|
||||
b44_chip_reset(bp);
|
||||
|
||||
- printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
|
||||
+ printk(KERN_INFO "%s: Broadcom %s 10/100BaseT Ethernet ", dev->name,
|
||||
+ (pdev->device == PCI_DEVICE_ID_BCM4713) ? "47xx" : "4400");
|
||||
for (i = 0; i < 6; i++)
|
||||
printk("%2.2x%c", dev->dev_addr[i],
|
||||
i == 5 ? '\n' : ':');
|
||||
|
||||
+ /* Initialize phy */
|
||||
+ spin_lock_irq(&bp->lock);
|
||||
+ b44_chip_reset(bp);
|
||||
+ spin_unlock_irq(&bp->lock);
|
||||
+
|
||||
return 0;
|
||||
|
||||
err_out_iounmap:
|
||||
diff -urN linux-2.6.19.ref/drivers/net/b44.h linux-2.6.19/drivers/net/b44.h
|
||||
--- linux-2.6.19.ref/drivers/net/b44.h 2006-11-29 22:57:37.000000000 +0100
|
||||
+++ linux-2.6.19/drivers/net/b44.h 2006-12-04 21:34:14.000000000 +0100
|
||||
@@ -297,6 +297,10 @@
|
||||
#define SSB_PCI_MASK1 0xfc000000
|
||||
#define SSB_PCI_MASK2 0xc0000000
|
||||
|
||||
+#define br32(bp, REG) readl((void *)bp->regs + (REG))
|
||||
+#define bw32(bp, REG,VAL) writel((VAL), (void *)bp->regs + (REG))
|
||||
+#define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0)
|
||||
+
|
||||
/* 4400 PHY registers */
|
||||
#define B44_MII_AUXCTRL 24 /* Auxiliary Control */
|
||||
#define MII_AUXCTRL_DUPLEX 0x0001 /* Full Duplex */
|
||||
@@ -350,6 +354,8 @@
|
||||
};
|
||||
|
||||
#define B44_MCAST_TABLE_SIZE 32
|
||||
+#define B44_PHY_ADDR_NO_PHY 30
|
||||
+#define B44_MDC_RATIO 5000000
|
||||
|
||||
#define B44_STAT_REG_DECLARE \
|
||||
_B44(tx_good_octets) \
|
||||
@@ -428,6 +434,7 @@
|
||||
#define B44_FLAG_B0_ANDLATER 0x00000001
|
||||
#define B44_FLAG_BUGGY_TXPTR 0x00000002
|
||||
#define B44_FLAG_REORDER_BUG 0x00000004
|
||||
+#define B44_FLAG_INIT_COMPLETE 0x00000008
|
||||
#define B44_FLAG_PAUSE_AUTO 0x00008000
|
||||
#define B44_FLAG_FULL_DUPLEX 0x00010000
|
||||
#define B44_FLAG_100_BASE_T 0x00020000
|
||||
@ -1,94 +0,0 @@
|
||||
diff -urN linux-2.6.19.ref/arch/mips/Kconfig linux-2.6.19/arch/mips/Kconfig
|
||||
--- linux-2.6.19.ref/arch/mips/Kconfig 2006-12-04 21:33:48.000000000 +0100
|
||||
+++ linux-2.6.19/arch/mips/Kconfig 2006-12-04 21:34:04.000000000 +0100
|
||||
@@ -283,7 +283,6 @@
|
||||
select I8259
|
||||
select MIPS_BOARDS_GEN
|
||||
select MIPS_BONITO64
|
||||
- select MIPS_CPU_SCACHE
|
||||
select MIPS_GT64120
|
||||
select MIPS_MSC
|
||||
select SWAP_IO_SPACE
|
||||
@@ -1434,13 +1433,6 @@
|
||||
bool
|
||||
select BOARD_SCACHE
|
||||
|
||||
-#
|
||||
-# Support for a MIPS32 / MIPS64 style S-caches
|
||||
-#
|
||||
-config MIPS_CPU_SCACHE
|
||||
- bool
|
||||
- select BOARD_SCACHE
|
||||
-
|
||||
config R5000_CPU_SCACHE
|
||||
bool
|
||||
select BOARD_SCACHE
|
||||
diff -urN linux-2.6.19.ref/arch/mips/kernel/cpu-probe.c linux-2.6.19/arch/mips/kernel/cpu-probe.c
|
||||
--- linux-2.6.19.ref/arch/mips/kernel/cpu-probe.c 2006-12-04 21:33:48.000000000 +0100
|
||||
+++ linux-2.6.19/arch/mips/kernel/cpu-probe.c 2006-12-04 21:34:04.000000000 +0100
|
||||
@@ -631,6 +631,8 @@
|
||||
break;
|
||||
case PRID_IMP_25KF:
|
||||
c->cputype = CPU_25KF;
|
||||
+ /* Probe for L2 cache */
|
||||
+ c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
|
||||
break;
|
||||
case PRID_IMP_34K:
|
||||
c->cputype = CPU_34K;
|
||||
diff -urN linux-2.6.19.ref/arch/mips/mm/c-r4k.c linux-2.6.19/arch/mips/mm/c-r4k.c
|
||||
--- linux-2.6.19.ref/arch/mips/mm/c-r4k.c 2006-11-29 22:57:37.000000000 +0100
|
||||
+++ linux-2.6.19/arch/mips/mm/c-r4k.c 2006-12-04 21:34:04.000000000 +0100
|
||||
@@ -1038,7 +1038,6 @@
|
||||
|
||||
extern int r5k_sc_init(void);
|
||||
extern int rm7k_sc_init(void);
|
||||
-extern int mips_sc_init(void);
|
||||
|
||||
static void __init setup_scache(void)
|
||||
{
|
||||
@@ -1086,29 +1085,17 @@
|
||||
return;
|
||||
|
||||
default:
|
||||
- if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
|
||||
- c->isa_level == MIPS_CPU_ISA_M32R2 ||
|
||||
- c->isa_level == MIPS_CPU_ISA_M64R1 ||
|
||||
- c->isa_level == MIPS_CPU_ISA_M64R2) {
|
||||
-#ifdef CONFIG_MIPS_CPU_SCACHE
|
||||
- if (mips_sc_init ()) {
|
||||
- scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
|
||||
- printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
|
||||
- scache_size >> 10,
|
||||
- way_string[c->scache.ways], c->scache.linesz);
|
||||
- }
|
||||
-#else
|
||||
- if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
|
||||
- panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
|
||||
-#endif
|
||||
- return;
|
||||
- }
|
||||
sc_present = 0;
|
||||
}
|
||||
|
||||
if (!sc_present)
|
||||
return;
|
||||
|
||||
+ if ((c->isa_level == MIPS_CPU_ISA_M32R1 ||
|
||||
+ c->isa_level == MIPS_CPU_ISA_M64R1) &&
|
||||
+ !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
|
||||
+ panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
|
||||
+
|
||||
/* compute a couple of other cache variables */
|
||||
c->scache.waysize = scache_size / c->scache.ways;
|
||||
|
||||
diff -urN linux-2.6.19.ref/arch/mips/mm/Makefile linux-2.6.19/arch/mips/mm/Makefile
|
||||
--- linux-2.6.19.ref/arch/mips/mm/Makefile 2006-11-29 22:57:37.000000000 +0100
|
||||
+++ linux-2.6.19/arch/mips/mm/Makefile 2006-12-04 21:34:04.000000000 +0100
|
||||
@@ -30,7 +30,6 @@
|
||||
obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o
|
||||
obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o
|
||||
obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o
|
||||
-obj-$(CONFIG_MIPS_CPU_SCACHE) += sc-mips.o
|
||||
|
||||
#
|
||||
# Choose one DMA coherency model
|
||||
@ -1,44 +0,0 @@
|
||||
diff -urN linux-2.6.19.ref/drivers/net/b44.c linux-2.6.19/drivers/net/b44.c
|
||||
--- linux-2.6.19.ref/drivers/net/b44.c 2006-12-04 21:34:14.000000000 +0100
|
||||
+++ linux-2.6.19/drivers/net/b44.c 2006-12-04 21:34:19.000000000 +0100
|
||||
@@ -1445,6 +1445,7 @@
|
||||
{
|
||||
struct b44 *bp = netdev_priv(dev);
|
||||
struct sockaddr *addr = p;
|
||||
+ u32 val;
|
||||
|
||||
if (netif_running(dev))
|
||||
return -EBUSY;
|
||||
@@ -1455,7 +1456,11 @@
|
||||
memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
|
||||
|
||||
spin_lock_irq(&bp->lock);
|
||||
- __b44_set_mac_addr(bp);
|
||||
+
|
||||
+ val = br32(bp, B44_RXCONFIG);
|
||||
+ if (!(val & RXCONFIG_CAM_ABSENT))
|
||||
+ __b44_set_mac_addr(bp);
|
||||
+
|
||||
spin_unlock_irq(&bp->lock);
|
||||
|
||||
return 0;
|
||||
@@ -1797,7 +1802,7 @@
|
||||
|
||||
val = br32(bp, B44_RXCONFIG);
|
||||
val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
|
||||
- if (dev->flags & IFF_PROMISC) {
|
||||
+ if ((dev->flags & IFF_PROMISC) || (val & RXCONFIG_CAM_ABSENT)) {
|
||||
val |= RXCONFIG_PROMISC;
|
||||
bw32(bp, B44_RXCONFIG, val);
|
||||
} else {
|
||||
diff -urN linux-2.6.19.ref/drivers/net/b44.h linux-2.6.19/drivers/net/b44.h
|
||||
--- linux-2.6.19.ref/drivers/net/b44.h 2006-12-04 21:34:14.000000000 +0100
|
||||
+++ linux-2.6.19/drivers/net/b44.h 2006-12-04 21:34:19.000000000 +0100
|
||||
@@ -129,6 +129,7 @@
|
||||
#define RXCONFIG_FLOW 0x00000020 /* Flow Control Enable */
|
||||
#define RXCONFIG_FLOW_ACCEPT 0x00000040 /* Accept Unicast Flow Control Frame */
|
||||
#define RXCONFIG_RFILT 0x00000080 /* Reject Filter */
|
||||
+#define RXCONFIG_CAM_ABSENT 0x00000100 /* CAM Absent */
|
||||
#define B44_RXMAXLEN 0x0404UL /* EMAC RX Max Packet Length */
|
||||
#define B44_TXMAXLEN 0x0408UL /* EMAC TX Max Packet Length */
|
||||
#define B44_MDIO_CTRL 0x0410UL /* EMAC MDIO Control */
|
||||
@ -1 +0,0 @@
|
||||
../brcm-2.4/src
|
||||
Loading…
Reference in New Issue