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@ -30,6 +30,7 @@
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#define AR71XX_SYS_TYPE_LEN 64
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#define AR71XX_BASE_FREQ 40000000
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#define AR91XX_BASE_FREQ 5000000
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#define AR71XX_MEM_SIZE_MIN 0x0200000
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#define AR71XX_MEM_SIZE_MAX 0x8000000
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@ -128,6 +129,9 @@ static void __init ar71xx_detect_sys_type(void)
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case REV_ID_CHIP_AR7161:
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chip = "7161";
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break;
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case REV_ID_CHIP_AR9130:
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chip = "9130";
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break;
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default:
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chip = "71xx";
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}
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@ -136,24 +140,49 @@ static void __init ar71xx_detect_sys_type(void)
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chip, rev, id);
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}
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static void __init ar91xx_detect_sys_frequency(void)
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{
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u32 pll;
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u32 freq;
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u32 div;
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pll = ar71xx_pll_rr(PLL_REG_CPU_PLL_CFG);
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div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
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freq = div * AR91XX_BASE_FREQ;
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ar71xx_cpu_freq = freq;
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div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
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ar71xx_ddr_freq = freq / div;
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div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
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ar71xx_ahb_freq = ar71xx_cpu_freq / div;
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}
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static void __init ar71xx_detect_sys_frequency(void)
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{
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u32 pll;
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u32 freq;
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u32 div;
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if ((ar71xx_reset_rr(RESET_REG_REV_ID) & REV_ID_MASK) >=
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REV_ID_CHIP_AR9130) {
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return ar91xx_detect_sys_frequency();
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}
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pll = ar71xx_pll_rr(PLL_REG_CPU_PLL_CFG);
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div = ((pll >> PLL_DIV_SHIFT) & PLL_DIV_MASK) + 1;
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div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
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freq = div * AR71XX_BASE_FREQ;
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div = ((pll >> CPU_DIV_SHIFT) & CPU_DIV_MASK) + 1;
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div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
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ar71xx_cpu_freq = freq / div;
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div = ((pll >> DDR_DIV_SHIFT) & DDR_DIV_MASK) + 1;
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div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
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ar71xx_ddr_freq = freq / div;
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div = (((pll >> AHB_DIV_SHIFT) & AHB_DIV_MASK) + 1) * 2;
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div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
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ar71xx_ahb_freq = ar71xx_cpu_freq / div;
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}
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