From d8655868ca04d12ad5ed36e26fc63d61b076e33d Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Tue, 27 Feb 2018 15:09:43 +0100 Subject: [PATCH] ramips: fix spurious IRQ7 events when using perf on 4.14 Upstream handling of MIPS CPU IRQs is rather hackish and the interrupts are being enabled unconditionally in various places because of legacy code. Performance counter events are routed both through the GIC and through legacy CPU IRQ7 events, causing spurious interrupts. Fix this by disabling IRQ7 when trying to access the performance counter IRQ. Signed-off-by: Felix Fietkau --- .../patches-4.14/110-mt7621-perfctr-fix.patch | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 target/linux/ramips/patches-4.14/110-mt7621-perfctr-fix.patch diff --git a/target/linux/ramips/patches-4.14/110-mt7621-perfctr-fix.patch b/target/linux/ramips/patches-4.14/110-mt7621-perfctr-fix.patch new file mode 100644 index 0000000000..4c40e65ab9 --- /dev/null +++ b/target/linux/ramips/patches-4.14/110-mt7621-perfctr-fix.patch @@ -0,0 +1,15 @@ +--- a/arch/mips/ralink/irq-gic.c ++++ b/arch/mips/ralink/irq-gic.c +@@ -15,6 +15,12 @@ + + int get_c0_perfcount_int(void) + { ++ /* ++ * Performance counter events are routed through GIC. ++ * Prevent them from firing on CPU IRQ7 as well ++ */ ++ clear_c0_status(IE_SW0 << 7); ++ + return gic_get_c0_perfcount_int(); + } + EXPORT_SYMBOL_GPL(get_c0_perfcount_int);