ar71xx: add support for the Senao CAP4200AG board
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 33956v19.07.3_mercusys_ac12_duma
Gabor Juhos
12 years ago
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3b7cb4eb4a
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d54c9653e9
@ -0,0 +1,131 @@
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/*
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* Senao CAP4200AG board support
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*
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* Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/pci.h>
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#include <linux/phy.h>
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#include <linux/platform_device.h>
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#include <linux/ath9k_platform.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include "common.h"
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#include "dev-ap9x-pci.h"
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#include "dev-eth.h"
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#include "dev-gpio-buttons.h"
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#include "dev-leds-gpio.h"
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#include "dev-m25p80.h"
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#include "dev-spi.h"
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#include "dev-usb.h"
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#include "dev-wmac.h"
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#include "machtypes.h"
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#define CAP4200AG_GPIO_LED_PWR_GREEN 12
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#define CAP4200AG_GPIO_LED_PWR_AMBER 13
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#define CAP4200AG_GPIO_LED_LAN_GREEN 14
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#define CAP4200AG_GPIO_LED_LAN_AMBER 15
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#define CAP4200AG_GPIO_LED_WLAN_GREEN 18
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#define CAP4200AG_GPIO_LED_WLAN_AMBER 19
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#define CAP4200AG_GPIO_BTN_RESET 17
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#define CAP4200AG_KEYS_POLL_INTERVAL 20 /* msecs */
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#define CAP4200AG_KEYS_DEBOUNCE_INTERVAL (3 * CAP4200AG_KEYS_POLL_INTERVAL)
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#define CAP4200AG_MAC_OFFSET 0
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#define CAP4200AG_WMAC_CALDATA_OFFSET 0x1000
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#define CAP4200AG_PCIE_CALDATA_OFFSET 0x5000
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static struct gpio_led cap4200ag_leds_gpio[] __initdata = {
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{
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.name = "senao:green:pwr",
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.gpio = CAP4200AG_GPIO_LED_PWR_GREEN,
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.active_low = 1,
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},
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{
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.name = "senao:amber:pwr",
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.gpio = CAP4200AG_GPIO_LED_PWR_AMBER,
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.active_low = 1,
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},
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{
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.name = "senao:green:lan",
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.gpio = CAP4200AG_GPIO_LED_LAN_GREEN,
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.active_low = 1,
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},
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{
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.name = "senao:amber:lan",
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.gpio = CAP4200AG_GPIO_LED_LAN_AMBER,
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.active_low = 1,
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},
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{
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.name = "senao:green:wlan",
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.gpio = CAP4200AG_GPIO_LED_WLAN_GREEN,
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.active_low = 1,
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},
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{
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.name = "senao:amber:wlan",
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.gpio = CAP4200AG_GPIO_LED_WLAN_AMBER,
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.active_low = 1,
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},
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};
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static struct gpio_keys_button cap4200ag_gpio_keys[] __initdata = {
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{
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.desc = "Reset button",
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.type = EV_KEY,
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.code = KEY_RESTART,
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.debounce_interval = CAP4200AG_KEYS_DEBOUNCE_INTERVAL,
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.gpio = CAP4200AG_GPIO_BTN_RESET,
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.active_low = 1,
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},
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};
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static void __init cap4200ag_setup(void)
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{
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u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
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u8 mac[6];
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ath79_gpio_output_select(CAP4200AG_GPIO_LED_LAN_GREEN,
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AR934X_GPIO_OUT_GPIO);
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ath79_gpio_output_select(CAP4200AG_GPIO_LED_LAN_AMBER,
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AR934X_GPIO_OUT_GPIO);
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ath79_register_m25p80(NULL);
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ath79_register_leds_gpio(-1, ARRAY_SIZE(cap4200ag_leds_gpio),
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cap4200ag_leds_gpio);
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ath79_register_gpio_keys_polled(-1, CAP4200AG_KEYS_POLL_INTERVAL,
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ARRAY_SIZE(cap4200ag_gpio_keys),
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cap4200ag_gpio_keys);
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ath79_init_mac(mac, art + CAP4200AG_MAC_OFFSET, -1);
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ath79_wmac_disable_2ghz();
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ath79_register_wmac(art + CAP4200AG_WMAC_CALDATA_OFFSET, mac);
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ath79_init_mac(mac, art + CAP4200AG_MAC_OFFSET, -2);
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ap91_pci_init(art + CAP4200AG_PCIE_CALDATA_OFFSET, mac);
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ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
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AR934X_ETH_CFG_SW_ONLY_MODE);
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ath79_register_mdio(0, 0x0);
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ath79_init_mac(ath79_eth0_data.mac_addr,
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art + CAP4200AG_MAC_OFFSET, -2);
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/* GMAC0 is connected to an external PHY */
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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ath79_eth0_data.phy_mask = BIT(0);
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ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
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ath79_eth0_pll_data.pll_1000 = 0x06000000;
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ath79_register_eth(0);
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}
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MIPS_MACHINE(ATH79_MACH_CAP4200AG, "CAP4200AG", "Senao CAP4200AG",
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cap4200ag_setup);
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@ -0,0 +1,39 @@
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--- a/arch/mips/ath79/Kconfig
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+++ b/arch/mips/ath79/Kconfig
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@@ -403,6 +403,16 @@ config ATH79_MACH_RW2458N
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select ATH79_DEV_M25P80
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select ATH79_DEV_USB
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+config ATH79_MACH_CAP4200AG
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+ bool "Senao CAP4200AG support"
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+ select SOC_AR934X
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+ select ATH79_DEV_AP9X_PCI if PCI
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+ select ATH79_DEV_WMAC
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+
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config ATH79_MACH_EAP7660D
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bool "Senao EAP7660D support"
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select SOC_AR71XX
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--- a/arch/mips/ath79/machtypes.h
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+++ b/arch/mips/ath79/machtypes.h
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@@ -29,6 +29,7 @@ enum ath79_mach_type {
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ATH79_MACH_AP83, /* Atheros AP83 */
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ATH79_MACH_AP96, /* Atheros AP96 */
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ATH79_MACH_AW_NR580, /* AzureWave AW-NR580 */
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+ ATH79_MACH_CAP4200AG, /* Senao CAP4200AG */
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ATH79_MACH_DB120, /* Atheros DB120 reference board */
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ATH79_MACH_PB44, /* Atheros PB44 reference board */
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ATH79_MACH_DIR_600_A1, /* D-Link DIR-600 rev. A1 */
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--- a/arch/mips/ath79/Makefile
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+++ b/arch/mips/ath79/Makefile
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@@ -49,6 +49,7 @@ obj-$(CONFIG_ATH79_MACH_AP81) += mach-a
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obj-$(CONFIG_ATH79_MACH_AP83) += mach-ap83.o
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obj-$(CONFIG_ATH79_MACH_AP96) += mach-ap96.o
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obj-$(CONFIG_ATH79_MACH_AW_NR580) += mach-aw-nr580.o
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+obj-$(CONFIG_ATH79_MACH_CAP4200AG) += mach-cap4200ag.o
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obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o
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obj-$(CONFIG_ATH79_MACH_DIR_600_A1) += mach-dir-600-a1.o
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obj-$(CONFIG_ATH79_MACH_DIR_615_C1) += mach-dir-615-c1.o
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