add the new ath9k driver (loads successfully on an AR9160 card, but still seems to have some rf issues)
SVN-Revision: 11884v19.07.3_mercusys_ac12_duma
Felix Fietkau
16 years ago
parent
12d206d9eb
commit
d53ff609b5
@ -0,0 +1,59 @@
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#
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# Copyright (C) 2008 OpenWrt.org
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#
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# This is free software, licensed under the GNU General Public License v2.
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# See /LICENSE for more information.
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include $(TOPDIR)/rules.mk
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include $(INCLUDE_DIR)/kernel.mk
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PKG_NAME:=ath9k
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PKG_VERSION:=20080720
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PKG_RELEASE:=1
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include $(INCLUDE_DIR)/package.mk
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define KernelPackage/ath9k
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SUBMENU:=Wireless Drivers
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TITLE:=Broadcom 43xx wireless support
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DEPENDS:=+kmod-mac80211 @!TARGET_brcm47xx
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FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ath9k/ath9k.$(LINUX_KMOD_SUFFIX)
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AUTOLOAD:=$(call AutoLoad,30,ath9k)
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endef
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define KernelPackage/ath9k/description
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Kernel module for Atheros AR9xxx and AR5416/AR5418 based cards
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endef
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EXTRA_KCONFIG:= \
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CONFIG_ATH9K=m
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EXTRA_CFLAGS:= \
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$(patsubst CONFIG_%, -DCONFIG_%=1, $(patsubst %=m,%,$(filter %=m,$(EXTRA_KCONFIG)))) \
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$(patsubst CONFIG_%, -DCONFIG_%=1, $(patsubst %=y,%,$(filter %=y,$(EXTRA_KCONFIG)))) \
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MAKE_OPTS:= \
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ARCH="$(LINUX_KARCH)" \
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CROSS_COMPILE="$(TARGET_CROSS)" \
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SUBDIRS="$(PKG_BUILD_DIR)/drivers/net/wireless/ath9k" \
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EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \
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LINUXINCLUDE="-I$(STAGING_DIR)/usr/include/mac80211 -I$(LINUX_DIR)/include -include linux/autoconf.h" \
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$(EXTRA_KCONFIG)
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define Build/Prepare
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mkdir -p $(PKG_BUILD_DIR)
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$(CP) ./src/* $(PKG_BUILD_DIR)/
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$(Build/Patch)
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$(if $(QUILT),touch $(PKG_BUILD_DIR)/.quilt_used)
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endef
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define Build/Configure
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endef
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define Build/Compile
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$(MAKE) -C "$(LINUX_DIR)" \
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$(MAKE_OPTS) \
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modules
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endef
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$(eval $(call KernelPackage,ath9k))
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@ -0,0 +1,15 @@
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Replace udelay(3000) with mdelay(3), because udelay(3000) fails on ARM
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
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--- a/drivers/net/wireless/ath9k/recv.c
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+++ b/drivers/net/wireless/ath9k/recv.c
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@@ -737,7 +737,7 @@
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ath9k_hw_stoppcurecv(ah); /* disable PCU */
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ath9k_hw_setrxfilter(ah, 0); /* clear recv filter */
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stopped = ath9k_hw_stopdmarecv(ah); /* disable DMA engine */
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- udelay(3000); /* 3ms is long enough for 1 frame */
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+ mdelay(3); /* 3ms is long enough for 1 frame */
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tsf = ath9k_hw_gettsf64(ah);
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sc->sc_rxlink = NULL; /* just in case */
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return stopped;
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@ -0,0 +1,15 @@
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Add missing include statements
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
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--- a/drivers/net/wireless/ath9k/regd.c
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+++ b/drivers/net/wireless/ath9k/regd.c
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@@ -14,6 +14,8 @@
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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+#include <linux/kernel.h>
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+#include <linux/slab.h>
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#include "ath9k.h"
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#include "regd.h"
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#include "regd_common.h"
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@ -0,0 +1,23 @@
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Add missing device ID for AR9160
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
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--- a/drivers/net/wireless/ath9k/hw.c
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+++ b/drivers/net/wireless/ath9k/hw.c
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@@ -8329,6 +8329,8 @@
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case AR5416_DEVID_PCI:
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case AR5416_DEVID_PCIE:
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return "Atheros 5416";
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+ case AR9160_DEVID_PCI:
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+ return "Atheros 9160";
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case AR9280_DEVID_PCI:
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case AR9280_DEVID_PCIE:
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return "Atheros 9280";
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@@ -8350,6 +8352,7 @@
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switch (devid) {
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case AR5416_DEVID_PCI:
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case AR5416_DEVID_PCIE:
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+ case AR9160_DEVID_PCI:
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case AR9280_DEVID_PCI:
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case AR9280_DEVID_PCIE:
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ah = ath9k_hw_do_attach(devid, sc, mem, error);
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@ -0,0 +1,16 @@
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Fix a return code check for ath9k_hw_nvram_read, this function returns
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AH_TRUE when the call succeeded
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
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--- a/drivers/net/wireless/ath9k/hw.c
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+++ b/drivers/net/wireless/ath9k/hw.c
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@@ -803,7 +803,7 @@
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u_int16_t magic, magic2;
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int addr;
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- if (ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
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+ if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
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&magic)) {
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HDPRINTF(ah, HAL_DBG_EEPROM,
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"%s: Reading Magic # failed\n", __func__);
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@ -0,0 +1,8 @@
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config ATH9K
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tristate "Atheros 802.11n wireless cards support"
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depends on PCI && MAC80211 && WLAN_80211
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---help---
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This module adds support for wireless adapters based on
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Atheros IEEE 802.11n AR5008 and AR9001 family of chipsets.
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If you choose to build a module, it'll be called ath9k.
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@ -0,0 +1,11 @@
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ath9k-y += hw.o \
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phy.o \
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regd.o \
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beacon.o \
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main.o \
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recv.o \
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xmit.o \
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rc.o \
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core.o
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obj-$(CONFIG_ATH9K) += ath9k.o
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,969 @@
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/*
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* Copyright (c) 2008 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef HW_H
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#define HW_H
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#include <linux/if_ether.h>
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#include <linux/delay.h>
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struct ar5416_desc {
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u_int32_t ds_link;
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u_int32_t ds_data;
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u_int32_t ds_ctl0;
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u_int32_t ds_ctl1;
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union {
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struct {
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u_int32_t ctl2;
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u_int32_t ctl3;
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u_int32_t ctl4;
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u_int32_t ctl5;
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u_int32_t ctl6;
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u_int32_t ctl7;
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u_int32_t ctl8;
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u_int32_t ctl9;
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u_int32_t ctl10;
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u_int32_t ctl11;
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u_int32_t status0;
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u_int32_t status1;
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u_int32_t status2;
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u_int32_t status3;
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u_int32_t status4;
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u_int32_t status5;
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u_int32_t status6;
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u_int32_t status7;
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u_int32_t status8;
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u_int32_t status9;
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} tx;
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struct {
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u_int32_t status0;
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u_int32_t status1;
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u_int32_t status2;
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u_int32_t status3;
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u_int32_t status4;
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u_int32_t status5;
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u_int32_t status6;
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u_int32_t status7;
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u_int32_t status8;
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} rx;
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} u;
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} __packed;
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#define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds))
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#define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds))
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#define ds_ctl2 u.tx.ctl2
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#define ds_ctl3 u.tx.ctl3
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#define ds_ctl4 u.tx.ctl4
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#define ds_ctl5 u.tx.ctl5
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#define ds_ctl6 u.tx.ctl6
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#define ds_ctl7 u.tx.ctl7
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#define ds_ctl8 u.tx.ctl8
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#define ds_ctl9 u.tx.ctl9
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#define ds_ctl10 u.tx.ctl10
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#define ds_ctl11 u.tx.ctl11
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#define ds_txstatus0 u.tx.status0
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#define ds_txstatus1 u.tx.status1
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#define ds_txstatus2 u.tx.status2
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#define ds_txstatus3 u.tx.status3
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#define ds_txstatus4 u.tx.status4
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#define ds_txstatus5 u.tx.status5
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#define ds_txstatus6 u.tx.status6
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#define ds_txstatus7 u.tx.status7
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#define ds_txstatus8 u.tx.status8
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#define ds_txstatus9 u.tx.status9
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#define ds_rxstatus0 u.rx.status0
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#define ds_rxstatus1 u.rx.status1
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#define ds_rxstatus2 u.rx.status2
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#define ds_rxstatus3 u.rx.status3
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#define ds_rxstatus4 u.rx.status4
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#define ds_rxstatus5 u.rx.status5
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#define ds_rxstatus6 u.rx.status6
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#define ds_rxstatus7 u.rx.status7
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#define ds_rxstatus8 u.rx.status8
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#define AR_FrameLen 0x00000fff
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#define AR_VirtMoreFrag 0x00001000
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#define AR_TxCtlRsvd00 0x0000e000
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#define AR_XmitPower 0x003f0000
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#define AR_XmitPower_S 16
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#define AR_RTSEnable 0x00400000
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#define AR_VEOL 0x00800000
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#define AR_ClrDestMask 0x01000000
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#define AR_TxCtlRsvd01 0x1e000000
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#define AR_TxIntrReq 0x20000000
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#define AR_DestIdxValid 0x40000000
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#define AR_CTSEnable 0x80000000
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#define AR_BufLen 0x00000fff
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#define AR_TxMore 0x00001000
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#define AR_DestIdx 0x000fe000
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#define AR_DestIdx_S 13
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#define AR_FrameType 0x00f00000
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#define AR_FrameType_S 20
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#define AR_NoAck 0x01000000
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#define AR_InsertTS 0x02000000
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#define AR_CorruptFCS 0x04000000
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#define AR_ExtOnly 0x08000000
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#define AR_ExtAndCtl 0x10000000
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#define AR_MoreAggr 0x20000000
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#define AR_IsAggr 0x40000000
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#define AR_BurstDur 0x00007fff
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#define AR_BurstDur_S 0
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#define AR_DurUpdateEna 0x00008000
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#define AR_XmitDataTries0 0x000f0000
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#define AR_XmitDataTries0_S 16
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#define AR_XmitDataTries1 0x00f00000
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#define AR_XmitDataTries1_S 20
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#define AR_XmitDataTries2 0x0f000000
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#define AR_XmitDataTries2_S 24
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#define AR_XmitDataTries3 0xf0000000
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#define AR_XmitDataTries3_S 28
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#define AR_XmitRate0 0x000000ff
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#define AR_XmitRate0_S 0
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#define AR_XmitRate1 0x0000ff00
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#define AR_XmitRate1_S 8
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#define AR_XmitRate2 0x00ff0000
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#define AR_XmitRate2_S 16
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#define AR_XmitRate3 0xff000000
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#define AR_XmitRate3_S 24
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#define AR_PacketDur0 0x00007fff
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#define AR_PacketDur0_S 0
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#define AR_RTSCTSQual0 0x00008000
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#define AR_PacketDur1 0x7fff0000
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#define AR_PacketDur1_S 16
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#define AR_RTSCTSQual1 0x80000000
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#define AR_PacketDur2 0x00007fff
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#define AR_PacketDur2_S 0
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#define AR_RTSCTSQual2 0x00008000
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#define AR_PacketDur3 0x7fff0000
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#define AR_PacketDur3_S 16
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#define AR_RTSCTSQual3 0x80000000
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#define AR_AggrLen 0x0000ffff
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#define AR_AggrLen_S 0
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#define AR_TxCtlRsvd60 0x00030000
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#define AR_PadDelim 0x03fc0000
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#define AR_PadDelim_S 18
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#define AR_EncrType 0x0c000000
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#define AR_EncrType_S 26
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#define AR_TxCtlRsvd61 0xf0000000
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#define AR_2040_0 0x00000001
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#define AR_GI0 0x00000002
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#define AR_ChainSel0 0x0000001c
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#define AR_ChainSel0_S 2
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#define AR_2040_1 0x00000020
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#define AR_GI1 0x00000040
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#define AR_ChainSel1 0x00000380
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#define AR_ChainSel1_S 7
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#define AR_2040_2 0x00000400
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#define AR_GI2 0x00000800
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#define AR_ChainSel2 0x00007000
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#define AR_ChainSel2_S 12
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#define AR_2040_3 0x00008000
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#define AR_GI3 0x00010000
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#define AR_ChainSel3 0x000e0000
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#define AR_ChainSel3_S 17
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#define AR_RTSCTSRate 0x0ff00000
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#define AR_RTSCTSRate_S 20
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#define AR_TxCtlRsvd70 0xf0000000
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#define AR_TxRSSIAnt00 0x000000ff
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#define AR_TxRSSIAnt00_S 0
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#define AR_TxRSSIAnt01 0x0000ff00
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#define AR_TxRSSIAnt01_S 8
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#define AR_TxRSSIAnt02 0x00ff0000
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#define AR_TxRSSIAnt02_S 16
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#define AR_TxStatusRsvd00 0x3f000000
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#define AR_TxBaStatus 0x40000000
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#define AR_TxStatusRsvd01 0x80000000
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#define AR_FrmXmitOK 0x00000001
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#define AR_ExcessiveRetries 0x00000002
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#define AR_FIFOUnderrun 0x00000004
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#define AR_Filtered 0x00000008
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#define AR_RTSFailCnt 0x000000f0
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#define AR_RTSFailCnt_S 4
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#define AR_DataFailCnt 0x00000f00
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#define AR_DataFailCnt_S 8
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#define AR_VirtRetryCnt 0x0000f000
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#define AR_VirtRetryCnt_S 12
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#define AR_TxDelimUnderrun 0x00010000
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#define AR_TxDataUnderrun 0x00020000
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#define AR_DescCfgErr 0x00040000
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#define AR_TxTimerExpired 0x00080000
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#define AR_TxStatusRsvd10 0xfff00000
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#define AR_SendTimestamp ds_txstatus2
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#define AR_BaBitmapLow ds_txstatus3
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#define AR_BaBitmapHigh ds_txstatus4
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#define AR_TxRSSIAnt10 0x000000ff
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#define AR_TxRSSIAnt10_S 0
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#define AR_TxRSSIAnt11 0x0000ff00
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#define AR_TxRSSIAnt11_S 8
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#define AR_TxRSSIAnt12 0x00ff0000
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#define AR_TxRSSIAnt12_S 16
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#define AR_TxRSSICombined 0xff000000
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#define AR_TxRSSICombined_S 24
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#define AR_TxEVM0 ds_txstatus5
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#define AR_TxEVM1 ds_txstatus6
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#define AR_TxEVM2 ds_txstatus7
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#define AR_TxDone 0x00000001
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#define AR_SeqNum 0x00001ffe
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#define AR_SeqNum_S 1
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#define AR_TxStatusRsvd80 0x0001e000
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#define AR_TxOpExceeded 0x00020000
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#define AR_TxStatusRsvd81 0x001c0000
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#define AR_FinalTxIdx 0x00600000
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#define AR_FinalTxIdx_S 21
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#define AR_TxStatusRsvd82 0x01800000
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#define AR_PowerMgmt 0x02000000
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#define AR_TxStatusRsvd83 0xfc000000
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#define AR_RxCTLRsvd00 0xffffffff
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#define AR_BufLen 0x00000fff
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#define AR_RxCtlRsvd00 0x00001000
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#define AR_RxIntrReq 0x00002000
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#define AR_RxCtlRsvd01 0xffffc000
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#define AR_RxRSSIAnt00 0x000000ff
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#define AR_RxRSSIAnt00_S 0
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#define AR_RxRSSIAnt01 0x0000ff00
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#define AR_RxRSSIAnt01_S 8
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#define AR_RxRSSIAnt02 0x00ff0000
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#define AR_RxRSSIAnt02_S 16
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#define AR_RxRate 0xff000000
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#define AR_RxRate_S 24
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#define AR_RxStatusRsvd00 0xff000000
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#define AR_DataLen 0x00000fff
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#define AR_RxMore 0x00001000
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#define AR_NumDelim 0x003fc000
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#define AR_NumDelim_S 14
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#define AR_RxStatusRsvd10 0xff800000
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|
||||
#define AR_RcvTimestamp ds_rxstatus2
|
||||
|
||||
#define AR_GI 0x00000001
|
||||
#define AR_2040 0x00000002
|
||||
#define AR_Parallel40 0x00000004
|
||||
#define AR_Parallel40_S 2
|
||||
#define AR_RxStatusRsvd30 0x000000f8
|
||||
#define AR_RxAntenna 0xffffff00
|
||||
#define AR_RxAntenna_S 8
|
||||
|
||||
#define AR_RxRSSIAnt10 0x000000ff
|
||||
#define AR_RxRSSIAnt10_S 0
|
||||
#define AR_RxRSSIAnt11 0x0000ff00
|
||||
#define AR_RxRSSIAnt11_S 8
|
||||
#define AR_RxRSSIAnt12 0x00ff0000
|
||||
#define AR_RxRSSIAnt12_S 16
|
||||
#define AR_RxRSSICombined 0xff000000
|
||||
#define AR_RxRSSICombined_S 24
|
||||
|
||||
#define AR_RxEVM0 ds_rxstatus4
|
||||
#define AR_RxEVM1 ds_rxstatus5
|
||||
#define AR_RxEVM2 ds_rxstatus6
|
||||
|
||||
#define AR_RxDone 0x00000001
|
||||
#define AR_RxFrameOK 0x00000002
|
||||
#define AR_CRCErr 0x00000004
|
||||
#define AR_DecryptCRCErr 0x00000008
|
||||
#define AR_PHYErr 0x00000010
|
||||
#define AR_MichaelErr 0x00000020
|
||||
#define AR_PreDelimCRCErr 0x00000040
|
||||
#define AR_RxStatusRsvd70 0x00000080
|
||||
#define AR_RxKeyIdxValid 0x00000100
|
||||
#define AR_KeyIdx 0x0000fe00
|
||||
#define AR_KeyIdx_S 9
|
||||
#define AR_PHYErrCode 0x0000ff00
|
||||
#define AR_PHYErrCode_S 8
|
||||
#define AR_RxMoreAggr 0x00010000
|
||||
#define AR_RxAggr 0x00020000
|
||||
#define AR_PostDelimCRCErr 0x00040000
|
||||
#define AR_RxStatusRsvd71 0x3ff80000
|
||||
#define AR_DecryptBusyErr 0x40000000
|
||||
#define AR_KeyMiss 0x80000000
|
||||
|
||||
#define AR5416_MAGIC 0x19641014
|
||||
|
||||
#define RXSTATUS_RATE(ah, ads) (AR_SREV_5416_V20_OR_LATER(ah) ? \
|
||||
MS(ads->ds_rxstatus0, AR_RxRate) : \
|
||||
(ads->ds_rxstatus3 >> 2) & 0xFF)
|
||||
#define RXSTATUS_DUPLICATE(ah, ads) (AR_SREV_5416_V20_OR_LATER(ah) ? \
|
||||
MS(ads->ds_rxstatus3, AR_Parallel40) : \
|
||||
(ads->ds_rxstatus3 >> 10) & 0x1)
|
||||
|
||||
#define set11nTries(_series, _index) \
|
||||
(SM((_series)[_index].Tries, AR_XmitDataTries##_index))
|
||||
|
||||
#define set11nRate(_series, _index) \
|
||||
(SM((_series)[_index].Rate, AR_XmitRate##_index))
|
||||
|
||||
#define set11nPktDurRTSCTS(_series, _index) \
|
||||
(SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \
|
||||
((_series)[_index].RateFlags & HAL_RATESERIES_RTS_CTS ? \
|
||||
AR_RTSCTSQual##_index : 0))
|
||||
|
||||
#define set11nRateFlags(_series, _index) \
|
||||
(((_series)[_index].RateFlags & HAL_RATESERIES_2040 ? \
|
||||
AR_2040_##_index : 0) \
|
||||
|((_series)[_index].RateFlags & HAL_RATESERIES_HALFGI ? \
|
||||
AR_GI##_index : 0) \
|
||||
|SM((_series)[_index].ChSel, AR_ChainSel##_index))
|
||||
|
||||
#define AR_SREV_9100(ah) ((ah->ah_macVersion) == AR_SREV_VERSION_9100)
|
||||
|
||||
#define INIT_CONFIG_STATUS 0x00000000
|
||||
#define INIT_RSSI_THR 0x00000700
|
||||
#define INIT_BCON_CNTRL_REG 0x00000000
|
||||
|
||||
#define MIN_TX_FIFO_THRESHOLD 0x1
|
||||
#define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1)
|
||||
#define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD
|
||||
|
||||
#define NUM_CORNER_FIX_BITS_2133 7
|
||||
#define CCK_OFDM_GAIN_DELTA 15
|
||||
|
||||
struct ar5416AniState {
|
||||
struct hal_channel c;
|
||||
u_int8_t noiseImmunityLevel;
|
||||
u_int8_t spurImmunityLevel;
|
||||
u_int8_t firstepLevel;
|
||||
u_int8_t ofdmWeakSigDetectOff;
|
||||
u_int8_t cckWeakSigThreshold;
|
||||
u_int32_t listenTime;
|
||||
u_int32_t ofdmTrigHigh;
|
||||
u_int32_t ofdmTrigLow;
|
||||
int32_t cckTrigHigh;
|
||||
int32_t cckTrigLow;
|
||||
int32_t rssiThrLow;
|
||||
int32_t rssiThrHigh;
|
||||
u_int32_t noiseFloor;
|
||||
u_int32_t txFrameCount;
|
||||
u_int32_t rxFrameCount;
|
||||
u_int32_t cycleCount;
|
||||
u_int32_t ofdmPhyErrCount;
|
||||
u_int32_t cckPhyErrCount;
|
||||
u_int32_t ofdmPhyErrBase;
|
||||
u_int32_t cckPhyErrBase;
|
||||
int16_t pktRssi[2];
|
||||
int16_t ofdmErrRssi[2];
|
||||
int16_t cckErrRssi[2];
|
||||
};
|
||||
|
||||
#define HAL_PROCESS_ANI 0x00000001
|
||||
#define HAL_RADAR_EN 0x80000000
|
||||
#define HAL_AR_EN 0x40000000
|
||||
|
||||
#define DO_ANI(ah) \
|
||||
((AH5416(ah)->ah_procPhyErr & HAL_PROCESS_ANI))
|
||||
|
||||
struct ar5416Stats {
|
||||
u_int32_t ast_ani_niup;
|
||||
u_int32_t ast_ani_nidown;
|
||||
u_int32_t ast_ani_spurup;
|
||||
u_int32_t ast_ani_spurdown;
|
||||
u_int32_t ast_ani_ofdmon;
|
||||
u_int32_t ast_ani_ofdmoff;
|
||||
u_int32_t ast_ani_cckhigh;
|
||||
u_int32_t ast_ani_ccklow;
|
||||
u_int32_t ast_ani_stepup;
|
||||
u_int32_t ast_ani_stepdown;
|
||||
u_int32_t ast_ani_ofdmerrs;
|
||||
u_int32_t ast_ani_cckerrs;
|
||||
u_int32_t ast_ani_reset;
|
||||
u_int32_t ast_ani_lzero;
|
||||
u_int32_t ast_ani_lneg;
|
||||
struct hal_mib_stats ast_mibstats;
|
||||
struct hal_node_stats ast_nodestats;
|
||||
};
|
||||
|
||||
#define AR5416_OPFLAGS_11A 0x01
|
||||
#define AR5416_OPFLAGS_11G 0x02
|
||||
#define AR5416_OPFLAGS_N_5G_HT40 0x04
|
||||
#define AR5416_OPFLAGS_N_2G_HT40 0x08
|
||||
#define AR5416_OPFLAGS_N_5G_HT20 0x10
|
||||
#define AR5416_OPFLAGS_N_2G_HT20 0x20
|
||||
|
||||
#define EEP_RFSILENT_ENABLED 0x0001
|
||||
#define EEP_RFSILENT_ENABLED_S 0
|
||||
#define EEP_RFSILENT_POLARITY 0x0002
|
||||
#define EEP_RFSILENT_POLARITY_S 1
|
||||
#define EEP_RFSILENT_GPIO_SEL 0x001c
|
||||
#define EEP_RFSILENT_GPIO_SEL_S 2
|
||||
|
||||
#define AR5416_EEP_NO_BACK_VER 0x1
|
||||
#define AR5416_EEP_VER 0xE
|
||||
#define AR5416_EEP_VER_MINOR_MASK 0x0FFF
|
||||
#define AR5416_EEP_MINOR_VER_2 0x2
|
||||
#define AR5416_EEP_MINOR_VER_3 0x3
|
||||
#define AR5416_EEP_MINOR_VER_7 0x7
|
||||
#define AR5416_EEP_MINOR_VER_9 0x9
|
||||
|
||||
#define AR5416_EEP_START_LOC 256
|
||||
#define AR5416_NUM_5G_CAL_PIERS 8
|
||||
#define AR5416_NUM_2G_CAL_PIERS 4
|
||||
#define AR5416_NUM_5G_20_TARGET_POWERS 8
|
||||
#define AR5416_NUM_5G_40_TARGET_POWERS 8
|
||||
#define AR5416_NUM_2G_CCK_TARGET_POWERS 3
|
||||
#define AR5416_NUM_2G_20_TARGET_POWERS 4
|
||||
#define AR5416_NUM_2G_40_TARGET_POWERS 4
|
||||
#define AR5416_NUM_CTLS 24
|
||||
#define AR5416_NUM_BAND_EDGES 8
|
||||
#define AR5416_NUM_PD_GAINS 4
|
||||
#define AR5416_PD_GAINS_IN_MASK 4
|
||||
#define AR5416_PD_GAIN_ICEPTS 5
|
||||
#define AR5416_EEPROM_MODAL_SPURS 5
|
||||
#define AR5416_MAX_RATE_POWER 63
|
||||
#define AR5416_NUM_PDADC_VALUES 128
|
||||
#define AR5416_NUM_RATES 16
|
||||
#define AR5416_BCHAN_UNUSED 0xFF
|
||||
#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
|
||||
#define AR5416_EEPMISC_BIG_ENDIAN 0x01
|
||||
#define AR5416_MAX_CHAINS 3
|
||||
#define AR5416_ANT_16S 25
|
||||
|
||||
#define AR5416_NUM_ANT_CHAIN_FIELDS 7
|
||||
#define AR5416_NUM_ANT_COMMON_FIELDS 4
|
||||
#define AR5416_SIZE_ANT_CHAIN_FIELD 3
|
||||
#define AR5416_SIZE_ANT_COMMON_FIELD 4
|
||||
#define AR5416_ANT_CHAIN_MASK 0x7
|
||||
#define AR5416_ANT_COMMON_MASK 0xf
|
||||
#define AR5416_CHAIN_0_IDX 0
|
||||
#define AR5416_CHAIN_1_IDX 1
|
||||
#define AR5416_CHAIN_2_IDX 2
|
||||
|
||||
#define AR5416_PWR_TABLE_OFFSET -5
|
||||
#define AR5416_LEGACY_CHAINMASK 1
|
||||
|
||||
enum eeprom_param {
|
||||
EEP_NFTHRESH_5,
|
||||
EEP_NFTHRESH_2,
|
||||
EEP_MAC_MSW,
|
||||
EEP_MAC_MID,
|
||||
EEP_MAC_LSW,
|
||||
EEP_REG_0,
|
||||
EEP_REG_1,
|
||||
EEP_OP_CAP,
|
||||
EEP_OP_MODE,
|
||||
EEP_RF_SILENT,
|
||||
EEP_OB_5,
|
||||
EEP_DB_5,
|
||||
EEP_OB_2,
|
||||
EEP_DB_2,
|
||||
EEP_MINOR_REV,
|
||||
EEP_TX_MASK,
|
||||
EEP_RX_MASK,
|
||||
};
|
||||
|
||||
enum ar5416_rates {
|
||||
rate6mb, rate9mb, rate12mb, rate18mb,
|
||||
rate24mb, rate36mb, rate48mb, rate54mb,
|
||||
rate1l, rate2l, rate2s, rate5_5l,
|
||||
rate5_5s, rate11l, rate11s, rateXr,
|
||||
rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
|
||||
rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
|
||||
rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
|
||||
rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
|
||||
rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
|
||||
Ar5416RateSize
|
||||
};
|
||||
|
||||
struct base_eep_header {
|
||||
u_int16_t length;
|
||||
u_int16_t checksum;
|
||||
u_int16_t version;
|
||||
u_int8_t opCapFlags;
|
||||
u_int8_t eepMisc;
|
||||
u_int16_t regDmn[2];
|
||||
u_int8_t macAddr[6];
|
||||
u_int8_t rxMask;
|
||||
u_int8_t txMask;
|
||||
u_int16_t rfSilent;
|
||||
u_int16_t blueToothOptions;
|
||||
u_int16_t deviceCap;
|
||||
u_int32_t binBuildNumber;
|
||||
u_int8_t deviceType;
|
||||
u_int8_t pwdclkind;
|
||||
u_int8_t futureBase[32];
|
||||
} __packed;
|
||||
|
||||
struct spur_chan {
|
||||
u_int16_t spurChan;
|
||||
u_int8_t spurRangeLow;
|
||||
u_int8_t spurRangeHigh;
|
||||
} __packed;
|
||||
|
||||
struct modal_eep_header {
|
||||
u_int32_t antCtrlChain[AR5416_MAX_CHAINS];
|
||||
u_int32_t antCtrlCommon;
|
||||
u_int8_t antennaGainCh[AR5416_MAX_CHAINS];
|
||||
u_int8_t switchSettling;
|
||||
u_int8_t txRxAttenCh[AR5416_MAX_CHAINS];
|
||||
u_int8_t rxTxMarginCh[AR5416_MAX_CHAINS];
|
||||
u_int8_t adcDesiredSize;
|
||||
u_int8_t pgaDesiredSize;
|
||||
u_int8_t xlnaGainCh[AR5416_MAX_CHAINS];
|
||||
u_int8_t txEndToXpaOff;
|
||||
u_int8_t txEndToRxOn;
|
||||
u_int8_t txFrameToXpaOn;
|
||||
u_int8_t thresh62;
|
||||
u_int8_t noiseFloorThreshCh[AR5416_MAX_CHAINS];
|
||||
u_int8_t xpdGain;
|
||||
u_int8_t xpd;
|
||||
u_int8_t iqCalICh[AR5416_MAX_CHAINS];
|
||||
u_int8_t iqCalQCh[AR5416_MAX_CHAINS];
|
||||
u_int8_t pdGainOverlap;
|
||||
u_int8_t ob;
|
||||
u_int8_t db;
|
||||
u_int8_t xpaBiasLvl;
|
||||
u_int8_t pwrDecreaseFor2Chain;
|
||||
u_int8_t pwrDecreaseFor3Chain;
|
||||
u_int8_t txFrameToDataStart;
|
||||
u_int8_t txFrameToPaOn;
|
||||
u_int8_t ht40PowerIncForPdadc;
|
||||
u_int8_t bswAtten[AR5416_MAX_CHAINS];
|
||||
u_int8_t bswMargin[AR5416_MAX_CHAINS];
|
||||
u_int8_t swSettleHt40;
|
||||
u_int8_t xatten2Db[AR5416_MAX_CHAINS];
|
||||
u_int8_t xatten2Margin[AR5416_MAX_CHAINS];
|
||||
u_int8_t ob_ch1;
|
||||
u_int8_t db_ch1;
|
||||
u_int8_t useAnt1:1,
|
||||
force_xpaon:1,
|
||||
local_bias:1,
|
||||
femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1;
|
||||
u_int8_t futureModalar9280;
|
||||
u_int16_t xpaBiasLvlFreq[3];
|
||||
u_int8_t futureModal[6];
|
||||
|
||||
struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
|
||||
} __packed;
|
||||
|
||||
struct cal_data_per_freq {
|
||||
u_int8_t pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
|
||||
u_int8_t vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
|
||||
} __packed;
|
||||
|
||||
struct cal_target_power_leg {
|
||||
u_int8_t bChannel;
|
||||
u_int8_t tPow2x[4];
|
||||
} __packed;
|
||||
|
||||
struct cal_target_power_ht {
|
||||
u_int8_t bChannel;
|
||||
u_int8_t tPow2x[8];
|
||||
} __packed;
|
||||
|
||||
#ifdef __BIG_ENDIAN_BITFIELD
|
||||
struct cal_ctl_edges {
|
||||
u_int8_t bChannel;
|
||||
u_int8_t flag:2, tPower:6;
|
||||
} __packed;
|
||||
#else
|
||||
struct cal_ctl_edges {
|
||||
u_int8_t bChannel;
|
||||
u_int8_t tPower:6, flag:2;
|
||||
} __packed;
|
||||
#endif
|
||||
|
||||
struct cal_ctl_data {
|
||||
struct cal_ctl_edges
|
||||
ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
|
||||
} __packed;
|
||||
|
||||
struct ar5416_eeprom {
|
||||
struct base_eep_header baseEepHeader;
|
||||
u_int8_t custData[64];
|
||||
struct modal_eep_header modalHeader[2];
|
||||
u_int8_t calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
|
||||
u_int8_t calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
|
||||
struct cal_data_per_freq
|
||||
calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
|
||||
struct cal_data_per_freq
|
||||
calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
|
||||
struct cal_target_power_leg
|
||||
calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
|
||||
struct cal_target_power_ht
|
||||
calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
|
||||
struct cal_target_power_ht
|
||||
calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
|
||||
struct cal_target_power_leg
|
||||
calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
|
||||
struct cal_target_power_leg
|
||||
calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
|
||||
struct cal_target_power_ht
|
||||
calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
|
||||
struct cal_target_power_ht
|
||||
calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
|
||||
u_int8_t ctlIndex[AR5416_NUM_CTLS];
|
||||
struct cal_ctl_data ctlData[AR5416_NUM_CTLS];
|
||||
u_int8_t padding;
|
||||
} __packed;
|
||||
|
||||
struct ar5416IniArray {
|
||||
u_int32_t *ia_array;
|
||||
u_int32_t ia_rows;
|
||||
u_int32_t ia_columns;
|
||||
};
|
||||
|
||||
#define INIT_INI_ARRAY(iniarray, array, rows, columns) do { \
|
||||
(iniarray)->ia_array = (u_int32_t *)(array); \
|
||||
(iniarray)->ia_rows = (rows); \
|
||||
(iniarray)->ia_columns = (columns); \
|
||||
} while (0)
|
||||
|
||||
#define INI_RA(iniarray, row, column) \
|
||||
(((iniarray)->ia_array)[(row) * ((iniarray)->ia_columns) + (column)])
|
||||
|
||||
#define INIT_CAL(_perCal) do { \
|
||||
(_perCal)->calState = CAL_WAITING; \
|
||||
(_perCal)->calNext = NULL; \
|
||||
} while (0)
|
||||
|
||||
#define INSERT_CAL(_ahp, _perCal) \
|
||||
do { \
|
||||
if ((_ahp)->ah_cal_list_last == NULL) { \
|
||||
(_ahp)->ah_cal_list = \
|
||||
(_ahp)->ah_cal_list_last = (_perCal); \
|
||||
((_ahp)->ah_cal_list_last)->calNext = (_perCal); \
|
||||
} else { \
|
||||
((_ahp)->ah_cal_list_last)->calNext = (_perCal); \
|
||||
(_ahp)->ah_cal_list_last = (_perCal); \
|
||||
(_perCal)->calNext = (_ahp)->ah_cal_list; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
enum hal_cal_types {
|
||||
ADC_DC_INIT_CAL = 0x1,
|
||||
ADC_GAIN_CAL = 0x2,
|
||||
ADC_DC_CAL = 0x4,
|
||||
IQ_MISMATCH_CAL = 0x8
|
||||
};
|
||||
|
||||
enum hal_cal_state {
|
||||
CAL_INACTIVE,
|
||||
CAL_WAITING,
|
||||
CAL_RUNNING,
|
||||
CAL_DONE
|
||||
};
|
||||
|
||||
#define MIN_CAL_SAMPLES 1
|
||||
#define MAX_CAL_SAMPLES 64
|
||||
#define INIT_LOG_COUNT 5
|
||||
#define PER_MIN_LOG_COUNT 2
|
||||
#define PER_MAX_LOG_COUNT 10
|
||||
|
||||
struct hal_percal_data {
|
||||
enum hal_cal_types calType;
|
||||
u_int32_t calNumSamples;
|
||||
u_int32_t calCountMax;
|
||||
void (*calCollect) (struct ath_hal *);
|
||||
void (*calPostProc) (struct ath_hal *, u_int8_t);
|
||||
};
|
||||
|
||||
struct hal_cal_list {
|
||||
const struct hal_percal_data *calData;
|
||||
enum hal_cal_state calState;
|
||||
struct hal_cal_list *calNext;
|
||||
};
|
||||
|
||||
struct ath_hal_5416 {
|
||||
struct ath_hal ah;
|
||||
struct ar5416_eeprom ah_eeprom;
|
||||
u_int8_t ah_macaddr[ETH_ALEN];
|
||||
u_int8_t ah_bssid[ETH_ALEN];
|
||||
u_int8_t ah_bssidmask[ETH_ALEN];
|
||||
u_int16_t ah_assocId;
|
||||
int16_t ah_curchanRadIndex;
|
||||
u_int32_t ah_maskReg;
|
||||
struct ar5416Stats ah_stats;
|
||||
u_int32_t ah_txDescMask;
|
||||
u_int32_t ah_txOkInterruptMask;
|
||||
u_int32_t ah_txErrInterruptMask;
|
||||
u_int32_t ah_txDescInterruptMask;
|
||||
u_int32_t ah_txEolInterruptMask;
|
||||
u_int32_t ah_txUrnInterruptMask;
|
||||
struct hal_tx_queue_info ah_txq[HAL_NUM_TX_QUEUES];
|
||||
enum hal_power_mode ah_powerMode;
|
||||
enum hal_bool ah_chipFullSleep;
|
||||
u_int32_t ah_atimWindow;
|
||||
enum hal_ant_setting ah_diversityControl;
|
||||
u_int16_t ah_antennaSwitchSwap;
|
||||
enum hal_cal_types ah_suppCals;
|
||||
struct hal_cal_list ah_iqCalData;
|
||||
struct hal_cal_list ah_adcGainCalData;
|
||||
struct hal_cal_list ah_adcDcCalInitData;
|
||||
struct hal_cal_list ah_adcDcCalData;
|
||||
struct hal_cal_list *ah_cal_list;
|
||||
struct hal_cal_list *ah_cal_list_last;
|
||||
struct hal_cal_list *ah_cal_list_curr;
|
||||
#define ah_totalPowerMeasI ah_Meas0.unsign
|
||||
#define ah_totalPowerMeasQ ah_Meas1.unsign
|
||||
#define ah_totalIqCorrMeas ah_Meas2.sign
|
||||
#define ah_totalAdcIOddPhase ah_Meas0.unsign
|
||||
#define ah_totalAdcIEvenPhase ah_Meas1.unsign
|
||||
#define ah_totalAdcQOddPhase ah_Meas2.unsign
|
||||
#define ah_totalAdcQEvenPhase ah_Meas3.unsign
|
||||
#define ah_totalAdcDcOffsetIOddPhase ah_Meas0.sign
|
||||
#define ah_totalAdcDcOffsetIEvenPhase ah_Meas1.sign
|
||||
#define ah_totalAdcDcOffsetQOddPhase ah_Meas2.sign
|
||||
#define ah_totalAdcDcOffsetQEvenPhase ah_Meas3.sign
|
||||
union {
|
||||
u_int32_t unsign[AR5416_MAX_CHAINS];
|
||||
int32_t sign[AR5416_MAX_CHAINS];
|
||||
} ah_Meas0;
|
||||
union {
|
||||
u_int32_t unsign[AR5416_MAX_CHAINS];
|
||||
int32_t sign[AR5416_MAX_CHAINS];
|
||||
} ah_Meas1;
|
||||
union {
|
||||
u_int32_t unsign[AR5416_MAX_CHAINS];
|
||||
int32_t sign[AR5416_MAX_CHAINS];
|
||||
} ah_Meas2;
|
||||
union {
|
||||
u_int32_t unsign[AR5416_MAX_CHAINS];
|
||||
int32_t sign[AR5416_MAX_CHAINS];
|
||||
} ah_Meas3;
|
||||
u_int16_t ah_CalSamples;
|
||||
u_int32_t ah_tx6PowerInHalfDbm;
|
||||
u_int32_t ah_staId1Defaults;
|
||||
u_int32_t ah_miscMode;
|
||||
enum hal_bool ah_tpcEnabled;
|
||||
u_int32_t ah_beaconInterval;
|
||||
enum {
|
||||
AUTO_32KHZ,
|
||||
USE_32KHZ,
|
||||
DONT_USE_32KHZ,
|
||||
} ah_enable32kHzClock;
|
||||
u_int32_t *ah_analogBank0Data;
|
||||
u_int32_t *ah_analogBank1Data;
|
||||
u_int32_t *ah_analogBank2Data;
|
||||
u_int32_t *ah_analogBank3Data;
|
||||
u_int32_t *ah_analogBank6Data;
|
||||
u_int32_t *ah_analogBank6TPCData;
|
||||
u_int32_t *ah_analogBank7Data;
|
||||
u_int32_t *ah_addac5416_21;
|
||||
u_int32_t *ah_bank6Temp;
|
||||
u_int32_t ah_ofdmTxPower;
|
||||
int16_t ah_txPowerIndexOffset;
|
||||
u_int ah_slottime;
|
||||
u_int ah_acktimeout;
|
||||
u_int ah_ctstimeout;
|
||||
u_int ah_globaltxtimeout;
|
||||
u_int8_t ah_gBeaconRate;
|
||||
u_int32_t ah_gpioSelect;
|
||||
u_int32_t ah_polarity;
|
||||
u_int32_t ah_gpioBit;
|
||||
enum hal_bool ah_eepEnabled;
|
||||
u_int32_t ah_procPhyErr;
|
||||
enum hal_bool ah_hasHwPhyCounters;
|
||||
u_int32_t ah_aniPeriod;
|
||||
struct ar5416AniState *ah_curani;
|
||||
struct ar5416AniState ah_ani[255];
|
||||
int ah_totalSizeDesired[5];
|
||||
int ah_coarseHigh[5];
|
||||
int ah_coarseLow[5];
|
||||
int ah_firpwr[5];
|
||||
u_int16_t ah_ratesArray[16];
|
||||
u_int32_t ah_intrTxqs;
|
||||
enum hal_bool ah_intrMitigation;
|
||||
u_int32_t ah_cycleCount;
|
||||
u_int32_t ah_ctlBusy;
|
||||
u_int32_t ah_extBusy;
|
||||
enum hal_ht_extprotspacing ah_extprotspacing;
|
||||
u_int8_t ah_txchainmask;
|
||||
u_int8_t ah_rxchainmask;
|
||||
int ah_hwp;
|
||||
void __iomem *ah_cal_mem;
|
||||
enum hal_ani_cmd ah_ani_function;
|
||||
struct ar5416IniArray ah_iniModes;
|
||||
struct ar5416IniArray ah_iniCommon;
|
||||
struct ar5416IniArray ah_iniBank0;
|
||||
struct ar5416IniArray ah_iniBB_RfGain;
|
||||
struct ar5416IniArray ah_iniBank1;
|
||||
struct ar5416IniArray ah_iniBank2;
|
||||
struct ar5416IniArray ah_iniBank3;
|
||||
struct ar5416IniArray ah_iniBank6;
|
||||
struct ar5416IniArray ah_iniBank6TPC;
|
||||
struct ar5416IniArray ah_iniBank7;
|
||||
struct ar5416IniArray ah_iniAddac;
|
||||
struct ar5416IniArray ah_iniPcieSerdes;
|
||||
struct ar5416IniArray ah_iniModesAdditional;
|
||||
};
|
||||
#define AH5416(_ah) ((struct ath_hal_5416 *)(_ah))
|
||||
|
||||
#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
|
||||
|
||||
#define IS_5416_EMU(ah) \
|
||||
((ah->ah_devid == AR5416_DEVID_EMU) || \
|
||||
(ah->ah_devid == AR5416_DEVID_EMU_PCIE))
|
||||
|
||||
#define ar5416RfDetach(ah) do { \
|
||||
if (AH5416(ah)->ah_rfHal.rfDetach != NULL) \
|
||||
AH5416(ah)->ah_rfHal.rfDetach(ah); \
|
||||
} while (0)
|
||||
|
||||
#define ath9k_hw_use_flash(_ah) \
|
||||
(!(_ah->ah_flags & AH_USE_EEPROM))
|
||||
|
||||
|
||||
#define DO_DELAY(x) do { \
|
||||
if ((++(x) % 64) == 0) \
|
||||
udelay(1); \
|
||||
} while (0)
|
||||
|
||||
#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
|
||||
int r; \
|
||||
for (r = 0; r < ((iniarray)->ia_rows); r++) { \
|
||||
REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
|
||||
INI_RA((iniarray), r, (column))); \
|
||||
DO_DELAY(regWr); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define BASE_ACTIVATE_DELAY 100
|
||||
#define RTC_PLL_SETTLE_DELAY 1000
|
||||
#define COEF_SCALE_S 24
|
||||
#define HT40_CHANNEL_CENTER_SHIFT 10
|
||||
|
||||
#define ar5416CheckOpMode(_opmode) \
|
||||
((_opmode == HAL_M_STA) || (_opmode == HAL_M_IBSS) || \
|
||||
(_opmode == HAL_M_HOSTAP) || (_opmode == HAL_M_MONITOR))
|
||||
|
||||
#define AR5416_EEPROM_MAGIC_OFFSET 0x0
|
||||
|
||||
#define AR5416_EEPROM_S 2
|
||||
#define AR5416_EEPROM_OFFSET 0x2000
|
||||
#define AR5416_EEPROM_START_ADDR \
|
||||
(AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
|
||||
#define AR5416_EEPROM_MAX 0xae0
|
||||
#define ar5416_get_eep_ver(_ahp) \
|
||||
(((_ahp)->ah_eeprom.baseEepHeader.version >> 12) & 0xF)
|
||||
#define ar5416_get_eep_rev(_ahp) \
|
||||
(((_ahp)->ah_eeprom.baseEepHeader.version) & 0xFFF)
|
||||
#define ar5416_get_ntxchains(_txchainmask) \
|
||||
(((_txchainmask >> 2) & 1) + \
|
||||
((_txchainmask >> 1) & 1) + (_txchainmask & 1))
|
||||
|
||||
#define IS_EEP_MINOR_V3(_ahp) \
|
||||
(ath9k_hw_get_eeprom((_ahp), EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_3)
|
||||
|
||||
#define FIXED_CCA_THRESHOLD 15
|
||||
|
||||
#ifdef __BIG_ENDIAN
|
||||
#define AR5416_EEPROM_MAGIC 0x5aa5
|
||||
#else
|
||||
#define AR5416_EEPROM_MAGIC 0xa55a
|
||||
#endif
|
||||
|
||||
#define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
|
||||
|
||||
#define ATH9K_ANTENNA0_CHAINMASK 0x1
|
||||
#define ATH9K_ANTENNA1_CHAINMASK 0x2
|
||||
|
||||
#define ATH9K_NUM_DMA_DEBUG_REGS 8
|
||||
#define ATH9K_NUM_QUEUES 10
|
||||
|
||||
#define HAL_NOISE_IMMUNE_MAX 4
|
||||
#define HAL_SPUR_IMMUNE_MAX 7
|
||||
#define HAL_FIRST_STEP_MAX 2
|
||||
|
||||
#define HAL_ANI_OFDM_TRIG_HIGH 500
|
||||
#define HAL_ANI_OFDM_TRIG_LOW 200
|
||||
#define HAL_ANI_CCK_TRIG_HIGH 200
|
||||
#define HAL_ANI_CCK_TRIG_LOW 100
|
||||
#define HAL_ANI_NOISE_IMMUNE_LVL 4
|
||||
#define HAL_ANI_USE_OFDM_WEAK_SIG AH_TRUE
|
||||
#define HAL_ANI_CCK_WEAK_SIG_THR AH_FALSE
|
||||
#define HAL_ANI_SPUR_IMMUNE_LVL 7
|
||||
#define HAL_ANI_FIRSTEP_LVL 0
|
||||
#define HAL_ANI_RSSI_THR_HIGH 40
|
||||
#define HAL_ANI_RSSI_THR_LOW 7
|
||||
#define HAL_ANI_PERIOD 100
|
||||
|
||||
#define AR_GPIOD_MASK 0x00001FFF
|
||||
#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
|
||||
|
||||
#define MAX_ANALOG_START 319
|
||||
|
||||
#define HAL_EP_RND(x, mul) \
|
||||
((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
|
||||
#define BEACON_RSSI(ahp) \
|
||||
HAL_EP_RND(ahp->ah_stats.ast_nodestats.ns_avgbrssi, \
|
||||
HAL_RSSI_EP_MULTIPLIER)
|
||||
|
||||
#define ah_mibStats ah_stats.ast_mibstats
|
||||
|
||||
#define AH_TIMEOUT 100000
|
||||
#define AH_TIME_QUANTUM 10
|
||||
|
||||
#define IS(_c, _f) (((_c)->channelFlags & _f) || 0)
|
||||
|
||||
#define AR_KEYTABLE_SIZE 128
|
||||
#define POWER_UP_TIME 200000
|
||||
|
||||
#define EXT_ADDITIVE (0x8000)
|
||||
#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
|
||||
#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
|
||||
#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
|
||||
|
||||
#define SUB_NUM_CTL_MODES_AT_5G_40 2
|
||||
#define SUB_NUM_CTL_MODES_AT_2G_40 3
|
||||
#define SPUR_RSSI_THRESH 40
|
||||
|
||||
#define TU_TO_USEC(_tu) ((_tu) << 10)
|
||||
|
||||
#define CAB_TIMEOUT_VAL 10
|
||||
#define BEACON_TIMEOUT_VAL 10
|
||||
#define MIN_BEACON_TIMEOUT_VAL 1
|
||||
#define SLEEP_SLOP 3
|
||||
|
||||
#define CCK_SIFS_TIME 10
|
||||
#define CCK_PREAMBLE_BITS 144
|
||||
#define CCK_PLCP_BITS 48
|
||||
|
||||
#define OFDM_SIFS_TIME 16
|
||||
#define OFDM_PREAMBLE_TIME 20
|
||||
#define OFDM_PLCP_BITS 22
|
||||
#define OFDM_SYMBOL_TIME 4
|
||||
|
||||
#define OFDM_SIFS_TIME_HALF 32
|
||||
#define OFDM_PREAMBLE_TIME_HALF 40
|
||||
#define OFDM_PLCP_BITS_HALF 22
|
||||
#define OFDM_SYMBOL_TIME_HALF 8
|
||||
|
||||
#define OFDM_SIFS_TIME_QUARTER 64
|
||||
#define OFDM_PREAMBLE_TIME_QUARTER 80
|
||||
#define OFDM_PLCP_BITS_QUARTER 22
|
||||
#define OFDM_SYMBOL_TIME_QUARTER 16
|
||||
|
||||
u_int32_t ath9k_hw_get_eeprom(struct ath_hal_5416 *ahp,
|
||||
enum eeprom_param param);
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,451 @@
|
||||
/*
|
||||
* Copyright (c) 2008 Atheros Communications Inc.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "ath9k.h"
|
||||
#include "hw.h"
|
||||
#include "reg.h"
|
||||
#include "phy.h"
|
||||
|
||||
void
|
||||
ath9k_hw_write_regs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
|
||||
int regWrites)
|
||||
{
|
||||
struct ath_hal_5416 *ahp = AH5416(ah);
|
||||
|
||||
REG_WRITE_ARRAY(&ahp->ah_iniBB_RfGain, freqIndex, regWrites);
|
||||
}
|
||||
|
||||
enum hal_bool
|
||||
ath9k_hw_set_channel(struct ath_hal *ah, struct hal_channel_internal *chan)
|
||||
{
|
||||
u_int32_t channelSel = 0;
|
||||
u_int32_t bModeSynth = 0;
|
||||
u_int32_t aModeRefSel = 0;
|
||||
u_int32_t reg32 = 0;
|
||||
u_int16_t freq;
|
||||
struct chan_centers centers;
|
||||
|
||||
ath9k_hw_get_channel_centers(ah, chan, ¢ers);
|
||||
freq = centers.synth_center;
|
||||
|
||||
if (freq < 4800) {
|
||||
u_int32_t txctl;
|
||||
|
||||
if (((freq - 2192) % 5) == 0) {
|
||||
channelSel = ((freq - 672) * 2 - 3040) / 10;
|
||||
bModeSynth = 0;
|
||||
} else if (((freq - 2224) % 5) == 0) {
|
||||
channelSel = ((freq - 704) * 2 - 3040) / 10;
|
||||
bModeSynth = 1;
|
||||
} else {
|
||||
HDPRINTF(ah, HAL_DBG_CHANNEL,
|
||||
"%s: invalid channel %u MHz\n", __func__,
|
||||
freq);
|
||||
return AH_FALSE;
|
||||
}
|
||||
|
||||
channelSel = (channelSel << 2) & 0xff;
|
||||
channelSel = ath9k_hw_reverse_bits(channelSel, 8);
|
||||
|
||||
txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
|
||||
if (freq == 2484) {
|
||||
|
||||
REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
|
||||
txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
|
||||
} else {
|
||||
REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
|
||||
txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
|
||||
}
|
||||
|
||||
} else if ((freq % 20) == 0 && freq >= 5120) {
|
||||
channelSel =
|
||||
ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
|
||||
aModeRefSel = ath9k_hw_reverse_bits(1, 2);
|
||||
} else if ((freq % 10) == 0) {
|
||||
channelSel =
|
||||
ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
|
||||
if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
|
||||
aModeRefSel = ath9k_hw_reverse_bits(2, 2);
|
||||
else
|
||||
aModeRefSel = ath9k_hw_reverse_bits(1, 2);
|
||||
} else if ((freq % 5) == 0) {
|
||||
channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
|
||||
aModeRefSel = ath9k_hw_reverse_bits(1, 2);
|
||||
} else {
|
||||
HDPRINTF(ah, HAL_DBG_CHANNEL,
|
||||
"%s: invalid channel %u MHz\n", __func__, freq);
|
||||
return AH_FALSE;
|
||||
}
|
||||
|
||||
reg32 =
|
||||
(channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
|
||||
(1 << 5) | 0x1;
|
||||
|
||||
REG_WRITE(ah, AR_PHY(0x37), reg32);
|
||||
|
||||
ah->ah_curchan = chan;
|
||||
|
||||
AH5416(ah)->ah_curchanRadIndex = -1;
|
||||
|
||||
return AH_TRUE;
|
||||
}
|
||||
|
||||
enum hal_bool
|
||||
ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
|
||||
struct hal_channel_internal *chan)
|
||||
{
|
||||
u_int16_t bMode, fracMode, aModeRefSel = 0;
|
||||
u_int32_t freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
|
||||
struct chan_centers centers;
|
||||
u_int32_t refDivA = 24;
|
||||
|
||||
ath9k_hw_get_channel_centers(ah, chan, ¢ers);
|
||||
freq = centers.synth_center;
|
||||
|
||||
reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
|
||||
reg32 &= 0xc0000000;
|
||||
|
||||
if (freq < 4800) {
|
||||
u_int32_t txctl;
|
||||
|
||||
bMode = 1;
|
||||
fracMode = 1;
|
||||
aModeRefSel = 0;
|
||||
channelSel = (freq * 0x10000) / 15;
|
||||
|
||||
txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
|
||||
if (freq == 2484) {
|
||||
|
||||
REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
|
||||
txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
|
||||
} else {
|
||||
REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
|
||||
txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
|
||||
}
|
||||
} else {
|
||||
bMode = 0;
|
||||
fracMode = 0;
|
||||
|
||||
if ((freq % 20) == 0) {
|
||||
aModeRefSel = 3;
|
||||
} else if ((freq % 10) == 0) {
|
||||
aModeRefSel = 2;
|
||||
} else {
|
||||
aModeRefSel = 0;
|
||||
|
||||
fracMode = 1;
|
||||
refDivA = 1;
|
||||
channelSel = (freq * 0x8000) / 15;
|
||||
|
||||
OS_REG_RMW_FIELD(ah, AR_AN_SYNTH9,
|
||||
AR_AN_SYNTH9_REFDIVA, refDivA);
|
||||
}
|
||||
if (!fracMode) {
|
||||
ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
|
||||
channelSel = ndiv & 0x1ff;
|
||||
channelFrac = (ndiv & 0xfffffe00) * 2;
|
||||
channelSel = (channelSel << 17) | channelFrac;
|
||||
}
|
||||
}
|
||||
|
||||
reg32 = reg32 |
|
||||
(bMode << 29) |
|
||||
(fracMode << 28) | (aModeRefSel << 26) | (channelSel);
|
||||
|
||||
REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
|
||||
|
||||
ah->ah_curchan = chan;
|
||||
|
||||
AH5416(ah)->ah_curchanRadIndex = -1;
|
||||
|
||||
return AH_TRUE;
|
||||
}
|
||||
|
||||
static void
|
||||
ath9k_phy_modify_rx_buffer(u_int32_t *rfBuf, u_int32_t reg32,
|
||||
u_int32_t numBits, u_int32_t firstBit,
|
||||
u_int32_t column)
|
||||
{
|
||||
u_int32_t tmp32, mask, arrayEntry, lastBit;
|
||||
int32_t bitPosition, bitsLeft;
|
||||
|
||||
tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
|
||||
arrayEntry = (firstBit - 1) / 8;
|
||||
bitPosition = (firstBit - 1) % 8;
|
||||
bitsLeft = numBits;
|
||||
while (bitsLeft > 0) {
|
||||
lastBit = (bitPosition + bitsLeft > 8) ?
|
||||
8 : bitPosition + bitsLeft;
|
||||
mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
|
||||
(column * 8);
|
||||
rfBuf[arrayEntry] &= ~mask;
|
||||
rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
|
||||
(column * 8)) & mask;
|
||||
bitsLeft -= 8 - bitPosition;
|
||||
tmp32 = tmp32 >> (8 - bitPosition);
|
||||
bitPosition = 0;
|
||||
arrayEntry++;
|
||||
}
|
||||
}
|
||||
|
||||
enum hal_bool
|
||||
ath9k_hw_set_rf_regs(struct ath_hal *ah, struct hal_channel_internal *chan,
|
||||
u_int16_t modesIndex)
|
||||
{
|
||||
struct ath_hal_5416 *ahp = AH5416(ah);
|
||||
|
||||
u_int32_t eepMinorRev;
|
||||
u_int32_t ob5GHz = 0, db5GHz = 0;
|
||||
u_int32_t ob2GHz = 0, db2GHz = 0;
|
||||
int regWrites = 0;
|
||||
|
||||
if (AR_SREV_9280_10_OR_LATER(ah))
|
||||
return AH_TRUE;
|
||||
|
||||
eepMinorRev = ath9k_hw_get_eeprom(ahp, EEP_MINOR_REV);
|
||||
|
||||
RF_BANK_SETUP(ahp->ah_analogBank0Data, &ahp->ah_iniBank0, 1);
|
||||
|
||||
RF_BANK_SETUP(ahp->ah_analogBank1Data, &ahp->ah_iniBank1, 1);
|
||||
|
||||
RF_BANK_SETUP(ahp->ah_analogBank2Data, &ahp->ah_iniBank2, 1);
|
||||
|
||||
RF_BANK_SETUP(ahp->ah_analogBank3Data, &ahp->ah_iniBank3,
|
||||
modesIndex);
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < ahp->ah_iniBank6TPC.ia_rows; i++) {
|
||||
ahp->ah_analogBank6Data[i] =
|
||||
INI_RA(&ahp->ah_iniBank6TPC, i, modesIndex);
|
||||
}
|
||||
}
|
||||
|
||||
if (eepMinorRev >= 2) {
|
||||
if (IS_CHAN_2GHZ(chan)) {
|
||||
ob2GHz = ath9k_hw_get_eeprom(ahp, EEP_OB_2);
|
||||
db2GHz = ath9k_hw_get_eeprom(ahp, EEP_DB_2);
|
||||
ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data,
|
||||
ob2GHz, 3, 197, 0);
|
||||
ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data,
|
||||
db2GHz, 3, 194, 0);
|
||||
} else {
|
||||
ob5GHz = ath9k_hw_get_eeprom(ahp, EEP_OB_5);
|
||||
db5GHz = ath9k_hw_get_eeprom(ahp, EEP_DB_5);
|
||||
ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data,
|
||||
ob5GHz, 3, 203, 0);
|
||||
ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data,
|
||||
db5GHz, 3, 200, 0);
|
||||
}
|
||||
}
|
||||
|
||||
RF_BANK_SETUP(ahp->ah_analogBank7Data, &ahp->ah_iniBank7, 1);
|
||||
|
||||
REG_WRITE_RF_ARRAY(&ahp->ah_iniBank0, ahp->ah_analogBank0Data,
|
||||
regWrites);
|
||||
REG_WRITE_RF_ARRAY(&ahp->ah_iniBank1, ahp->ah_analogBank1Data,
|
||||
regWrites);
|
||||
REG_WRITE_RF_ARRAY(&ahp->ah_iniBank2, ahp->ah_analogBank2Data,
|
||||
regWrites);
|
||||
REG_WRITE_RF_ARRAY(&ahp->ah_iniBank3, ahp->ah_analogBank3Data,
|
||||
regWrites);
|
||||
REG_WRITE_RF_ARRAY(&ahp->ah_iniBank6TPC, ahp->ah_analogBank6Data,
|
||||
regWrites);
|
||||
REG_WRITE_RF_ARRAY(&ahp->ah_iniBank7, ahp->ah_analogBank7Data,
|
||||
regWrites);
|
||||
|
||||
return AH_TRUE;
|
||||
}
|
||||
|
||||
void
|
||||
ath9k_hw_rfdetach(struct ath_hal *ah)
|
||||
{
|
||||
struct ath_hal_5416 *ahp = AH5416(ah);
|
||||
|
||||
if (ahp->ah_analogBank0Data != NULL) {
|
||||
kfree(ahp->ah_analogBank0Data);
|
||||
ahp->ah_analogBank0Data = NULL;
|
||||
}
|
||||
if (ahp->ah_analogBank1Data != NULL) {
|
||||
kfree(ahp->ah_analogBank1Data);
|
||||
ahp->ah_analogBank1Data = NULL;
|
||||
}
|
||||
if (ahp->ah_analogBank2Data != NULL) {
|
||||
kfree(ahp->ah_analogBank2Data);
|
||||
ahp->ah_analogBank2Data = NULL;
|
||||
}
|
||||
if (ahp->ah_analogBank3Data != NULL) {
|
||||
kfree(ahp->ah_analogBank3Data);
|
||||
ahp->ah_analogBank3Data = NULL;
|
||||
}
|
||||
if (ahp->ah_analogBank6Data != NULL) {
|
||||
kfree(ahp->ah_analogBank6Data);
|
||||
ahp->ah_analogBank6Data = NULL;
|
||||
}
|
||||
if (ahp->ah_analogBank6TPCData != NULL) {
|
||||
kfree(ahp->ah_analogBank6TPCData);
|
||||
ahp->ah_analogBank6TPCData = NULL;
|
||||
}
|
||||
if (ahp->ah_analogBank7Data != NULL) {
|
||||
kfree(ahp->ah_analogBank7Data);
|
||||
ahp->ah_analogBank7Data = NULL;
|
||||
}
|
||||
if (ahp->ah_addac5416_21 != NULL) {
|
||||
kfree(ahp->ah_addac5416_21);
|
||||
ahp->ah_addac5416_21 = NULL;
|
||||
}
|
||||
if (ahp->ah_bank6Temp != NULL) {
|
||||
kfree(ahp->ah_bank6Temp);
|
||||
ahp->ah_bank6Temp = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
enum hal_bool
|
||||
ath9k_hw_get_chip_power_limits(struct ath_hal *ah,
|
||||
struct hal_channel *chans, u_int32_t nchans)
|
||||
{
|
||||
enum hal_bool retVal = AH_TRUE;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nchans; i++) {
|
||||
chans[i].maxTxPower = AR5416_MAX_RATE_POWER;
|
||||
chans[i].minTxPower = AR5416_MAX_RATE_POWER;
|
||||
}
|
||||
return retVal;
|
||||
}
|
||||
|
||||
|
||||
enum hal_bool ath9k_hw_init_rf(struct ath_hal *ah, enum hal_status *status)
|
||||
{
|
||||
struct ath_hal_5416 *ahp = AH5416(ah);
|
||||
|
||||
if (!AR_SREV_9280_10_OR_LATER(ah)) {
|
||||
|
||||
ahp->ah_analogBank0Data =
|
||||
kzalloc((sizeof(u_int32_t) *
|
||||
ahp->ah_iniBank0.ia_rows), GFP_KERNEL);
|
||||
ahp->ah_analogBank1Data =
|
||||
kzalloc((sizeof(u_int32_t) *
|
||||
ahp->ah_iniBank1.ia_rows), GFP_KERNEL);
|
||||
ahp->ah_analogBank2Data =
|
||||
kzalloc((sizeof(u_int32_t) *
|
||||
ahp->ah_iniBank2.ia_rows), GFP_KERNEL);
|
||||
ahp->ah_analogBank3Data =
|
||||
kzalloc((sizeof(u_int32_t) *
|
||||
ahp->ah_iniBank3.ia_rows), GFP_KERNEL);
|
||||
ahp->ah_analogBank6Data =
|
||||
kzalloc((sizeof(u_int32_t) *
|
||||
ahp->ah_iniBank6.ia_rows), GFP_KERNEL);
|
||||
ahp->ah_analogBank6TPCData =
|
||||
kzalloc((sizeof(u_int32_t) *
|
||||
ahp->ah_iniBank6TPC.ia_rows), GFP_KERNEL);
|
||||
ahp->ah_analogBank7Data =
|
||||
kzalloc((sizeof(u_int32_t) *
|
||||
ahp->ah_iniBank7.ia_rows), GFP_KERNEL);
|
||||
|
||||
if (ahp->ah_analogBank0Data == NULL
|
||||
|| ahp->ah_analogBank1Data == NULL
|
||||
|| ahp->ah_analogBank2Data == NULL
|
||||
|| ahp->ah_analogBank3Data == NULL
|
||||
|| ahp->ah_analogBank6Data == NULL
|
||||
|| ahp->ah_analogBank6TPCData == NULL
|
||||
|| ahp->ah_analogBank7Data == NULL) {
|
||||
HDPRINTF(ah, HAL_DBG_MALLOC,
|
||||
"%s: cannot allocate RF banks\n",
|
||||
__func__);
|
||||
*status = HAL_ENOMEM;
|
||||
return AH_FALSE;
|
||||
}
|
||||
|
||||
ahp->ah_addac5416_21 =
|
||||
kzalloc((sizeof(u_int32_t) *
|
||||
ahp->ah_iniAddac.ia_rows *
|
||||
ahp->ah_iniAddac.ia_columns), GFP_KERNEL);
|
||||
if (ahp->ah_addac5416_21 == NULL) {
|
||||
HDPRINTF(ah, HAL_DBG_MALLOC,
|
||||
"%s: cannot allocate ah_addac5416_21\n",
|
||||
__func__);
|
||||
*status = HAL_ENOMEM;
|
||||
return AH_FALSE;
|
||||
}
|
||||
|
||||
ahp->ah_bank6Temp =
|
||||
kzalloc((sizeof(u_int32_t) *
|
||||
ahp->ah_iniBank6.ia_rows), GFP_KERNEL);
|
||||
if (ahp->ah_bank6Temp == NULL) {
|
||||
HDPRINTF(ah, HAL_DBG_MALLOC,
|
||||
"%s: cannot allocate ah_bank6Temp\n",
|
||||
__func__);
|
||||
*status = HAL_ENOMEM;
|
||||
return AH_FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
return AH_TRUE;
|
||||
}
|
||||
|
||||
void
|
||||
ath9k_hw_decrease_chain_power(struct ath_hal *ah, struct hal_channel *chan)
|
||||
{
|
||||
int i, regWrites = 0;
|
||||
struct ath_hal_5416 *ahp = AH5416(ah);
|
||||
u_int32_t bank6SelMask;
|
||||
u_int32_t *bank6Temp = ahp->ah_bank6Temp;
|
||||
|
||||
switch (ahp->ah_diversityControl) {
|
||||
case HAL_ANT_FIXED_A:
|
||||
bank6SelMask =
|
||||
(ahp->
|
||||
ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_0 :
|
||||
REDUCE_CHAIN_1;
|
||||
break;
|
||||
case HAL_ANT_FIXED_B:
|
||||
bank6SelMask =
|
||||
(ahp->
|
||||
ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_1 :
|
||||
REDUCE_CHAIN_0;
|
||||
break;
|
||||
case HAL_ANT_VARIABLE:
|
||||
return;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
break;
|
||||
}
|
||||
|
||||
for (i = 0; i < ahp->ah_iniBank6.ia_rows; i++)
|
||||
bank6Temp[i] = ahp->ah_analogBank6Data[i];
|
||||
|
||||
REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask);
|
||||
|
||||
ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 189, 0);
|
||||
ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 190, 0);
|
||||
ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 191, 0);
|
||||
ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 192, 0);
|
||||
ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 193, 0);
|
||||
ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 222, 0);
|
||||
ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 245, 0);
|
||||
ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0);
|
||||
ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0);
|
||||
|
||||
REG_WRITE_RF_ARRAY(&ahp->ah_iniBank6, bank6Temp, regWrites);
|
||||
|
||||
REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053);
|
||||
#ifdef ALTER_SWITCH
|
||||
REG_WRITE(ah, PHY_SWITCH_CHAIN_0,
|
||||
(REG_READ(ah, PHY_SWITCH_CHAIN_0) & ~0x38)
|
||||
| ((REG_READ(ah, PHY_SWITCH_CHAIN_0) >> 3) & 0x38));
|
||||
#endif
|
||||
}
|
||||
@ -0,0 +1,543 @@
|
||||
/*
|
||||
* Copyright (c) 2008 Atheros Communications Inc.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef PHY_H
|
||||
#define PHY_H
|
||||
|
||||
enum hal_bool ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
|
||||
struct hal_channel_internal
|
||||
*chan);
|
||||
enum hal_bool ath9k_hw_set_channel(struct ath_hal *ah,
|
||||
struct hal_channel_internal *chan);
|
||||
void ath9k_hw_write_regs(struct ath_hal *ah, u_int modesIndex,
|
||||
u_int freqIndex, int regWrites);
|
||||
enum hal_bool ath9k_hw_set_rf_regs(struct ath_hal *ah,
|
||||
struct hal_channel_internal *chan,
|
||||
u_int16_t modesIndex);
|
||||
void ath9k_hw_decrease_chain_power(struct ath_hal *ah,
|
||||
struct hal_channel *chan);
|
||||
enum hal_bool ath9k_hw_init_rf(struct ath_hal *ah,
|
||||
enum hal_status *status);
|
||||
|
||||
#define AR_PHY_BASE 0x9800
|
||||
#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))
|
||||
|
||||
#define AR_PHY_TEST 0x9800
|
||||
#define PHY_AGC_CLR 0x10000000
|
||||
#define RFSILENT_BB 0x00002000
|
||||
|
||||
#define AR_PHY_TURBO 0x9804
|
||||
#define AR_PHY_FC_TURBO_MODE 0x00000001
|
||||
#define AR_PHY_FC_TURBO_SHORT 0x00000002
|
||||
#define AR_PHY_FC_DYN2040_EN 0x00000004
|
||||
#define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
|
||||
#define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
|
||||
#define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
|
||||
#define AR_PHY_FC_HT_EN 0x00000040
|
||||
#define AR_PHY_FC_SHORT_GI_40 0x00000080
|
||||
#define AR_PHY_FC_WALSH 0x00000100
|
||||
#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200
|
||||
|
||||
#define AR_PHY_TIMING2 0x9810
|
||||
#define AR_PHY_TIMING3 0x9814
|
||||
#define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000
|
||||
#define AR_PHY_TIMING3_DSC_MAN_S 17
|
||||
#define AR_PHY_TIMING3_DSC_EXP 0x0001E000
|
||||
#define AR_PHY_TIMING3_DSC_EXP_S 13
|
||||
|
||||
#define AR_PHY_CHIP_ID 0x9818
|
||||
#define AR_PHY_CHIP_ID_REV_0 0x80
|
||||
#define AR_PHY_CHIP_ID_REV_1 0x81
|
||||
#define AR_PHY_CHIP_ID_9160_REV_0 0xb0
|
||||
|
||||
#define AR_PHY_ACTIVE 0x981C
|
||||
#define AR_PHY_ACTIVE_EN 0x00000001
|
||||
#define AR_PHY_ACTIVE_DIS 0x00000000
|
||||
|
||||
#define AR_PHY_RF_CTL2 0x9824
|
||||
#define AR_PHY_TX_END_DATA_START 0x000000FF
|
||||
#define AR_PHY_TX_END_DATA_START_S 0
|
||||
#define AR_PHY_TX_END_PA_ON 0x0000FF00
|
||||
#define AR_PHY_TX_END_PA_ON_S 8
|
||||
|
||||
#define AR_PHY_RF_CTL3 0x9828
|
||||
#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
|
||||
#define AR_PHY_TX_END_TO_A2_RX_ON_S 16
|
||||
|
||||
#define AR_PHY_ADC_CTL 0x982C
|
||||
#define AR_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003
|
||||
#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0
|
||||
#define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000
|
||||
#define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000
|
||||
#define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000
|
||||
#define AR_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000
|
||||
#define AR_PHY_ADC_CTL_ON_INBUFGAIN_S 16
|
||||
|
||||
#define AR_PHY_ADC_SERIAL_CTL 0x9830
|
||||
#define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000
|
||||
#define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001
|
||||
|
||||
#define AR_PHY_RF_CTL4 0x9834
|
||||
#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000
|
||||
#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24
|
||||
#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000
|
||||
#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16
|
||||
#define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00
|
||||
#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8
|
||||
#define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF
|
||||
#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0
|
||||
|
||||
#define AR_PHY_SETTLING 0x9844
|
||||
#define AR_PHY_SETTLING_SWITCH 0x00003F80
|
||||
#define AR_PHY_SETTLING_SWITCH_S 7
|
||||
|
||||
#define AR_PHY_RXGAIN 0x9848
|
||||
#define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000
|
||||
#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12
|
||||
#define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000
|
||||
#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
|
||||
#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
|
||||
#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
|
||||
#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
|
||||
#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
|
||||
|
||||
#define AR_PHY_DESIRED_SZ 0x9850
|
||||
#define AR_PHY_DESIRED_SZ_ADC 0x000000FF
|
||||
#define AR_PHY_DESIRED_SZ_ADC_S 0
|
||||
#define AR_PHY_DESIRED_SZ_PGA 0x0000FF00
|
||||
#define AR_PHY_DESIRED_SZ_PGA_S 8
|
||||
#define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000
|
||||
#define AR_PHY_DESIRED_SZ_TOT_DES_S 20
|
||||
|
||||
#define AR_PHY_FIND_SIG 0x9858
|
||||
#define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000
|
||||
#define AR_PHY_FIND_SIG_FIRSTEP_S 12
|
||||
#define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
|
||||
#define AR_PHY_FIND_SIG_FIRPWR_S 18
|
||||
|
||||
#define AR_PHY_AGC_CTL1 0x985C
|
||||
#define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80
|
||||
#define AR_PHY_AGC_CTL1_COARSE_LOW_S 7
|
||||
#define AR_PHY_AGC_CTL1_COARSE_HIGH 0x003F8000
|
||||
#define AR_PHY_AGC_CTL1_COARSE_HIGH_S 15
|
||||
|
||||
#define AR_PHY_AGC_CONTROL 0x9860
|
||||
#define AR_PHY_AGC_CONTROL_CAL 0x00000001
|
||||
#define AR_PHY_AGC_CONTROL_NF 0x00000002
|
||||
#define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000
|
||||
#define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000
|
||||
#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000
|
||||
|
||||
#define AR_PHY_CCA 0x9864
|
||||
#define AR_PHY_MINCCA_PWR 0x0FF80000
|
||||
#define AR_PHY_MINCCA_PWR_S 19
|
||||
#define AR_PHY_CCA_THRESH62 0x0007F000
|
||||
#define AR_PHY_CCA_THRESH62_S 12
|
||||
#define AR9280_PHY_MINCCA_PWR 0x1FF00000
|
||||
#define AR9280_PHY_MINCCA_PWR_S 20
|
||||
#define AR9280_PHY_CCA_THRESH62 0x000FF000
|
||||
#define AR9280_PHY_CCA_THRESH62_S 12
|
||||
|
||||
#define AR_PHY_SFCORR_LOW 0x986C
|
||||
#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
|
||||
#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00
|
||||
#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
|
||||
#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000
|
||||
#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
|
||||
#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000
|
||||
#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
|
||||
|
||||
#define AR_PHY_SFCORR 0x9868
|
||||
#define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F
|
||||
#define AR_PHY_SFCORR_M2COUNT_THR_S 0
|
||||
#define AR_PHY_SFCORR_M1_THRESH 0x00FE0000
|
||||
#define AR_PHY_SFCORR_M1_THRESH_S 17
|
||||
#define AR_PHY_SFCORR_M2_THRESH 0x7F000000
|
||||
#define AR_PHY_SFCORR_M2_THRESH_S 24
|
||||
|
||||
#define AR_PHY_SLEEP_CTR_CONTROL 0x9870
|
||||
#define AR_PHY_SLEEP_CTR_LIMIT 0x9874
|
||||
#define AR_PHY_SYNTH_CONTROL 0x9874
|
||||
#define AR_PHY_SLEEP_SCAL 0x9878
|
||||
|
||||
#define AR_PHY_PLL_CTL 0x987c
|
||||
#define AR_PHY_PLL_CTL_40 0xaa
|
||||
#define AR_PHY_PLL_CTL_40_5413 0x04
|
||||
#define AR_PHY_PLL_CTL_44 0xab
|
||||
#define AR_PHY_PLL_CTL_44_2133 0xeb
|
||||
#define AR_PHY_PLL_CTL_40_2133 0xea
|
||||
|
||||
#define AR_PHY_RX_DELAY 0x9914
|
||||
#define AR_PHY_SEARCH_START_DELAY 0x9918
|
||||
#define AR_PHY_RX_DELAY_DELAY 0x00003FFF
|
||||
|
||||
#define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12))
|
||||
#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F
|
||||
#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0
|
||||
#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0
|
||||
#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5
|
||||
#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800
|
||||
#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000
|
||||
#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12
|
||||
#define AR_PHY_TIMING_CTRL4_DO_CAL 0x10000
|
||||
|
||||
#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000
|
||||
#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000
|
||||
#define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000
|
||||
#define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000
|
||||
|
||||
#define AR_PHY_TIMING5 0x9924
|
||||
#define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
|
||||
#define AR_PHY_TIMING5_CYCPWR_THR1_S 1
|
||||
|
||||
#define AR_PHY_POWER_TX_RATE1 0x9934
|
||||
#define AR_PHY_POWER_TX_RATE2 0x9938
|
||||
#define AR_PHY_POWER_TX_RATE_MAX 0x993c
|
||||
#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
|
||||
|
||||
#define AR_PHY_FRAME_CTL 0x9944
|
||||
#define AR_PHY_FRAME_CTL_TX_CLIP 0x00000038
|
||||
#define AR_PHY_FRAME_CTL_TX_CLIP_S 3
|
||||
|
||||
#define AR_PHY_TXPWRADJ 0x994C
|
||||
#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA 0x00000FC0
|
||||
#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6
|
||||
#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX 0x00FC0000
|
||||
#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18
|
||||
|
||||
#define AR_PHY_RADAR_EXT 0x9940
|
||||
#define AR_PHY_RADAR_EXT_ENA 0x00004000
|
||||
|
||||
#define AR_PHY_RADAR_0 0x9954
|
||||
#define AR_PHY_RADAR_0_ENA 0x00000001
|
||||
#define AR_PHY_RADAR_0_FFT_ENA 0x80000000
|
||||
#define AR_PHY_RADAR_0_INBAND 0x0000003e
|
||||
#define AR_PHY_RADAR_0_INBAND_S 1
|
||||
#define AR_PHY_RADAR_0_PRSSI 0x00000FC0
|
||||
#define AR_PHY_RADAR_0_PRSSI_S 6
|
||||
#define AR_PHY_RADAR_0_HEIGHT 0x0003F000
|
||||
#define AR_PHY_RADAR_0_HEIGHT_S 12
|
||||
#define AR_PHY_RADAR_0_RRSSI 0x00FC0000
|
||||
#define AR_PHY_RADAR_0_RRSSI_S 18
|
||||
#define AR_PHY_RADAR_0_FIRPWR 0x7F000000
|
||||
#define AR_PHY_RADAR_0_FIRPWR_S 24
|
||||
|
||||
#define AR_PHY_RADAR_1 0x9958
|
||||
#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000
|
||||
#define AR_PHY_RADAR_1_USE_FIR128 0x00400000
|
||||
#define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000
|
||||
#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
|
||||
#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000
|
||||
#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000
|
||||
#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
|
||||
#define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00
|
||||
#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
|
||||
#define AR_PHY_RADAR_1_MAXLEN 0x000000FF
|
||||
#define AR_PHY_RADAR_1_MAXLEN_S 0
|
||||
|
||||
#define AR_PHY_SWITCH_CHAIN_0 0x9960
|
||||
#define AR_PHY_SWITCH_COM 0x9964
|
||||
|
||||
#define AR_PHY_SIGMA_DELTA 0x996C
|
||||
#define AR_PHY_SIGMA_DELTA_ADC_SEL 0x00000003
|
||||
#define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0
|
||||
#define AR_PHY_SIGMA_DELTA_FILT2 0x000000F8
|
||||
#define AR_PHY_SIGMA_DELTA_FILT2_S 3
|
||||
#define AR_PHY_SIGMA_DELTA_FILT1 0x00001F00
|
||||
#define AR_PHY_SIGMA_DELTA_FILT1_S 8
|
||||
#define AR_PHY_SIGMA_DELTA_ADC_CLIP 0x01FFE000
|
||||
#define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13
|
||||
|
||||
#define AR_PHY_RESTART 0x9970
|
||||
#define AR_PHY_RESTART_DIV_GC 0x001C0000
|
||||
#define AR_PHY_RESTART_DIV_GC_S 18
|
||||
|
||||
#define AR_PHY_RFBUS_REQ 0x997C
|
||||
#define AR_PHY_RFBUS_REQ_EN 0x00000001
|
||||
|
||||
#define AR_PHY_TIMING7 0x9980
|
||||
#define AR_PHY_TIMING8 0x9984
|
||||
#define AR_PHY_TIMING8_PILOT_MASK_2 0x000FFFFF
|
||||
#define AR_PHY_TIMING8_PILOT_MASK_2_S 0
|
||||
|
||||
#define AR_PHY_BIN_MASK2_1 0x9988
|
||||
#define AR_PHY_BIN_MASK2_2 0x998c
|
||||
#define AR_PHY_BIN_MASK2_3 0x9990
|
||||
#define AR_PHY_BIN_MASK2_4 0x9994
|
||||
|
||||
#define AR_PHY_BIN_MASK_1 0x9900
|
||||
#define AR_PHY_BIN_MASK_2 0x9904
|
||||
#define AR_PHY_BIN_MASK_3 0x9908
|
||||
|
||||
#define AR_PHY_MASK_CTL 0x990c
|
||||
|
||||
#define AR_PHY_BIN_MASK2_4_MASK_4 0x00003FFF
|
||||
#define AR_PHY_BIN_MASK2_4_MASK_4_S 0
|
||||
|
||||
#define AR_PHY_TIMING9 0x9998
|
||||
#define AR_PHY_TIMING10 0x999c
|
||||
#define AR_PHY_TIMING10_PILOT_MASK_2 0x000FFFFF
|
||||
#define AR_PHY_TIMING10_PILOT_MASK_2_S 0
|
||||
|
||||
#define AR_PHY_TIMING11 0x99a0
|
||||
#define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
|
||||
#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
|
||||
#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
|
||||
#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
|
||||
#define AR_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000
|
||||
#define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000
|
||||
|
||||
#define AR_PHY_RX_CHAINMASK 0x99a4
|
||||
#define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12))
|
||||
#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
|
||||
#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
|
||||
#define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac
|
||||
|
||||
#define AR_PHY_EXT_CCA0 0x99b8
|
||||
#define AR_PHY_EXT_CCA0_THRESH62 0x000000FF
|
||||
#define AR_PHY_EXT_CCA0_THRESH62_S 0
|
||||
|
||||
#define AR_PHY_EXT_CCA 0x99bc
|
||||
#define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00
|
||||
#define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9
|
||||
#define AR_PHY_EXT_CCA_THRESH62 0x007F0000
|
||||
#define AR_PHY_EXT_CCA_THRESH62_S 16
|
||||
#define AR_PHY_EXT_MINCCA_PWR 0xFF800000
|
||||
#define AR_PHY_EXT_MINCCA_PWR_S 23
|
||||
#define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000
|
||||
#define AR9280_PHY_EXT_MINCCA_PWR_S 16
|
||||
|
||||
#define AR_PHY_SFCORR_EXT 0x99c0
|
||||
#define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F
|
||||
#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
|
||||
#define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80
|
||||
#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7
|
||||
#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000
|
||||
#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
|
||||
#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000
|
||||
#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
|
||||
#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
|
||||
|
||||
#define AR_PHY_HALFGI 0x99D0
|
||||
#define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0
|
||||
#define AR_PHY_HALFGI_DSC_MAN_S 4
|
||||
#define AR_PHY_HALFGI_DSC_EXP 0x0000000F
|
||||
#define AR_PHY_HALFGI_DSC_EXP_S 0
|
||||
|
||||
#define AR_PHY_CHAN_INFO_MEMORY 0x99DC
|
||||
#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001
|
||||
|
||||
#define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0
|
||||
|
||||
#define AR_PHY_M_SLEEP 0x99f0
|
||||
#define AR_PHY_REFCLKDLY 0x99f4
|
||||
#define AR_PHY_REFCLKPD 0x99f8
|
||||
|
||||
#define AR_PHY_CALMODE 0x99f0
|
||||
|
||||
#define AR_PHY_CALMODE_IQ 0x00000000
|
||||
#define AR_PHY_CALMODE_ADC_GAIN 0x00000001
|
||||
#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
|
||||
#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
|
||||
|
||||
#define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12))
|
||||
#define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12))
|
||||
#define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12))
|
||||
#define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12))
|
||||
|
||||
#define AR_PHY_CURRENT_RSSI 0x9c1c
|
||||
#define AR9280_PHY_CURRENT_RSSI 0x9c3c
|
||||
|
||||
#define AR_PHY_RFBUS_GRANT 0x9C20
|
||||
#define AR_PHY_RFBUS_GRANT_EN 0x00000001
|
||||
|
||||
#define AR_PHY_CHAN_INFO_GAIN_DIFF 0x9CF4
|
||||
#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
|
||||
|
||||
#define AR_PHY_CHAN_INFO_GAIN 0x9CFC
|
||||
|
||||
#define AR_PHY_MODE 0xA200
|
||||
#define AR_PHY_MODE_AR2133 0x08
|
||||
#define AR_PHY_MODE_AR5111 0x00
|
||||
#define AR_PHY_MODE_AR5112 0x08
|
||||
#define AR_PHY_MODE_DYNAMIC 0x04
|
||||
#define AR_PHY_MODE_RF2GHZ 0x02
|
||||
#define AR_PHY_MODE_RF5GHZ 0x00
|
||||
#define AR_PHY_MODE_CCK 0x01
|
||||
#define AR_PHY_MODE_OFDM 0x00
|
||||
#define AR_PHY_MODE_DYN_CCK_DISABLE 0x100
|
||||
|
||||
#define AR_PHY_CCK_TX_CTRL 0xA204
|
||||
#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
|
||||
|
||||
#define AR_PHY_CCK_DETECT 0xA208
|
||||
#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
|
||||
#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
|
||||
/* [12:6] settling time for antenna switch */
|
||||
#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0
|
||||
#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
|
||||
#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
|
||||
|
||||
#define AR_PHY_GAIN_2GHZ 0xA20C
|
||||
#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00FC0000
|
||||
#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18
|
||||
#define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00
|
||||
#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10
|
||||
#define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F
|
||||
#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0
|
||||
|
||||
#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003E0000
|
||||
#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17
|
||||
#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001F000
|
||||
#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12
|
||||
#define AR_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000FC0
|
||||
#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6
|
||||
#define AR_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003F
|
||||
#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0
|
||||
|
||||
#define AR_PHY_CCK_RXCTRL4 0xA21C
|
||||
#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01F80000
|
||||
#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19
|
||||
|
||||
#define AR_PHY_DAG_CTRLCCK 0xA228
|
||||
#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
|
||||
#define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00
|
||||
#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10
|
||||
|
||||
#define AR_PHY_FORCE_CLKEN_CCK 0xA22C
|
||||
#define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040
|
||||
|
||||
#define AR_PHY_POWER_TX_RATE3 0xA234
|
||||
#define AR_PHY_POWER_TX_RATE4 0xA238
|
||||
|
||||
#define AR_PHY_SCRM_SEQ_XR 0xA23C
|
||||
#define AR_PHY_HEADER_DETECT_XR 0xA240
|
||||
#define AR_PHY_CHIRP_DETECTED_XR 0xA244
|
||||
#define AR_PHY_BLUETOOTH 0xA254
|
||||
|
||||
#define AR_PHY_TPCRG1 0xA258
|
||||
#define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
|
||||
#define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
|
||||
|
||||
#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
|
||||
#define AR_PHY_TPCRG1_PD_GAIN_1_S 16
|
||||
#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
|
||||
#define AR_PHY_TPCRG1_PD_GAIN_2_S 18
|
||||
#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
|
||||
#define AR_PHY_TPCRG1_PD_GAIN_3_S 20
|
||||
|
||||
#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0
|
||||
#define AR_PHY_MASK2_M_31_45 0xa3a4
|
||||
#define AR_PHY_MASK2_M_16_30 0xa3a8
|
||||
#define AR_PHY_MASK2_M_00_15 0xa3ac
|
||||
#define AR_PHY_MASK2_P_15_01 0xa3b8
|
||||
#define AR_PHY_MASK2_P_30_16 0xa3bc
|
||||
#define AR_PHY_MASK2_P_45_31 0xa3c0
|
||||
#define AR_PHY_MASK2_P_61_45 0xa3c4
|
||||
#define AR_PHY_SPUR_REG 0x994c
|
||||
|
||||
#define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18)
|
||||
#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18
|
||||
|
||||
#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000
|
||||
#define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9)
|
||||
#define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9
|
||||
#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100
|
||||
#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F
|
||||
#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
|
||||
|
||||
#define AR_PHY_PILOT_MASK_01_30 0xa3b0
|
||||
#define AR_PHY_PILOT_MASK_31_60 0xa3b4
|
||||
|
||||
#define AR_PHY_CHANNEL_MASK_01_30 0x99d4
|
||||
#define AR_PHY_CHANNEL_MASK_31_60 0x99d8
|
||||
|
||||
#define AR_PHY_ANALOG_SWAP 0xa268
|
||||
#define AR_PHY_SWAP_ALT_CHAIN 0x00000040
|
||||
|
||||
#define AR_PHY_TPCRG5 0xA26C
|
||||
#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F
|
||||
#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
|
||||
#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0
|
||||
#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4
|
||||
#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00
|
||||
#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10
|
||||
#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000
|
||||
#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16
|
||||
#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000
|
||||
#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22
|
||||
|
||||
#define AR_PHY_POWER_TX_RATE5 0xA38C
|
||||
#define AR_PHY_POWER_TX_RATE6 0xA390
|
||||
|
||||
#define AR_PHY_CAL_CHAINMASK 0xA39C
|
||||
|
||||
#define AR_PHY_POWER_TX_SUB 0xA3C8
|
||||
#define AR_PHY_POWER_TX_RATE7 0xA3CC
|
||||
#define AR_PHY_POWER_TX_RATE8 0xA3D0
|
||||
#define AR_PHY_POWER_TX_RATE9 0xA3D4
|
||||
|
||||
#define AR_PHY_XPA_CFG 0xA3D8
|
||||
#define AR_PHY_FORCE_XPA_CFG 0x000000001
|
||||
#define AR_PHY_FORCE_XPA_CFG_S 0
|
||||
|
||||
#define AR_PHY_CH1_CCA 0xa864
|
||||
#define AR_PHY_CH1_MINCCA_PWR 0x0FF80000
|
||||
#define AR_PHY_CH1_MINCCA_PWR_S 19
|
||||
#define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000
|
||||
#define AR9280_PHY_CH1_MINCCA_PWR_S 20
|
||||
|
||||
#define AR_PHY_CH2_CCA 0xb864
|
||||
#define AR_PHY_CH2_MINCCA_PWR 0x0FF80000
|
||||
#define AR_PHY_CH2_MINCCA_PWR_S 19
|
||||
|
||||
#define AR_PHY_CH1_EXT_CCA 0xa9bc
|
||||
#define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000
|
||||
#define AR_PHY_CH1_EXT_MINCCA_PWR_S 23
|
||||
#define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
|
||||
#define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16
|
||||
|
||||
#define AR_PHY_CH2_EXT_CCA 0xb9bc
|
||||
#define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000
|
||||
#define AR_PHY_CH2_EXT_MINCCA_PWR_S 23
|
||||
|
||||
#define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) do { \
|
||||
int r; \
|
||||
for (r = 0; r < ((iniarray)->ia_rows); r++) { \
|
||||
REG_WRITE(ah, INI_RA((iniarray), r, 0), (regData)[r]); \
|
||||
HDPRINTF(ah, HAL_DBG_CHANNEL, \
|
||||
"RF 0x%x V 0x%x\n", \
|
||||
INI_RA((iniarray), r, 0), (regData)[r]); \
|
||||
DO_DELAY(regWr); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define ATH9K_KEY_XOR 0xaa
|
||||
|
||||
#define ATH9K_IS_MIC_ENABLED(ah) \
|
||||
(AH5416(ah)->ah_staId1Defaults & AR_STA_ID1_CRPT_MIC_ENABLE)
|
||||
|
||||
#define ANTSWAP_AB 0x0001
|
||||
#define REDUCE_CHAIN_0 0x00000050
|
||||
#define REDUCE_CHAIN_1 0x00000051
|
||||
|
||||
#define RF_BANK_SETUP(_bank, _iniarray, _col) do { \
|
||||
int i; \
|
||||
for (i = 0; i < (_iniarray)->ia_rows; i++) \
|
||||
(_bank)[i] = INI_RA((_iniarray), i, _col);; \
|
||||
} while (0)
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,316 @@
|
||||
/*
|
||||
* Copyright (c) 2004 Sam Leffler, Errno Consulting
|
||||
* Copyright (c) 2004 Video54 Technologies, Inc.
|
||||
* Copyright (c) 2008 Atheros Communications Inc.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef RC_H
|
||||
#define RC_H
|
||||
|
||||
#include "ath9k.h"
|
||||
/*
|
||||
* Interface definitions for transmit rate control modules for the
|
||||
* Atheros driver.
|
||||
*
|
||||
* A rate control module is responsible for choosing the transmit rate
|
||||
* for each data frame. Management+control frames are always sent at
|
||||
* a fixed rate.
|
||||
*
|
||||
* Only one module may be present at a time; the driver references
|
||||
* rate control interfaces by symbol name. If multiple modules are
|
||||
* to be supported we'll need to switch to a registration-based scheme
|
||||
* as is currently done, for example, for authentication modules.
|
||||
*
|
||||
* An instance of the rate control module is attached to each device
|
||||
* at attach time and detached when the device is destroyed. The module
|
||||
* may associate data with each device and each node (station). Both
|
||||
* sets of storage are opaque except for the size of the per-node storage
|
||||
* which must be provided when the module is attached.
|
||||
*
|
||||
* The rate control module is notified for each state transition and
|
||||
* station association/reassociation. Otherwise it is queried for a
|
||||
* rate for each outgoing frame and provided status from each transmitted
|
||||
* frame. Any ancillary processing is the responsibility of the module
|
||||
* (e.g. if periodic processing is required then the module should setup
|
||||
* it's own timer).
|
||||
*
|
||||
* In addition to the transmit rate for each frame the module must also
|
||||
* indicate the number of attempts to make at the specified rate. If this
|
||||
* number is != ATH_TXMAXTRY then an additional callback is made to setup
|
||||
* additional transmit state. The rate control code is assumed to write
|
||||
* this additional data directly to the transmit descriptor.
|
||||
*/
|
||||
|
||||
struct ath_softc;
|
||||
|
||||
#define TRUE 1
|
||||
#define FALSE 0
|
||||
|
||||
#define ATH_RATE_MAX 30
|
||||
#define MCS_SET_SIZE 128
|
||||
|
||||
enum ieee80211_fixed_rate_mode {
|
||||
IEEE80211_FIXED_RATE_NONE = 0,
|
||||
IEEE80211_FIXED_RATE_MCS = 1 /* HT rates */
|
||||
};
|
||||
|
||||
/*
|
||||
* Use the hal os glue code to get ms time
|
||||
*/
|
||||
#define IEEE80211_RATE_IDX_ENTRY(val, idx) (((val&(0xff<<(idx*8)))>>(idx*8)))
|
||||
|
||||
#define SHORT_PRE 1
|
||||
#define LONG_PRE 0
|
||||
|
||||
#define WLAN_PHY_HT_20_SS WLAN_RC_PHY_HT_20_SS
|
||||
#define WLAN_PHY_HT_20_DS WLAN_RC_PHY_HT_20_DS
|
||||
#define WLAN_PHY_HT_20_DS_HGI WLAN_RC_PHY_HT_20_DS_HGI
|
||||
#define WLAN_PHY_HT_40_SS WLAN_RC_PHY_HT_40_SS
|
||||
#define WLAN_PHY_HT_40_SS_HGI WLAN_RC_PHY_HT_40_SS_HGI
|
||||
#define WLAN_PHY_HT_40_DS WLAN_RC_PHY_HT_40_DS
|
||||
#define WLAN_PHY_HT_40_DS_HGI WLAN_RC_PHY_HT_40_DS_HGI
|
||||
|
||||
#define WLAN_PHY_OFDM PHY_OFDM
|
||||
#define WLAN_PHY_CCK PHY_CCK
|
||||
|
||||
#define TRUE_20 0x2
|
||||
#define TRUE_40 0x4
|
||||
#define TRUE_2040 (TRUE_20|TRUE_40)
|
||||
#define TRUE_ALL (TRUE_2040|TRUE)
|
||||
|
||||
enum {
|
||||
WLAN_RC_PHY_HT_20_SS = 4,
|
||||
WLAN_RC_PHY_HT_20_DS,
|
||||
WLAN_RC_PHY_HT_40_SS,
|
||||
WLAN_RC_PHY_HT_40_DS,
|
||||
WLAN_RC_PHY_HT_20_SS_HGI,
|
||||
WLAN_RC_PHY_HT_20_DS_HGI,
|
||||
WLAN_RC_PHY_HT_40_SS_HGI,
|
||||
WLAN_RC_PHY_HT_40_DS_HGI,
|
||||
WLAN_RC_PHY_MAX
|
||||
};
|
||||
|
||||
#define WLAN_RC_PHY_DS(_phy) ((_phy == WLAN_RC_PHY_HT_20_DS) \
|
||||
|| (_phy == WLAN_RC_PHY_HT_40_DS) \
|
||||
|| (_phy == WLAN_RC_PHY_HT_20_DS_HGI) \
|
||||
|| (_phy == WLAN_RC_PHY_HT_40_DS_HGI))
|
||||
#define WLAN_RC_PHY_40(_phy) ((_phy == WLAN_RC_PHY_HT_40_SS) \
|
||||
|| (_phy == WLAN_RC_PHY_HT_40_DS) \
|
||||
|| (_phy == WLAN_RC_PHY_HT_40_SS_HGI) \
|
||||
|| (_phy == WLAN_RC_PHY_HT_40_DS_HGI))
|
||||
#define WLAN_RC_PHY_SGI(_phy) ((_phy == WLAN_RC_PHY_HT_20_SS_HGI) \
|
||||
|| (_phy == WLAN_RC_PHY_HT_20_DS_HGI) \
|
||||
|| (_phy == WLAN_RC_PHY_HT_40_SS_HGI) \
|
||||
|| (_phy == WLAN_RC_PHY_HT_40_DS_HGI))
|
||||
|
||||
#define WLAN_RC_PHY_HT(_phy) (_phy >= WLAN_RC_PHY_HT_20_SS)
|
||||
|
||||
/* Returns the capflag mode */
|
||||
#define WLAN_RC_CAP_MODE(capflag) (((capflag & WLAN_RC_HT_FLAG)? \
|
||||
(capflag & WLAN_RC_40_FLAG)?TRUE_40:TRUE_20:\
|
||||
TRUE))
|
||||
|
||||
/* Return TRUE if flag supports HT20 && client supports HT20 or
|
||||
* return TRUE if flag supports HT40 && client supports HT40.
|
||||
* This is used becos some rates overlap between HT20/HT40.
|
||||
*/
|
||||
|
||||
#define WLAN_RC_PHY_HT_VALID(flag, capflag) (((flag & TRUE_20) && !(capflag \
|
||||
& WLAN_RC_40_FLAG)) || ((flag & TRUE_40) && \
|
||||
(capflag & WLAN_RC_40_FLAG)))
|
||||
|
||||
#define WLAN_RC_DS_FLAG (0x01)
|
||||
#define WLAN_RC_40_FLAG (0x02)
|
||||
#define WLAN_RC_SGI_FLAG (0x04)
|
||||
#define WLAN_RC_HT_FLAG (0x08)
|
||||
|
||||
/* Index into the rate table */
|
||||
#define INIT_RATE_MAX_20 23
|
||||
#define INIT_RATE_MAX_40 40
|
||||
|
||||
#define RATE_TABLE_SIZE 64
|
||||
|
||||
/* XXX: Convert to kdoc */
|
||||
struct ath_rate_table {
|
||||
int rate_cnt;
|
||||
struct {
|
||||
int valid; /* Valid for use in rate control */
|
||||
int valid_single_stream;/* Valid for use in rate control
|
||||
for single stream operation */
|
||||
u_int8_t phy; /* CCK/OFDM/TURBO/XR */
|
||||
u_int32_t ratekbps; /* Rate in Kbits per second */
|
||||
u_int32_t user_ratekbps; /* User rate in KBits per second */
|
||||
u_int8_t ratecode; /* rate that goes into
|
||||
hw descriptors */
|
||||
u_int8_t short_preamble; /* Mask for enabling short preamble
|
||||
in rate code for CCK */
|
||||
u_int8_t dot11rate; /* Value that goes into supported
|
||||
rates info element of MLME */
|
||||
u_int8_t ctrl_rate; /* Index of next lower basic rate,
|
||||
used for duration computation */
|
||||
int8_t rssi_ack_validmin; /* Rate control related */
|
||||
int8_t rssi_ack_deltamin; /* Rate control related */
|
||||
u_int8_t base_index; /* base rate index */
|
||||
u_int8_t cw40index; /* 40cap rate index */
|
||||
u_int8_t sgi_index; /* shortgi rate index */
|
||||
u_int8_t ht_index; /* shortgi rate index */
|
||||
u_int32_t max_4ms_framelen; /* Maximum frame length(bytes)
|
||||
for 4ms tx duration */
|
||||
} info[RATE_TABLE_SIZE];
|
||||
u_int32_t probe_interval; /* interval for ratectrl to
|
||||
probe for other rates */
|
||||
u_int32_t rssi_reduce_interval; /* interval for ratectrl
|
||||
to reduce RSSI */
|
||||
u_int8_t initial_ratemax; /* the initial ratemax value used
|
||||
in ath_rc_sib_update() */
|
||||
};
|
||||
|
||||
#define ATH_RC_PROBE_ALLOWED 0x00000001
|
||||
#define ATH_RC_MINRATE_LASTRATE 0x00000002
|
||||
#define ATH_RC_SHORT_PREAMBLE 0x00000004
|
||||
|
||||
struct ath_rc_series {
|
||||
u_int8_t rix;
|
||||
u_int8_t tries;
|
||||
u_int8_t flags;
|
||||
u_int32_t max_4ms_framelen;
|
||||
};
|
||||
|
||||
/* rcs_flags definition */
|
||||
#define ATH_RC_DS_FLAG 0x01
|
||||
#define ATH_RC_CW40_FLAG 0x02 /* CW 40 */
|
||||
#define ATH_RC_SGI_FLAG 0x04 /* Short Guard Interval */
|
||||
#define ATH_RC_HT_FLAG 0x08 /* HT */
|
||||
#define ATH_RC_RTSCTS_FLAG 0x10 /* RTS-CTS */
|
||||
|
||||
/*
|
||||
* State structures for new rate adaptation code
|
||||
*/
|
||||
#define MAX_TX_RATE_TBL 64
|
||||
#define MAX_TX_RATE_PHY 48
|
||||
|
||||
struct ath_tx_ratectrl_state {
|
||||
int8_t rssi_thres; /* required rssi for this rate (dB) */
|
||||
u_int8_t per; /* recent estimate of packet error rate (%) */
|
||||
};
|
||||
|
||||
struct ath_tx_ratectrl {
|
||||
struct ath_tx_ratectrl_state state[MAX_TX_RATE_TBL]; /* state */
|
||||
int8_t rssi_last; /* last ack rssi */
|
||||
int8_t rssi_last_lookup; /* last ack rssi used for lookup */
|
||||
int8_t rssi_last_prev; /* previous last ack rssi */
|
||||
int8_t rssi_last_prev2; /* 2nd previous last ack rssi */
|
||||
int32_t rssi_sum_cnt; /* count of rssi_sum for averaging */
|
||||
int32_t rssi_sum_rate; /* rate that we are averaging */
|
||||
int32_t rssi_sum; /* running sum of rssi for averaging */
|
||||
u_int32_t valid_txrate_mask; /* mask of valid rates */
|
||||
u_int8_t rate_table_size; /* rate table size */
|
||||
u_int8_t rate_max; /* max rate that has recently worked */
|
||||
u_int8_t probe_rate; /* rate we are probing at */
|
||||
u_int32_t rssi_time; /* msec timestamp for last ack rssi */
|
||||
u_int32_t rssi_down_time; /* msec timestamp for last down step */
|
||||
u_int32_t probe_time; /* msec timestamp for last probe */
|
||||
u_int8_t hw_maxretry_pktcnt; /* num packets since we got
|
||||
HW max retry error */
|
||||
u_int8_t max_valid_rate; /* maximum number of valid rate */
|
||||
u_int8_t valid_rate_index[MAX_TX_RATE_TBL]; /* valid rate index */
|
||||
u_int32_t per_down_time; /* msec timstamp for last
|
||||
PER down step */
|
||||
|
||||
/* 11n state */
|
||||
u_int8_t valid_phy_ratecnt[WLAN_RC_PHY_MAX]; /* valid rate count */
|
||||
u_int8_t valid_phy_rateidx[WLAN_RC_PHY_MAX][MAX_TX_RATE_TBL];
|
||||
u_int8_t rc_phy_mode;
|
||||
u_int8_t rate_max_phy; /* Phy index for the max rate */
|
||||
u_int32_t rate_max_lastused; /* msec timstamp of when we
|
||||
last used rateMaxPhy */
|
||||
u_int32_t probe_interval; /* interval for ratectrl to probe
|
||||
for other rates */
|
||||
};
|
||||
|
||||
struct ath_rateset {
|
||||
u_int8_t rs_nrates;
|
||||
u_int8_t rs_rates[ATH_RATE_MAX];
|
||||
};
|
||||
|
||||
/* per-device state */
|
||||
struct ath_rate_softc {
|
||||
/* phy tables that contain rate control data */
|
||||
const void *hw_rate_table[WIRELESS_MODE_MAX];
|
||||
int fixedrix; /* -1 or index of fixed rate */
|
||||
};
|
||||
|
||||
/* per-node state */
|
||||
struct ath_rate_node {
|
||||
struct ath_tx_ratectrl tx_ratectrl; /* rate control state proper */
|
||||
u_int32_t prev_data_rix; /* rate idx of last data frame */
|
||||
|
||||
/* map of rate ix -> negotiated rate set ix */
|
||||
u_int8_t rixmap[MAX_TX_RATE_TBL];
|
||||
|
||||
/* map of ht rate ix -> negotiated rate set ix */
|
||||
u_int8_t ht_rixmap[MAX_TX_RATE_TBL];
|
||||
|
||||
u_int8_t ht_cap; /* ht capabilities */
|
||||
u_int8_t ant_tx; /* current transmit antenna */
|
||||
|
||||
u_int8_t single_stream; /* When TRUE, only single
|
||||
stream Tx possible */
|
||||
struct ath_rateset neg_rates; /* Negotiated rates */
|
||||
struct ath_rateset neg_ht_rates; /* Negotiated HT rates */
|
||||
struct ath_rate_softc *asc; /* back pointer to atheros softc */
|
||||
struct ath_vap *avp; /* back pointer to vap */
|
||||
};
|
||||
|
||||
/* Driver data of ieee80211_tx_info */
|
||||
struct ath_tx_info_priv {
|
||||
struct ath_rc_series rcs[4];
|
||||
struct ath_tx_status tx;
|
||||
int n_frames;
|
||||
int n_bad_frames;
|
||||
u_int8_t min_rate;
|
||||
};
|
||||
|
||||
/*
|
||||
* Attach/detach a rate control module.
|
||||
*/
|
||||
struct ath_rate_softc *ath_rate_attach(struct ath_hal *ah);
|
||||
void ath_rate_detach(struct ath_rate_softc *asc);
|
||||
|
||||
/*
|
||||
* Update/reset rate control state for 802.11 state transitions.
|
||||
* Important mostly as the analog to ath_rate_newassoc when operating
|
||||
* in station mode.
|
||||
*/
|
||||
void ath_rate_newstate(struct ath_softc *sc, struct ath_vap *avp, int up);
|
||||
|
||||
/*
|
||||
* Return the tx rate series.
|
||||
*/
|
||||
void ath_rate_findrate(struct ath_softc *sc, struct ath_rate_node *ath_rc_priv,
|
||||
int num_tries, int num_rates,
|
||||
unsigned int rcflag, struct ath_rc_series[],
|
||||
int *is_probe, int isretry);
|
||||
/*
|
||||
* Return rate index for given Dot11 Rate.
|
||||
*/
|
||||
u_int8_t ath_rate_findrateix(struct ath_softc *sc,
|
||||
u_int8_t dot11_rate);
|
||||
|
||||
/* Routines to register/unregister rate control algorithm */
|
||||
int ath_rate_control_register(void);
|
||||
void ath_rate_control_unregister(void);
|
||||
|
||||
#endif /* RC_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,415 @@
|
||||
/*
|
||||
* Copyright (c) 2008 Atheros Communications Inc.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef REGD_H
|
||||
#define REGD_H
|
||||
|
||||
#include "ath9k.h"
|
||||
|
||||
#define ATH9K_MODE_11A_TURBO ATH9K_MODE_SEL_108A
|
||||
#define ATH9K_MODE_11G_TURBO ATH9K_MODE_SEL_108G
|
||||
|
||||
#define BMLEN 2
|
||||
#define BMZERO {(u_int64_t) 0, (u_int64_t) 0}
|
||||
|
||||
#define BM(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh, _fi, _fj, _fk, _fl) \
|
||||
{((((_fa >= 0) && (_fa < 64)) ? \
|
||||
(((u_int64_t) 1) << _fa) : (u_int64_t) 0) | \
|
||||
(((_fb >= 0) && (_fb < 64)) ? \
|
||||
(((u_int64_t) 1) << _fb) : (u_int64_t) 0) | \
|
||||
(((_fc >= 0) && (_fc < 64)) ? \
|
||||
(((u_int64_t) 1) << _fc) : (u_int64_t) 0) | \
|
||||
(((_fd >= 0) && (_fd < 64)) ? \
|
||||
(((u_int64_t) 1) << _fd) : (u_int64_t) 0) | \
|
||||
(((_fe >= 0) && (_fe < 64)) ? \
|
||||
(((u_int64_t) 1) << _fe) : (u_int64_t) 0) | \
|
||||
(((_ff >= 0) && (_ff < 64)) ? \
|
||||
(((u_int64_t) 1) << _ff) : (u_int64_t) 0) | \
|
||||
(((_fg >= 0) && (_fg < 64)) ? \
|
||||
(((u_int64_t) 1) << _fg) : (u_int64_t) 0) | \
|
||||
(((_fh >= 0) && (_fh < 64)) ? \
|
||||
(((u_int64_t) 1) << _fh) : (u_int64_t) 0) | \
|
||||
(((_fi >= 0) && (_fi < 64)) ? \
|
||||
(((u_int64_t) 1) << _fi) : (u_int64_t) 0) | \
|
||||
(((_fj >= 0) && (_fj < 64)) ? \
|
||||
(((u_int64_t) 1) << _fj) : (u_int64_t) 0) | \
|
||||
(((_fk >= 0) && (_fk < 64)) ? \
|
||||
(((u_int64_t) 1) << _fk) : (u_int64_t) 0) | \
|
||||
(((_fl >= 0) && (_fl < 64)) ? \
|
||||
(((u_int64_t) 1) << _fl) : (u_int64_t) 0) | \
|
||||
((((_fa > 63) && (_fa < 128)) ? \
|
||||
(((u_int64_t) 1) << (_fa - 64)) : (u_int64_t) 0) | \
|
||||
(((_fb > 63) && (_fb < 128)) ? \
|
||||
(((u_int64_t) 1) << (_fb - 64)) : (u_int64_t) 0) | \
|
||||
(((_fc > 63) && (_fc < 128)) ? \
|
||||
(((u_int64_t) 1) << (_fc - 64)) : (u_int64_t) 0) | \
|
||||
(((_fd > 63) && (_fd < 128)) ? \
|
||||
(((u_int64_t) 1) << (_fd - 64)) : (u_int64_t) 0) | \
|
||||
(((_fe > 63) && (_fe < 128)) ? \
|
||||
(((u_int64_t) 1) << (_fe - 64)) : (u_int64_t) 0) | \
|
||||
(((_ff > 63) && (_ff < 128)) ? \
|
||||
(((u_int64_t) 1) << (_ff - 64)) : (u_int64_t) 0) | \
|
||||
(((_fg > 63) && (_fg < 128)) ? \
|
||||
(((u_int64_t) 1) << (_fg - 64)) : (u_int64_t) 0) | \
|
||||
(((_fh > 63) && (_fh < 128)) ? \
|
||||
(((u_int64_t) 1) << (_fh - 64)) : (u_int64_t) 0) | \
|
||||
(((_fi > 63) && (_fi < 128)) ? \
|
||||
(((u_int64_t) 1) << (_fi - 64)) : (u_int64_t) 0) | \
|
||||
(((_fj > 63) && (_fj < 128)) ? \
|
||||
(((u_int64_t) 1) << (_fj - 64)) : (u_int64_t) 0) | \
|
||||
(((_fk > 63) && (_fk < 128)) ? \
|
||||
(((u_int64_t) 1) << (_fk - 64)) : (u_int64_t) 0) | \
|
||||
(((_fl > 63) && (_fl < 128)) ? \
|
||||
(((u_int64_t) 1) << (_fl - 64)) : (u_int64_t) 0)))}
|
||||
|
||||
#define DEF_REGDMN FCC1_FCCA
|
||||
#define DEF_DMN_5 FCC1
|
||||
#define DEF_DMN_2 FCCA
|
||||
#define COUNTRY_ERD_FLAG 0x8000
|
||||
#define WORLDWIDE_ROAMING_FLAG 0x4000
|
||||
#define SUPER_DOMAIN_MASK 0x0fff
|
||||
#define COUNTRY_CODE_MASK 0x3fff
|
||||
#define CF_INTERFERENCE (CHANNEL_CW_INT | CHANNEL_RADAR_INT)
|
||||
#define CHANNEL_14 (2484)
|
||||
#define IS_11G_CH14(_ch,_cf) \
|
||||
(((_ch) == CHANNEL_14) && ((_cf) == CHANNEL_G))
|
||||
|
||||
#define NO_PSCAN 0x0ULL
|
||||
#define PSCAN_FCC 0x0000000000000001ULL
|
||||
#define PSCAN_FCC_T 0x0000000000000002ULL
|
||||
#define PSCAN_ETSI 0x0000000000000004ULL
|
||||
#define PSCAN_MKK1 0x0000000000000008ULL
|
||||
#define PSCAN_MKK2 0x0000000000000010ULL
|
||||
#define PSCAN_MKKA 0x0000000000000020ULL
|
||||
#define PSCAN_MKKA_G 0x0000000000000040ULL
|
||||
#define PSCAN_ETSIA 0x0000000000000080ULL
|
||||
#define PSCAN_ETSIB 0x0000000000000100ULL
|
||||
#define PSCAN_ETSIC 0x0000000000000200ULL
|
||||
#define PSCAN_WWR 0x0000000000000400ULL
|
||||
#define PSCAN_MKKA1 0x0000000000000800ULL
|
||||
#define PSCAN_MKKA1_G 0x0000000000001000ULL
|
||||
#define PSCAN_MKKA2 0x0000000000002000ULL
|
||||
#define PSCAN_MKKA2_G 0x0000000000004000ULL
|
||||
#define PSCAN_MKK3 0x0000000000008000ULL
|
||||
#define PSCAN_DEFER 0x7FFFFFFFFFFFFFFFULL
|
||||
#define IS_ECM_CHAN 0x8000000000000000ULL
|
||||
|
||||
#define isWwrSKU(_ah) \
|
||||
(((ath9k_regd_get_eepromRD((_ah)) & WORLD_SKU_MASK) == \
|
||||
WORLD_SKU_PREFIX) || \
|
||||
(ath9k_regd_get_eepromRD(_ah) == WORLD))
|
||||
|
||||
#define isWwrSKU_NoMidband(_ah) \
|
||||
((ath9k_regd_get_eepromRD((_ah)) == WOR3_WORLD) || \
|
||||
(ath9k_regd_get_eepromRD(_ah) == WOR4_WORLD) || \
|
||||
(ath9k_regd_get_eepromRD(_ah) == WOR5_ETSIC))
|
||||
|
||||
#define isUNII1OddChan(ch) \
|
||||
((ch == 5170) || (ch == 5190) || (ch == 5210) || (ch == 5230))
|
||||
|
||||
#define IS_HT40_MODE(_mode) \
|
||||
(((_mode == ATH9K_MODE_SEL_11NA_HT40PLUS || \
|
||||
_mode == ATH9K_MODE_SEL_11NG_HT40PLUS || \
|
||||
_mode == ATH9K_MODE_SEL_11NA_HT40MINUS || \
|
||||
_mode == ATH9K_MODE_SEL_11NG_HT40MINUS) ? AH_TRUE : AH_FALSE))
|
||||
|
||||
#define CHAN_FLAGS (CHANNEL_ALL|CHANNEL_HALF|CHANNEL_QUARTER)
|
||||
|
||||
#define swap(_a, _b, _size) { \
|
||||
u_int8_t *s = _b; \
|
||||
int i = _size; \
|
||||
do { \
|
||||
u_int8_t tmp = *_a; \
|
||||
*_a++ = *s; \
|
||||
*s++ = tmp; \
|
||||
} while (--i); \
|
||||
_a -= _size; \
|
||||
}
|
||||
|
||||
|
||||
#define HALF_MAXCHANBW 10
|
||||
|
||||
#define MULTI_DOMAIN_MASK 0xFF00
|
||||
|
||||
#define WORLD_SKU_MASK 0x00F0
|
||||
#define WORLD_SKU_PREFIX 0x0060
|
||||
|
||||
#define CHANNEL_HALF_BW 10
|
||||
#define CHANNEL_QUARTER_BW 5
|
||||
|
||||
typedef int ath_hal_cmp_t(const void *, const void *);
|
||||
|
||||
struct reg_dmn_pair_mapping {
|
||||
u_int16_t regDmnEnum;
|
||||
u_int16_t regDmn5GHz;
|
||||
u_int16_t regDmn2GHz;
|
||||
u_int32_t flags5GHz;
|
||||
u_int32_t flags2GHz;
|
||||
u_int64_t pscanMask;
|
||||
u_int16_t singleCC;
|
||||
};
|
||||
|
||||
struct ccmap {
|
||||
char isoName[3];
|
||||
u_int16_t countryCode;
|
||||
};
|
||||
|
||||
struct country_code_to_enum_rd {
|
||||
u_int16_t countryCode;
|
||||
u_int16_t regDmnEnum;
|
||||
const char *isoName;
|
||||
const char *name;
|
||||
enum hal_bool allow11g;
|
||||
enum hal_bool allow11aTurbo;
|
||||
enum hal_bool allow11gTurbo;
|
||||
enum hal_bool allow11ng20;
|
||||
enum hal_bool allow11ng40;
|
||||
enum hal_bool allow11na20;
|
||||
enum hal_bool allow11na40;
|
||||
u_int16_t outdoorChanStart;
|
||||
};
|
||||
|
||||
struct RegDmnFreqBand {
|
||||
u_int16_t lowChannel;
|
||||
u_int16_t highChannel;
|
||||
u_int8_t powerDfs;
|
||||
u_int8_t antennaMax;
|
||||
u_int8_t channelBW;
|
||||
u_int8_t channelSep;
|
||||
u_int64_t useDfs;
|
||||
u_int64_t usePassScan;
|
||||
u_int8_t regClassId;
|
||||
};
|
||||
|
||||
struct regDomain {
|
||||
u_int16_t regDmnEnum;
|
||||
u_int8_t conformanceTestLimit;
|
||||
u_int64_t dfsMask;
|
||||
u_int64_t pscan;
|
||||
u_int32_t flags;
|
||||
u_int64_t chan11a[BMLEN];
|
||||
u_int64_t chan11a_turbo[BMLEN];
|
||||
u_int64_t chan11a_dyn_turbo[BMLEN];
|
||||
u_int64_t chan11b[BMLEN];
|
||||
u_int64_t chan11g[BMLEN];
|
||||
u_int64_t chan11g_turbo[BMLEN];
|
||||
};
|
||||
|
||||
struct cmode {
|
||||
u_int32_t mode;
|
||||
u_int32_t flags;
|
||||
};
|
||||
|
||||
#define YES AH_TRUE
|
||||
#define NO AH_FALSE
|
||||
|
||||
struct japan_bandcheck {
|
||||
u_int16_t freqbandbit;
|
||||
u_int32_t eepromflagtocheck;
|
||||
};
|
||||
|
||||
struct common_mode_power {
|
||||
u_int16_t lchan;
|
||||
u_int16_t hchan;
|
||||
u_int8_t pwrlvl;
|
||||
};
|
||||
|
||||
enum CountryCode {
|
||||
CTRY_ALBANIA = 8,
|
||||
CTRY_ALGERIA = 12,
|
||||
CTRY_ARGENTINA = 32,
|
||||
CTRY_ARMENIA = 51,
|
||||
CTRY_AUSTRALIA = 36,
|
||||
CTRY_AUSTRIA = 40,
|
||||
CTRY_AZERBAIJAN = 31,
|
||||
CTRY_BAHRAIN = 48,
|
||||
CTRY_BELARUS = 112,
|
||||
CTRY_BELGIUM = 56,
|
||||
CTRY_BELIZE = 84,
|
||||
CTRY_BOLIVIA = 68,
|
||||
CTRY_BOSNIA_HERZ = 70,
|
||||
CTRY_BRAZIL = 76,
|
||||
CTRY_BRUNEI_DARUSSALAM = 96,
|
||||
CTRY_BULGARIA = 100,
|
||||
CTRY_CANADA = 124,
|
||||
CTRY_CHILE = 152,
|
||||
CTRY_CHINA = 156,
|
||||
CTRY_COLOMBIA = 170,
|
||||
CTRY_COSTA_RICA = 188,
|
||||
CTRY_CROATIA = 191,
|
||||
CTRY_CYPRUS = 196,
|
||||
CTRY_CZECH = 203,
|
||||
CTRY_DENMARK = 208,
|
||||
CTRY_DOMINICAN_REPUBLIC = 214,
|
||||
CTRY_ECUADOR = 218,
|
||||
CTRY_EGYPT = 818,
|
||||
CTRY_EL_SALVADOR = 222,
|
||||
CTRY_ESTONIA = 233,
|
||||
CTRY_FAEROE_ISLANDS = 234,
|
||||
CTRY_FINLAND = 246,
|
||||
CTRY_FRANCE = 250,
|
||||
CTRY_GEORGIA = 268,
|
||||
CTRY_GERMANY = 276,
|
||||
CTRY_GREECE = 300,
|
||||
CTRY_GUATEMALA = 320,
|
||||
CTRY_HONDURAS = 340,
|
||||
CTRY_HONG_KONG = 344,
|
||||
CTRY_HUNGARY = 348,
|
||||
CTRY_ICELAND = 352,
|
||||
CTRY_INDIA = 356,
|
||||
CTRY_INDONESIA = 360,
|
||||
CTRY_IRAN = 364,
|
||||
CTRY_IRAQ = 368,
|
||||
CTRY_IRELAND = 372,
|
||||
CTRY_ISRAEL = 376,
|
||||
CTRY_ITALY = 380,
|
||||
CTRY_JAMAICA = 388,
|
||||
CTRY_JAPAN = 392,
|
||||
CTRY_JORDAN = 400,
|
||||
CTRY_KAZAKHSTAN = 398,
|
||||
CTRY_KENYA = 404,
|
||||
CTRY_KOREA_NORTH = 408,
|
||||
CTRY_KOREA_ROC = 410,
|
||||
CTRY_KOREA_ROC2 = 411,
|
||||
CTRY_KOREA_ROC3 = 412,
|
||||
CTRY_KUWAIT = 414,
|
||||
CTRY_LATVIA = 428,
|
||||
CTRY_LEBANON = 422,
|
||||
CTRY_LIBYA = 434,
|
||||
CTRY_LIECHTENSTEIN = 438,
|
||||
CTRY_LITHUANIA = 440,
|
||||
CTRY_LUXEMBOURG = 442,
|
||||
CTRY_MACAU = 446,
|
||||
CTRY_MACEDONIA = 807,
|
||||
CTRY_MALAYSIA = 458,
|
||||
CTRY_MALTA = 470,
|
||||
CTRY_MEXICO = 484,
|
||||
CTRY_MONACO = 492,
|
||||
CTRY_MOROCCO = 504,
|
||||
CTRY_NEPAL = 524,
|
||||
CTRY_NETHERLANDS = 528,
|
||||
CTRY_NETHERLANDS_ANTILLES = 530,
|
||||
CTRY_NEW_ZEALAND = 554,
|
||||
CTRY_NICARAGUA = 558,
|
||||
CTRY_NORWAY = 578,
|
||||
CTRY_OMAN = 512,
|
||||
CTRY_PAKISTAN = 586,
|
||||
CTRY_PANAMA = 591,
|
||||
CTRY_PAPUA_NEW_GUINEA = 598,
|
||||
CTRY_PARAGUAY = 600,
|
||||
CTRY_PERU = 604,
|
||||
CTRY_PHILIPPINES = 608,
|
||||
CTRY_POLAND = 616,
|
||||
CTRY_PORTUGAL = 620,
|
||||
CTRY_PUERTO_RICO = 630,
|
||||
CTRY_QATAR = 634,
|
||||
CTRY_ROMANIA = 642,
|
||||
CTRY_RUSSIA = 643,
|
||||
CTRY_SAUDI_ARABIA = 682,
|
||||
CTRY_SERBIA_MONTENEGRO = 891,
|
||||
CTRY_SINGAPORE = 702,
|
||||
CTRY_SLOVAKIA = 703,
|
||||
CTRY_SLOVENIA = 705,
|
||||
CTRY_SOUTH_AFRICA = 710,
|
||||
CTRY_SPAIN = 724,
|
||||
CTRY_SRI_LANKA = 144,
|
||||
CTRY_SWEDEN = 752,
|
||||
CTRY_SWITZERLAND = 756,
|
||||
CTRY_SYRIA = 760,
|
||||
CTRY_TAIWAN = 158,
|
||||
CTRY_THAILAND = 764,
|
||||
CTRY_TRINIDAD_Y_TOBAGO = 780,
|
||||
CTRY_TUNISIA = 788,
|
||||
CTRY_TURKEY = 792,
|
||||
CTRY_UAE = 784,
|
||||
CTRY_UKRAINE = 804,
|
||||
CTRY_UNITED_KINGDOM = 826,
|
||||
CTRY_UNITED_STATES = 840,
|
||||
CTRY_UNITED_STATES_FCC49 = 842,
|
||||
CTRY_URUGUAY = 858,
|
||||
CTRY_UZBEKISTAN = 860,
|
||||
CTRY_VENEZUELA = 862,
|
||||
CTRY_VIET_NAM = 704,
|
||||
CTRY_YEMEN = 887,
|
||||
CTRY_ZIMBABWE = 716,
|
||||
CTRY_JAPAN1 = 393,
|
||||
CTRY_JAPAN2 = 394,
|
||||
CTRY_JAPAN3 = 395,
|
||||
CTRY_JAPAN4 = 396,
|
||||
CTRY_JAPAN5 = 397,
|
||||
CTRY_JAPAN6 = 4006,
|
||||
CTRY_JAPAN7 = 4007,
|
||||
CTRY_JAPAN8 = 4008,
|
||||
CTRY_JAPAN9 = 4009,
|
||||
CTRY_JAPAN10 = 4010,
|
||||
CTRY_JAPAN11 = 4011,
|
||||
CTRY_JAPAN12 = 4012,
|
||||
CTRY_JAPAN13 = 4013,
|
||||
CTRY_JAPAN14 = 4014,
|
||||
CTRY_JAPAN15 = 4015,
|
||||
CTRY_JAPAN16 = 4016,
|
||||
CTRY_JAPAN17 = 4017,
|
||||
CTRY_JAPAN18 = 4018,
|
||||
CTRY_JAPAN19 = 4019,
|
||||
CTRY_JAPAN20 = 4020,
|
||||
CTRY_JAPAN21 = 4021,
|
||||
CTRY_JAPAN22 = 4022,
|
||||
CTRY_JAPAN23 = 4023,
|
||||
CTRY_JAPAN24 = 4024,
|
||||
CTRY_JAPAN25 = 4025,
|
||||
CTRY_JAPAN26 = 4026,
|
||||
CTRY_JAPAN27 = 4027,
|
||||
CTRY_JAPAN28 = 4028,
|
||||
CTRY_JAPAN29 = 4029,
|
||||
CTRY_JAPAN30 = 4030,
|
||||
CTRY_JAPAN31 = 4031,
|
||||
CTRY_JAPAN32 = 4032,
|
||||
CTRY_JAPAN33 = 4033,
|
||||
CTRY_JAPAN34 = 4034,
|
||||
CTRY_JAPAN35 = 4035,
|
||||
CTRY_JAPAN36 = 4036,
|
||||
CTRY_JAPAN37 = 4037,
|
||||
CTRY_JAPAN38 = 4038,
|
||||
CTRY_JAPAN39 = 4039,
|
||||
CTRY_JAPAN40 = 4040,
|
||||
CTRY_JAPAN41 = 4041,
|
||||
CTRY_JAPAN42 = 4042,
|
||||
CTRY_JAPAN43 = 4043,
|
||||
CTRY_JAPAN44 = 4044,
|
||||
CTRY_JAPAN45 = 4045,
|
||||
CTRY_JAPAN46 = 4046,
|
||||
CTRY_JAPAN47 = 4047,
|
||||
CTRY_JAPAN48 = 4048,
|
||||
CTRY_JAPAN49 = 4049,
|
||||
CTRY_JAPAN50 = 4050,
|
||||
CTRY_JAPAN51 = 4051,
|
||||
CTRY_JAPAN52 = 4052,
|
||||
CTRY_JAPAN53 = 4053,
|
||||
CTRY_JAPAN54 = 4054,
|
||||
CTRY_JAPAN55 = 4055,
|
||||
CTRY_JAPAN56 = 4056,
|
||||
CTRY_JAPAN57 = 4057,
|
||||
CTRY_JAPAN58 = 4058,
|
||||
CTRY_JAPAN59 = 4059,
|
||||
CTRY_AUSTRALIA2 = 5000,
|
||||
CTRY_CANADA2 = 5001,
|
||||
CTRY_BELGIUM2 = 5002
|
||||
};
|
||||
|
||||
void ath9k_regd_get_current_country(struct ath_hal *ah,
|
||||
struct hal_country_entry *ctry);
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue