ipq806x: add NAND flash controller support
These patches add support for ipq806x NAND flash controller. Most of these are cherry-picked & backported from LKML: *https://lkml.org/lkml/2015/8/3/16 This patch just modifies the kernel code, but doesn't change the config. It should be harmless. Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 46568v19.07.3_mercusys_ac12_duma
Felix Fietkau
9 years ago
parent
c7bf2accc9
commit
d523866eb3
@ -0,0 +1,74 @@
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From 4c385b25fab119144bffb255ad77712fe586ac10 Mon Sep 17 00:00:00 2001
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From: Archit Taneja <architt@codeaurora.org>
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Date: Thu, 2 Apr 2015 11:20:41 +0530
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Subject: [PATCH] clk: qcom: Add EBI2 clocks for IPQ806x
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The NAND controller within EBI2 requires EBI2_CLK and
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EBI2_ALWAYS_ON_CLK clocks. Create structs for these clocks so
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that they can be used by the NAND controller driver. Add an entry
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for EBI2_AON_CLK in the gcc-ipq806x DT binding document.
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Signed-off-by: Archit Taneja <architt@codeaurora.org>
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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---
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drivers/clk/qcom/gcc-ipq806x.c | 32 ++++++++++++++++++++++++++++
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include/dt-bindings/clock/qcom,gcc-ipq806x.h | 1 +
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2 files changed, 33 insertions(+)
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--- a/drivers/clk/qcom/gcc-ipq806x.c
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+++ b/drivers/clk/qcom/gcc-ipq806x.c
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@@ -2239,6 +2239,36 @@ static struct clk_branch usb_fs1_h_clk =
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},
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};
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+static struct clk_branch ebi2_clk = {
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+ .hwcg_reg = 0x3b00,
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+ .hwcg_bit = 6,
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+ .halt_reg = 0x2fcc,
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+ .halt_bit = 1,
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+ .clkr = {
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+ .enable_reg = 0x3b00,
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+ .enable_mask = BIT(4),
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+ .hw.init = &(struct clk_init_data){
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+ .name = "ebi2_clk",
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+ .ops = &clk_branch_ops,
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+ .flags = CLK_IS_ROOT,
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+ },
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+ },
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+};
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+
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+static struct clk_branch ebi2_aon_clk = {
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+ .halt_reg = 0x2fcc,
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+ .halt_bit = 0,
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+ .clkr = {
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+ .enable_reg = 0x3b00,
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+ .enable_mask = BIT(8),
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+ .hw.init = &(struct clk_init_data){
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+ .name = "ebi2_always_on_clk",
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+ .ops = &clk_branch_ops,
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+ .flags = CLK_IS_ROOT,
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+ },
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+ },
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+};
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+
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static struct clk_regmap *gcc_ipq806x_clks[] = {
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[PLL0] = &pll0.clkr,
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[PLL0_VOTE] = &pll0_vote,
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@@ -2341,6 +2371,8 @@ static struct clk_regmap *gcc_ipq806x_cl
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[USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr,
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[USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr,
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[USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr,
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+ [EBI2_CLK] = &ebi2_clk.clkr,
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+ [EBI2_AON_CLK] = &ebi2_aon_clk.clkr,
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[PLL9] = &hfpll0.clkr,
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[PLL10] = &hfpll1.clkr,
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[PLL12] = &hfpll_l2.clkr,
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--- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
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+++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
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@@ -289,5 +289,6 @@
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#define UBI32_CORE2_CLK_SRC 278
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#define UBI32_CORE1_CLK 279
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#define UBI32_CORE2_CLK 280
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+#define EBI2_AON_CLK 281
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#endif
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@ -0,0 +1,84 @@
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [v3,
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1/5] mtd: nand: Create a BBT flag to access bad block markers in raw
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mode
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From: Archit Taneja <architt@codeaurora.org>
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X-Patchwork-Id: 6927081
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Message-Id: <1438578498-32254-2-git-send-email-architt@codeaurora.org>
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To: linux-mtd@lists.infradead.org, dehrenberg@google.com,
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cernekee@gmail.com, computersforpeace@gmail.com
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Cc: linux-arm-msm@vger.kernel.org, agross@codeaurora.org,
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sboyd@codeaurora.org, linux-kernel@vger.kernel.org,
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Archit Taneja <architt@codeaurora.org>
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Date: Mon, 3 Aug 2015 10:38:14 +0530
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Some controllers can access the factory bad block marker from OOB only
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when they read it in raw mode. When ECC is enabled, these controllers
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discard reading/writing bad block markers, preventing access to them
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altogether.
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The bbt driver assumes MTD_OPS_PLACE_OOB when scanning for bad blocks.
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This results in the nand driver's ecc->read_oob() op to be called, which
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works with ECC enabled.
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Create a new BBT option flag that tells nand_bbt to force the mode to
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MTD_OPS_RAW. This would result in the correct op being called for the
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underlying nand controller driver.
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Reviewed-by: Andy Gross <agross@codeaurora.org>
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Signed-off-by: Archit Taneja <architt@codeaurora.org>
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---
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drivers/mtd/nand/nand_base.c | 6 +++++-
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drivers/mtd/nand/nand_bbt.c | 6 +++++-
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include/linux/mtd/bbm.h | 7 +++++++
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3 files changed, 17 insertions(+), 2 deletions(-)
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--- a/drivers/mtd/nand/nand_base.c
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+++ b/drivers/mtd/nand/nand_base.c
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@@ -396,7 +396,11 @@ static int nand_default_block_markbad(st
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} else {
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ops.len = ops.ooblen = 1;
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}
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- ops.mode = MTD_OPS_PLACE_OOB;
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+
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+ if (unlikely(chip->bbt_options & NAND_BBT_ACCESS_BBM_RAW))
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+ ops.mode = MTD_OPS_RAW;
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+ else
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+ ops.mode = MTD_OPS_PLACE_OOB;
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/* Write to first/last page(s) if necessary */
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if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
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--- a/drivers/mtd/nand/nand_bbt.c
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+++ b/drivers/mtd/nand/nand_bbt.c
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@@ -423,7 +423,11 @@ static int scan_block_fast(struct mtd_in
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ops.oobbuf = buf;
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ops.ooboffs = 0;
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ops.datbuf = NULL;
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- ops.mode = MTD_OPS_PLACE_OOB;
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+
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+ if (unlikely(bd->options & NAND_BBT_ACCESS_BBM_RAW))
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+ ops.mode = MTD_OPS_RAW;
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+ else
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+ ops.mode = MTD_OPS_PLACE_OOB;
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for (j = 0; j < numpages; j++) {
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/*
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--- a/include/linux/mtd/bbm.h
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+++ b/include/linux/mtd/bbm.h
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@@ -116,6 +116,13 @@ struct nand_bbt_descr {
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#define NAND_BBT_NO_OOB_BBM 0x00080000
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/*
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+ * Force MTD_OPS_RAW mode when trying to access bad block markes from OOB. To
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+ * be used by controllers which can access BBM only when ECC is disabled, i.e,
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+ * when in RAW access mode
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+ */
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+#define NAND_BBT_ACCESS_BBM_RAW 0x00100000
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+
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+/*
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* Flag set by nand_create_default_bbt_descr(), marking that the nand_bbt_descr
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* was allocated dynamicaly and must be freed in nand_release(). Has no meaning
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* in nand_chip.bbt_options.
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,82 @@
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [v3,3/5] dt/bindings: qcom_nandc: Add DT bindings
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From: Archit Taneja <architt@codeaurora.org>
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X-Patchwork-Id: 6927141
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Message-Id: <1438578498-32254-4-git-send-email-architt@codeaurora.org>
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To: linux-mtd@lists.infradead.org, dehrenberg@google.com,
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cernekee@gmail.com, computersforpeace@gmail.com
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Cc: linux-arm-msm@vger.kernel.org, agross@codeaurora.org,
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sboyd@codeaurora.org, linux-kernel@vger.kernel.org,
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Archit Taneja <architt@codeaurora.org>, devicetree@vger.kernel.org
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Date: Mon, 3 Aug 2015 10:38:16 +0530
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Add DT bindings document for the Qualcomm NAND controller driver.
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Cc: devicetree@vger.kernel.org
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v3:
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- Don't use '0x' when specifying nand controller address space
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- Add optional property for on-flash bbt usage
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Acked-by: Andy Gross <agross@codeaurora.org>
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Signed-off-by: Archit Taneja <architt@codeaurora.org>
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---
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.../devicetree/bindings/mtd/qcom_nandc.txt | 49 ++++++++++++++++++++++
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1 file changed, 49 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/mtd/qcom_nandc.txt
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
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@@ -0,0 +1,49 @@
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+* Qualcomm NAND controller
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+
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+Required properties:
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+- compatible: should be "qcom,ebi2-nand" for IPQ806x
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+- reg: MMIO address range
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+- clocks: must contain core clock and always on clock
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+- clock-names: must contain "core" for the core clock and "aon" for the
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+ always on clock
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+- dmas: DMA specifier, consisting of a phandle to the ADM DMA
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+ controller node and the channel number to be used for
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+ NAND. Refer to dma.txt and qcom_adm.txt for more details
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+- dma-names: must be "rxtx"
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+- qcom,cmd-crci: must contain the ADM command type CRCI block instance
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+ number specified for the NAND controller on the given
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+ platform
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+- qcom,data-crci: must contain the ADM data type CRCI block instance
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+ number specified for the NAND controller on the given
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+ platform
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+
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+Optional properties:
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+- nand-bus-width: bus width. Must be 8 or 16. If not present, 8 is chosen
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+ as default
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+
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+- nand-ecc-strength: number of bits to correct per ECC step. Must be 4 or 8
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+ bits. If not present, 4 is chosen as default
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+- nand-on-flash-bbt: Create/use on-flash bad block table
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+
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+The device tree may optionally contain sub-nodes describing partitions of the
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+address space. See partition.txt for more detail.
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+
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+Example:
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+
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+nand@1ac00000 {
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+ compatible = "qcom,ebi2-nandc";
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+ reg = <0x1ac00000 0x800>;
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+
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+ clocks = <&gcc EBI2_CLK>,
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+ <&gcc EBI2_AON_CLK>;
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+ clock-names = "core", "aon";
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+
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+ dmas = <&adm_dma 3>;
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+ dma-names = "rxtx";
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+ qcom,cmd-crci = <15>;
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+ qcom,data-crci = <3>;
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+
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+ partition@0 {
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+ ...
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+ };
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+};
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@ -0,0 +1,50 @@
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [v3,4/5] arm: qcom: dts: Add NAND controller node for ipq806x
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From: Archit Taneja <architt@codeaurora.org>
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X-Patchwork-Id: 6927121
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Message-Id: <1438578498-32254-5-git-send-email-architt@codeaurora.org>
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To: linux-mtd@lists.infradead.org, dehrenberg@google.com,
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cernekee@gmail.com, computersforpeace@gmail.com
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Cc: linux-arm-msm@vger.kernel.org, agross@codeaurora.org,
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sboyd@codeaurora.org, linux-kernel@vger.kernel.org,
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Archit Taneja <architt@codeaurora.org>, devicetree@vger.kernel.org
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Date: Mon, 3 Aug 2015 10:38:17 +0530
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The nand controller in IPQ806x is of the 'EBI2 type'. Use the corresponding
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compatible string.
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Cc: devicetree@vger.kernel.org
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Reviewed-by: Andy Gross <agross@codeaurora.org>
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Signed-off-by: Archit Taneja <architt@codeaurora.org>
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---
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arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +++++++++++++++
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1 file changed, 15 insertions(+)
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -677,5 +677,21 @@
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status = "disabled";
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};
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+ nand@1ac00000 {
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+ compatible = "qcom,ebi2-nandc";
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+ reg = <0x1ac00000 0x800>;
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+
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+ clocks = <&gcc EBI2_CLK>,
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+ <&gcc EBI2_AON_CLK>;
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+ clock-names = "core", "aon";
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+
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+ dmas = <&adm_dma 3>;
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+ dma-names = "rxtx";
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+ qcom,cmd-crci = <15>;
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+ qcom,data-crci = <3>;
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+
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+ status = "disabled";
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+ };
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+
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};
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};
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@ -0,0 +1,79 @@
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [v3,5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform
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From: Archit Taneja <architt@codeaurora.org>
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X-Patchwork-Id: 6927091
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Message-Id: <1438578498-32254-6-git-send-email-architt@codeaurora.org>
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To: linux-mtd@lists.infradead.org, dehrenberg@google.com,
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cernekee@gmail.com, computersforpeace@gmail.com
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Cc: linux-arm-msm@vger.kernel.org, agross@codeaurora.org,
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sboyd@codeaurora.org, linux-kernel@vger.kernel.org,
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Archit Taneja <architt@codeaurora.org>, devicetree@vger.kernel.org
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Date: Mon, 3 Aug 2015 10:38:18 +0530
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Enable the NAND controller node on the AP148 platform. Provide pinmux
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information.
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Cc: devicetree@vger.kernel.org
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Signed-off-by: Archit Taneja <architt@codeaurora.org>
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---
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arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 ++++++++++++++++++++++++++++++++
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1 file changed, 36 insertions(+)
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--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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@@ -61,6 +61,31 @@
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bias-none;
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};
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};
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+
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+ nand_pins: nand_pins {
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+ mux {
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+ pins = "gpio34", "gpio35", "gpio36",
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+ "gpio37", "gpio38", "gpio39",
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+ "gpio40", "gpio41", "gpio42",
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+ "gpio43", "gpio44", "gpio45",
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+ "gpio46", "gpio47";
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+ function = "nand";
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+ drive-strength = <10>;
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+ bias-disable;
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+ };
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+
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+ pullups {
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+ pins = "gpio39";
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+ bias-pull-up;
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+ };
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+
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+ hold {
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+ pins = "gpio40", "gpio41", "gpio42",
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+ "gpio43", "gpio44", "gpio45",
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+ "gpio46", "gpio47";
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+ bias-bus-hold;
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+ };
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+ };
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};
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gsbi@16300000 {
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@@ -174,5 +199,19 @@
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pinctrl-0 = <&pcie1_pins>;
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pinctrl-names = "default";
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};
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+
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+ nand@1ac00000 {
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+ status = "ok";
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+
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+ pinctrl-0 = <&nand_pins>;
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+ pinctrl-names = "default";
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+
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+ nand-ecc-strength = <4>;
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+ nand-bus-width = <8>;
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+ };
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};
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};
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+
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+&adm_dma {
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+ status = "ok";
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+};
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@ -0,0 +1,84 @@
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [v3,
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1/5] mtd: nand: Create a BBT flag to access bad block markers in raw
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mode
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From: Archit Taneja <architt@codeaurora.org>
|
||||
X-Patchwork-Id: 6927081
|
||||
Message-Id: <1438578498-32254-2-git-send-email-architt@codeaurora.org>
|
||||
To: linux-mtd@lists.infradead.org, dehrenberg@google.com,
|
||||
cernekee@gmail.com, computersforpeace@gmail.com
|
||||
Cc: linux-arm-msm@vger.kernel.org, agross@codeaurora.org,
|
||||
sboyd@codeaurora.org, linux-kernel@vger.kernel.org,
|
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Archit Taneja <architt@codeaurora.org>
|
||||
Date: Mon, 3 Aug 2015 10:38:14 +0530
|
||||
|
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Some controllers can access the factory bad block marker from OOB only
|
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when they read it in raw mode. When ECC is enabled, these controllers
|
||||
discard reading/writing bad block markers, preventing access to them
|
||||
altogether.
|
||||
|
||||
The bbt driver assumes MTD_OPS_PLACE_OOB when scanning for bad blocks.
|
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This results in the nand driver's ecc->read_oob() op to be called, which
|
||||
works with ECC enabled.
|
||||
|
||||
Create a new BBT option flag that tells nand_bbt to force the mode to
|
||||
MTD_OPS_RAW. This would result in the correct op being called for the
|
||||
underlying nand controller driver.
|
||||
|
||||
Reviewed-by: Andy Gross <agross@codeaurora.org>
|
||||
Signed-off-by: Archit Taneja <architt@codeaurora.org>
|
||||
|
||||
---
|
||||
drivers/mtd/nand/nand_base.c | 6 +++++-
|
||||
drivers/mtd/nand/nand_bbt.c | 6 +++++-
|
||||
include/linux/mtd/bbm.h | 7 +++++++
|
||||
3 files changed, 17 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/mtd/nand/nand_base.c
|
||||
+++ b/drivers/mtd/nand/nand_base.c
|
||||
@@ -395,7 +395,11 @@ static int nand_default_block_markbad(st
|
||||
} else {
|
||||
ops.len = ops.ooblen = 1;
|
||||
}
|
||||
- ops.mode = MTD_OPS_PLACE_OOB;
|
||||
+
|
||||
+ if (unlikely(chip->bbt_options & NAND_BBT_ACCESS_BBM_RAW))
|
||||
+ ops.mode = MTD_OPS_RAW;
|
||||
+ else
|
||||
+ ops.mode = MTD_OPS_PLACE_OOB;
|
||||
|
||||
/* Write to first/last page(s) if necessary */
|
||||
if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
|
||||
--- a/drivers/mtd/nand/nand_bbt.c
|
||||
+++ b/drivers/mtd/nand/nand_bbt.c
|
||||
@@ -423,7 +423,11 @@ static int scan_block_fast(struct mtd_in
|
||||
ops.oobbuf = buf;
|
||||
ops.ooboffs = 0;
|
||||
ops.datbuf = NULL;
|
||||
- ops.mode = MTD_OPS_PLACE_OOB;
|
||||
+
|
||||
+ if (unlikely(bd->options & NAND_BBT_ACCESS_BBM_RAW))
|
||||
+ ops.mode = MTD_OPS_RAW;
|
||||
+ else
|
||||
+ ops.mode = MTD_OPS_PLACE_OOB;
|
||||
|
||||
for (j = 0; j < numpages; j++) {
|
||||
/*
|
||||
--- a/include/linux/mtd/bbm.h
|
||||
+++ b/include/linux/mtd/bbm.h
|
||||
@@ -116,6 +116,13 @@ struct nand_bbt_descr {
|
||||
#define NAND_BBT_NO_OOB_BBM 0x00080000
|
||||
|
||||
/*
|
||||
+ * Force MTD_OPS_RAW mode when trying to access bad block markes from OOB. To
|
||||
+ * be used by controllers which can access BBM only when ECC is disabled, i.e,
|
||||
+ * when in RAW access mode
|
||||
+ */
|
||||
+#define NAND_BBT_ACCESS_BBM_RAW 0x00100000
|
||||
+
|
||||
+/*
|
||||
* Flag set by nand_create_default_bbt_descr(), marking that the nand_bbt_descr
|
||||
* was allocated dynamicaly and must be freed in nand_release(). Has no meaning
|
||||
* in nand_chip.bbt_options.
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,82 @@
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [v3,3/5] dt/bindings: qcom_nandc: Add DT bindings
|
||||
From: Archit Taneja <architt@codeaurora.org>
|
||||
X-Patchwork-Id: 6927141
|
||||
Message-Id: <1438578498-32254-4-git-send-email-architt@codeaurora.org>
|
||||
To: linux-mtd@lists.infradead.org, dehrenberg@google.com,
|
||||
cernekee@gmail.com, computersforpeace@gmail.com
|
||||
Cc: linux-arm-msm@vger.kernel.org, agross@codeaurora.org,
|
||||
sboyd@codeaurora.org, linux-kernel@vger.kernel.org,
|
||||
Archit Taneja <architt@codeaurora.org>, devicetree@vger.kernel.org
|
||||
Date: Mon, 3 Aug 2015 10:38:16 +0530
|
||||
|
||||
Add DT bindings document for the Qualcomm NAND controller driver.
|
||||
|
||||
Cc: devicetree@vger.kernel.org
|
||||
|
||||
v3:
|
||||
- Don't use '0x' when specifying nand controller address space
|
||||
- Add optional property for on-flash bbt usage
|
||||
|
||||
Acked-by: Andy Gross <agross@codeaurora.org>
|
||||
Signed-off-by: Archit Taneja <architt@codeaurora.org>
|
||||
|
||||
---
|
||||
.../devicetree/bindings/mtd/qcom_nandc.txt | 49 ++++++++++++++++++++++
|
||||
1 file changed, 49 insertions(+)
|
||||
create mode 100644 Documentation/devicetree/bindings/mtd/qcom_nandc.txt
|
||||
|
||||
--- /dev/null
|
||||
+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
|
||||
@@ -0,0 +1,49 @@
|
||||
+* Qualcomm NAND controller
|
||||
+
|
||||
+Required properties:
|
||||
+- compatible: should be "qcom,ebi2-nand" for IPQ806x
|
||||
+- reg: MMIO address range
|
||||
+- clocks: must contain core clock and always on clock
|
||||
+- clock-names: must contain "core" for the core clock and "aon" for the
|
||||
+ always on clock
|
||||
+- dmas: DMA specifier, consisting of a phandle to the ADM DMA
|
||||
+ controller node and the channel number to be used for
|
||||
+ NAND. Refer to dma.txt and qcom_adm.txt for more details
|
||||
+- dma-names: must be "rxtx"
|
||||
+- qcom,cmd-crci: must contain the ADM command type CRCI block instance
|
||||
+ number specified for the NAND controller on the given
|
||||
+ platform
|
||||
+- qcom,data-crci: must contain the ADM data type CRCI block instance
|
||||
+ number specified for the NAND controller on the given
|
||||
+ platform
|
||||
+
|
||||
+Optional properties:
|
||||
+- nand-bus-width: bus width. Must be 8 or 16. If not present, 8 is chosen
|
||||
+ as default
|
||||
+
|
||||
+- nand-ecc-strength: number of bits to correct per ECC step. Must be 4 or 8
|
||||
+ bits. If not present, 4 is chosen as default
|
||||
+- nand-on-flash-bbt: Create/use on-flash bad block table
|
||||
+
|
||||
+The device tree may optionally contain sub-nodes describing partitions of the
|
||||
+address space. See partition.txt for more detail.
|
||||
+
|
||||
+Example:
|
||||
+
|
||||
+nand@1ac00000 {
|
||||
+ compatible = "qcom,ebi2-nandc";
|
||||
+ reg = <0x1ac00000 0x800>;
|
||||
+
|
||||
+ clocks = <&gcc EBI2_CLK>,
|
||||
+ <&gcc EBI2_AON_CLK>;
|
||||
+ clock-names = "core", "aon";
|
||||
+
|
||||
+ dmas = <&adm_dma 3>;
|
||||
+ dma-names = "rxtx";
|
||||
+ qcom,cmd-crci = <15>;
|
||||
+ qcom,data-crci = <3>;
|
||||
+
|
||||
+ partition@0 {
|
||||
+ ...
|
||||
+ };
|
||||
+};
|
||||
@ -0,0 +1,50 @@
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [v3,4/5] arm: qcom: dts: Add NAND controller node for ipq806x
|
||||
From: Archit Taneja <architt@codeaurora.org>
|
||||
X-Patchwork-Id: 6927121
|
||||
Message-Id: <1438578498-32254-5-git-send-email-architt@codeaurora.org>
|
||||
To: linux-mtd@lists.infradead.org, dehrenberg@google.com,
|
||||
cernekee@gmail.com, computersforpeace@gmail.com
|
||||
Cc: linux-arm-msm@vger.kernel.org, agross@codeaurora.org,
|
||||
sboyd@codeaurora.org, linux-kernel@vger.kernel.org,
|
||||
Archit Taneja <architt@codeaurora.org>, devicetree@vger.kernel.org
|
||||
Date: Mon, 3 Aug 2015 10:38:17 +0530
|
||||
|
||||
The nand controller in IPQ806x is of the 'EBI2 type'. Use the corresponding
|
||||
compatible string.
|
||||
|
||||
Cc: devicetree@vger.kernel.org
|
||||
|
||||
Reviewed-by: Andy Gross <agross@codeaurora.org>
|
||||
Signed-off-by: Archit Taneja <architt@codeaurora.org>
|
||||
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +++++++++++++++
|
||||
1 file changed, 15 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||||
@@ -615,5 +615,21 @@
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
+
|
||||
+ nand@1ac00000 {
|
||||
+ compatible = "qcom,ebi2-nandc";
|
||||
+ reg = <0x1ac00000 0x800>;
|
||||
+
|
||||
+ clocks = <&gcc EBI2_CLK>,
|
||||
+ <&gcc EBI2_AON_CLK>;
|
||||
+ clock-names = "core", "aon";
|
||||
+
|
||||
+ dmas = <&adm_dma 3>;
|
||||
+ dma-names = "rxtx";
|
||||
+ qcom,cmd-crci = <15>;
|
||||
+ qcom,data-crci = <3>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,76 @@
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [v3,5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform
|
||||
From: Archit Taneja <architt@codeaurora.org>
|
||||
X-Patchwork-Id: 6927091
|
||||
Message-Id: <1438578498-32254-6-git-send-email-architt@codeaurora.org>
|
||||
To: linux-mtd@lists.infradead.org, dehrenberg@google.com,
|
||||
cernekee@gmail.com, computersforpeace@gmail.com
|
||||
Cc: linux-arm-msm@vger.kernel.org, agross@codeaurora.org,
|
||||
sboyd@codeaurora.org, linux-kernel@vger.kernel.org,
|
||||
Archit Taneja <architt@codeaurora.org>, devicetree@vger.kernel.org
|
||||
Date: Mon, 3 Aug 2015 10:38:18 +0530
|
||||
|
||||
Enable the NAND controller node on the AP148 platform. Provide pinmux
|
||||
information.
|
||||
|
||||
Cc: devicetree@vger.kernel.org
|
||||
|
||||
Signed-off-by: Archit Taneja <architt@codeaurora.org>
|
||||
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 ++++++++++++++++++++++++++++++++
|
||||
1 file changed, 36 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
|
||||
@@ -61,6 +61,28 @@
|
||||
bias-none;
|
||||
};
|
||||
};
|
||||
+ nand_pins: nand_pins {
|
||||
+ mux {
|
||||
+ pins = "gpio34", "gpio35", "gpio36",
|
||||
+ "gpio37", "gpio38", "gpio39",
|
||||
+ "gpio40", "gpio41", "gpio42",
|
||||
+ "gpio43", "gpio44", "gpio45",
|
||||
+ "gpio46", "gpio47";
|
||||
+ function = "nand";
|
||||
+ drive-strength = <10>;
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+ pullups {
|
||||
+ pins = "gpio39";
|
||||
+ bias-pull-up;
|
||||
+ };
|
||||
+ hold {
|
||||
+ pins = "gpio40", "gpio41", "gpio42",
|
||||
+ "gpio43", "gpio44", "gpio45",
|
||||
+ "gpio46", "gpio47";
|
||||
+ bias-bus-hold;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
gsbi@16300000 {
|
||||
@@ -150,5 +172,19 @@
|
||||
pinctrl-0 = <&pcie1_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
+
|
||||
+ nand@1ac00000 {
|
||||
+ status = "ok";
|
||||
+
|
||||
+ pinctrl-0 = <&nand_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+
|
||||
+ nand-ecc-strength = <4>;
|
||||
+ nand-bus-width = <8>;
|
||||
+ };
|
||||
};
|
||||
};
|
||||
+
|
||||
+&adm_dma {
|
||||
+ status = "ok";
|
||||
+};
|
||||
Loading…
Reference in New Issue