John Crispin
4 years ago
parent
22d896eb21
commit
d3f058db1c
@ -0,0 +1,139 @@
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From a2479dc254ebe31c84fbcfda73f35e2321576494 Mon Sep 17 00:00:00 2001
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From: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
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Date: Tue, 19 Mar 2019 13:57:38 +0800
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Subject: [PATCH 1/6] mtd: mtk ecc: move mtk ecc header file to include/mtd
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Change-Id: I8dc1d30e21b40d68ef5efd9587012f82970156a5
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Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
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---
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drivers/mtd/nand/raw/mtk_ecc.c | 3 +--
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drivers/mtd/nand/raw/mtk_nand.c | 2 +-
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{drivers/mtd/nand/raw => include/linux/mtd}/mtk_ecc.h | 0
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3 files changed, 2 insertions(+), 3 deletions(-)
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rename {drivers/mtd/nand/raw => include/linux/mtd}/mtk_ecc.h (100%)
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--- a/drivers/mtd/nand/raw/mtk_ecc.c
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+++ b/drivers/mtd/nand/raw/mtk_ecc.c
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@@ -23,8 +23,7 @@
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/mutex.h>
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-
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-#include "mtk_ecc.h"
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+#include <linux/mtd/mtk_ecc.h>
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#define ECC_IDLE_MASK BIT(0)
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#define ECC_IRQ_EN BIT(0)
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--- a/drivers/mtd/nand/raw/mtk_nand.c
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+++ b/drivers/mtd/nand/raw/mtk_nand.c
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@@ -25,7 +25,7 @@
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#include <linux/iopoll.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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-#include "mtk_ecc.h"
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+#include <linux/mtd/mtk_ecc.h>
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/* NAND controller register definition */
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#define NFI_CNFG (0x00)
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--- /dev/null
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+++ b/include/linux/mtd/mtk_ecc.h
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@@ -0,0 +1,49 @@
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+/*
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+ * MTK SDG1 ECC controller
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+ *
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+ * Copyright (c) 2016 Mediatek
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+ * Authors: Xiaolei Li <xiaolei.li@mediatek.com>
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+ * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ */
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+
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+#ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__
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+#define __DRIVERS_MTD_NAND_MTK_ECC_H__
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+
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+#include <linux/types.h>
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+
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+enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1};
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+enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE};
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+
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+struct device_node;
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+struct mtk_ecc;
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+
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+struct mtk_ecc_stats {
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+ u32 corrected;
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+ u32 bitflips;
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+ u32 failed;
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+};
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+
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+struct mtk_ecc_config {
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+ enum mtk_ecc_operation op;
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+ enum mtk_ecc_mode mode;
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+ dma_addr_t addr;
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+ u32 strength;
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+ u32 sectors;
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+ u32 len;
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+};
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+
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+int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32);
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+void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int);
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+int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation);
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+int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *);
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+void mtk_ecc_disable(struct mtk_ecc *);
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+void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p);
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+unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc);
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+
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+struct mtk_ecc *of_mtk_ecc_get(struct device_node *);
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+void mtk_ecc_release(struct mtk_ecc *);
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+
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+#endif
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--- a/drivers/mtd/nand/raw/mtk_ecc.h
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+++ /dev/null
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@@ -1,47 +0,0 @@
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-/* SPDX-License-Identifier: GPL-2.0 OR MIT */
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-/*
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- * MTK SDG1 ECC controller
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- *
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- * Copyright (c) 2016 Mediatek
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- * Authors: Xiaolei Li <xiaolei.li@mediatek.com>
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- * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
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- */
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-
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-#ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__
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-#define __DRIVERS_MTD_NAND_MTK_ECC_H__
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-
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-#include <linux/types.h>
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-
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-enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1};
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-enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE};
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-
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-struct device_node;
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-struct mtk_ecc;
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-
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-struct mtk_ecc_stats {
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- u32 corrected;
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- u32 bitflips;
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- u32 failed;
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-};
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-
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-struct mtk_ecc_config {
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- enum mtk_ecc_operation op;
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- enum mtk_ecc_mode mode;
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- dma_addr_t addr;
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- u32 strength;
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- u32 sectors;
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- u32 len;
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-};
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-
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-int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32);
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-void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int);
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-int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation);
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-int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *);
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-void mtk_ecc_disable(struct mtk_ecc *);
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-void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p);
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-unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc);
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-
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-struct mtk_ecc *of_mtk_ecc_get(struct device_node *);
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-void mtk_ecc_release(struct mtk_ecc *);
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-
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-#endif
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@ -0,0 +1,31 @@
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From b341f120cfc9ca1dfd48364b7f36ac2c1fbdea43 Mon Sep 17 00:00:00 2001
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From: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
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Date: Wed, 3 Apr 2019 16:30:01 +0800
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Subject: [PATCH 3/6] mtd: spinand: disable on-die ECC
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Change-Id: I9745adaed5295202fabbe8ab8947885c57a5b847
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Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
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---
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drivers/mtd/nand/spi/core.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/drivers/mtd/nand/spi/core.c
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+++ b/drivers/mtd/nand/spi/core.c
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@@ -552,7 +552,7 @@ static int spinand_mtd_read(struct mtd_i
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int ret = 0;
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if (ops->mode != MTD_OPS_RAW && spinand->eccinfo.ooblayout)
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- enable_ecc = true;
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+ enable_ecc = false;
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mutex_lock(&spinand->lock);
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@@ -600,7 +600,7 @@ static int spinand_mtd_write(struct mtd_
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int ret = 0;
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if (ops->mode != MTD_OPS_RAW && mtd->ooblayout)
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- enable_ecc = true;
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+ enable_ecc = false;
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mutex_lock(&spinand->lock);
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,97 @@
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From c813fbe806257c574240770ef716fbee19f7dbfa Mon Sep 17 00:00:00 2001
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From: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
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Date: Thu, 6 Jun 2019 16:29:04 +0800
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Subject: [PATCH] spi: spi-mem: Mediatek: Add SPI Nand support for MT7629
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Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
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---
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arch/arm/boot/dts/mt7629-rfb.dts | 45 ++++++++++++++++++++++++++++++++
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arch/arm/boot/dts/mt7629.dtsi | 22 ++++++++++++++++
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3 files changed, 79 insertions(+)
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--- a/arch/arm/boot/dts/mt7629.dtsi
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+++ b/arch/arm/boot/dts/mt7629.dtsi
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@@ -259,6 +259,28 @@
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status = "disabled";
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};
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+ bch: ecc@1100e000 {
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+ compatible = "mediatek,mt7622-ecc";
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+ reg = <0x1100e000 0x1000>;
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+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&pericfg CLK_PERI_NFIECC_PD>;
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+ clock-names = "nfiecc_clk";
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+ status = "disabled";
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+ };
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+
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+ snfi: spi@1100d000 {
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+ compatible = "mediatek,mt7629-snfi";
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+ reg = <0x1100d000 0x1000>;
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+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&pericfg CLK_PERI_NFI_PD>,
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+ <&pericfg CLK_PERI_SNFI_PD>;
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+ clock-names = "nfi_clk", "spi_clk";
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+ ecc-engine = <&bch>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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spi: spi@1100a000 {
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compatible = "mediatek,mt7629-spi",
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"mediatek,mt7622-spi";
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--- a/arch/arm/boot/dts/mt7629-rfb.dts
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+++ b/arch/arm/boot/dts/mt7629-rfb.dts
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@@ -281,6 +281,52 @@
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};
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};
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+&bch {
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+ status = "okay";
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+};
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+
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+&snfi {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&serial_nand_pins>;
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+ status = "okay";
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+
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+ spi_nand@0 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "spi-nand";
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+ spi-max-frequency = <104000000>;
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+ reg = <0>;
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+
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+ partitions {
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+ compatible = "fixed-partitions";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ partition@0 {
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+ label = "Bootloader";
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+ reg = <0x00000 0x0100000>;
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+ read-only;
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+ };
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+
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+ partition@100000 {
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+ label = "Config";
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+ reg = <0x100000 0x0040000>;
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+ };
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+
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+ partition@140000 {
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+ label = "factory";
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+ reg = <0x140000 0x0080000>;
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+ };
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+
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+ partition@1c0000 {
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+ label = "firmware";
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+ reg = <0x1c0000 0x1000000>;
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+ };
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+
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+ };
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+ };
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+};
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+
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&spi {
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pinctrl-names = "default";
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pinctrl-0 = <&spi_pins>;
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@ -0,0 +1,98 @@
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diff -urN a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi 2020-03-02 17:16:13.700464470 +0800
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+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi 2020-03-02 17:15:55.276885406 +0800
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@@ -554,6 +554,19 @@
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status = "disabled";
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};
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+ snfi: spi@1100d000 {
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+ compatible = "mediatek,mt7622-snfi";
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+ reg = <0 0x1100d000 0 0x1000>;
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+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&pericfg CLK_PERI_NFI_PD>,
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+ <&pericfg CLK_PERI_SNFI_PD>;
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+ clock-names = "nfi_clk", "spi_clk";
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+ ecc-engine = <&bch>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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nor_flash: spi@11014000 {
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compatible = "mediatek,mt7622-nor",
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"mediatek,mt8173-nor";
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diff -urN a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts 2020-03-02 17:16:25.492193459 +0800
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+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts 2020-03-02 17:16:35.243968416 +0800
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@@ -108,7 +108,7 @@
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};
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&bch {
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- status = "disabled";
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+ status = "okay";
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};
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&btif {
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@@ -541,6 +541,62 @@
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status = "disable";
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};
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+&snfi {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&serial_nand_pins>;
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+ status = "okay";
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+
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+ spi_nand@0 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "spi-nand";
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+ spi-max-frequency = <104000000>;
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+ reg = <0>;
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+
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+ partitions {
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+ compatible = "fixed-partitions";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ partition@0 {
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+ label = "Preloader";
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+ reg = <0x00000 0x0080000>;
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+ read-only;
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+ };
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+
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+ partition@80000 {
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+ label = "ATF";
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+ reg = <0x80000 0x0040000>;
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+ };
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+
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+ partition@c0000 {
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+ label = "Bootloader";
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+ reg = <0xc0000 0x0080000>;
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+ };
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+
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+ partition@140000 {
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+ label = "Config";
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+ reg = <0x140000 0x0080000>;
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+ };
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+
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+ partition@1c0000 {
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+ label = "Factory";
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+ reg = <0x1c0000 0x0040000>;
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+ };
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+
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+ partition@200000 {
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+ label = "firmware";
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+ reg = <0x200000 0x2000000>;
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+ };
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+
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+ partition@2200000 {
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+ label = "User_data";
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+ reg = <0x2200000 0x4000000>;
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+ };
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+ };
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+ };
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+};
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+
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&spi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&spic0_pins>;
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@ -0,0 +1,32 @@
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diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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index 1ec68de..44cc80c 100644
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--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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@@ -105,6 +105,18 @@
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regulator-boot-on;
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regulator-always-on;
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};
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+
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+ wmac: wmac@18000000 {
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+ compatible = "mediatek,mt7622-wmac";
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+ reg = <0 0x18000000 0 0x100000>;
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+ interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>;
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+
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+ mediatek,infracfg = <&infracfg>;
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+ status = "okay";
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+
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+ power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
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+ mediatek,mtd-eeprom = <&factory 0x0000>;
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+ };
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};
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&bch {
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@@ -579,7 +591,7 @@
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reg = <0x140000 0x0080000>;
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};
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- partition@1c0000 {
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+ factory: partition@1c0000 {
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label = "Factory";
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reg = <0x1c0000 0x0040000>;
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};
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