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@ -93,13 +93,10 @@ static void __init ssb_fixup_pcibridge(struct pci_dev *dev)
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/* Enable PCI bridge BAR1 prefetch and burst */
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pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
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/* Make sure our latency is high enough to handle the devices behind us */
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xa8);
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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return ssb_mips_irq(extpci_core->dev) + 2;
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}
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@ -113,7 +110,7 @@ static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
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if (unlikely(pc->cardbusmode && dev > 1))
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goto out;
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if (bus == 0) {//FIXME busnumber ok?
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if (bus == 0) {
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/* Type 0 transaction */
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if (unlikely(dev >= SSB_PCI_SLOT_MAX))
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goto out;
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@ -227,7 +224,7 @@ static int ssb_extpci_write_config(struct ssb_pcicore *pc,
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val = *((const u32 *)buf);
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break;
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}
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writel(val, mmio);
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writel(*((const u32 *)buf), mmio);
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err = 0;
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unmap:
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@ -310,8 +307,6 @@ static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
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udelay(150);
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val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
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pcicore_write32(pc, SSB_PCICORE_CTL, val);
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val = SSB_PCICORE_ARBCTL_INTERN;
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pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
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udelay(1);
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//TODO cardbus mode
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@ -341,7 +336,6 @@ static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
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* The following needs change, if we want to port hostmode
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* to non-MIPS platform. */
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set_io_port_base((unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000));
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mdelay(300);
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register_pci_controller(&ssb_pcicore_controller);
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}
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