ralink: add support for mt7628
Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 43197v19.07.3_mercusys_ac12_duma
John Crispin
10 years ago
parent
f8404aaf9e
commit
cadf517107
@ -0,0 +1,59 @@
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/dts-v1/;
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/include/ "mt7628an.dtsi"
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/ {
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compatible = "mediatek,mt7628an-eval-board", "mediatek,mt7628an-soc";
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model = "Mediatek MT7628AN evaluation board";
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memory@0 {
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reg = <0x0 0x2000000>;
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};
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chosen {
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bootargs = "console=ttyS0,57600 init=/init";
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};
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palmbus@10000000 {
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spi@b00 {
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status = "okay";
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m25p80@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "en25q64";
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reg = <0 0>;
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linux,modalias = "m25p80", "en25q64";
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spi-max-frequency = <10000000>;
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m25p,chunked-io = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x30000>;
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read-only;
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};
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partition@30000 {
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label = "u-boot-env";
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reg = <0x30000 0x10000>;
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read-only;
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};
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factory: partition@40000 {
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label = "factory";
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reg = <0x40000 0x10000>;
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read-only;
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};
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partition@50000 {
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label = "firmware";
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reg = <0x50000 0x7b0000>;
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};
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};
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};
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};
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pcie@10140000 {
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status = "okay";
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};
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};
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@ -0,0 +1,222 @@
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "ralink,mtk7628an-soc";
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cpus {
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cpu@0 {
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compatible = "mips,mips24KEc";
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};
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};
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cpuintc: cpuintc@0 {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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palmbus@10000000 {
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compatible = "palmbus";
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reg = <0x10000000 0x200000>;
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ranges = <0x0 0x10000000 0x1FFFFF>;
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#address-cells = <1>;
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#size-cells = <1>;
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sysc@0 {
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compatible = "ralink,mt7620a-sysc";
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reg = <0x0 0x100>;
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};
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watchdog@120 {
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compatible = "ralink,mt7628an-wdt", "mtk,mt7621-wdt";
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reg = <0x120 0x10>;
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resets = <&rstctrl 8>;
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reset-names = "wdt";
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interrupt-parent = <&intc>;
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interrupts = <24>;
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};
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intc: intc@200 {
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compatible = "ralink,mt7628an-intc", "ralink,rt2880-intc";
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reg = <0x200 0x100>;
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resets = <&rstctrl 9>;
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reset-names = "intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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ralink,intc-registers = <0x9c 0xa0
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0x6c 0xa4
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0x80 0x78>;
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};
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memc@300 {
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compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
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reg = <0x300 0x100>;
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resets = <&rstctrl 20>;
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reset-names = "mc";
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interrupt-parent = <&intc>;
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interrupts = <3>;
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};
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gpio@600 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
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reg = <0x600 0x100>;
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gpio0: bank@0 {
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reg = <0>;
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compatible = "mtk,mt7621-gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio1: bank@1 {
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reg = <1>;
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compatible = "mtk,mt7621-gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio2: bank@2 {
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reg = <2>;
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compatible = "mtk,mt7621-gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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spi@b00 {
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compatible = "ralink,mt7621-spi";
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reg = <0xb00 0x100>;
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resets = <&rstctrl 18>;
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reset-names = "spi";
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#address-cells = <1>;
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#size-cells = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi_pins>;
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status = "disabled";
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};
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uartlite@c00 {
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compatible = "ns16550a";
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reg = <0xc00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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no-loopback-test;
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resets = <&rstctrl 12>;
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reset-names = "uartl";
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interrupt-parent = <&intc>;
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interrupts = <20>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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};
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};
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pinctrl {
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compatible = "ralink,rt2880-pinmux";
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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state_default: pinctrl0 {
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};
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spi_pins: spi {
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spi {
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ralink,group = "spi";
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ralink,function = "spi";
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};
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};
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uart0_pins: uartlite {
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uart {
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ralink,group = "uart0";
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ralink,function = "uart";
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};
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};
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};
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rstctrl: rstctrl {
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compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
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#reset-cells = <1>;
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};
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usbphy {
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compatible = "ralink,mt7628an-usbphy", "ralink,mt7620a-usbphy";
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resets = <&rstctrl 22>;
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reset-names = "host";
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};
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ehci@101c0000 {
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compatible = "ralink,rt3xxx-ehci";
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reg = <0x101c0000 0x1000>;
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interrupt-parent = <&intc>;
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interrupts = <18>;
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};
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ohci@101c1000 {
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compatible = "ralink,rt3xxx-ohci";
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reg = <0x101c1000 0x1000>;
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interrupt-parent = <&intc>;
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interrupts = <18>;
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};
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ethernet@10100000 {
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compatible = "ralink,rt5350-eth";
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reg = <0x10100000 10000>;
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interrupt-parent = <&cpuintc>;
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interrupts = <5>;
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};
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esw@10110000 {
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compatible = "ralink,rt3050-esw";
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reg = <0x10110000 8000>;
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interrupt-parent = <&intc>;
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interrupts = <17>;
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};
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pcie@10140000 {
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compatible = "mediatek,mt7620-pci";
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reg = <0x10140000 0x100
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0x10142000 0x100>;
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ranges = <0x2000000 0 0x8000000 0x2000000 0 0x1000000 /* pci memory */
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0x1000000 0 0x00000000 0x10160000 0 0x10000>; /* io space */
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resets = <&rstctrl 26>;
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reset-names = "pcie0";
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interrupt-parent = <&cpuintc>;
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interrupts = <4>;
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status = "disabled";
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pcie-bridge {
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reg = <0x0000 0 0 0 0>;
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device_type = "pci";
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};
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};
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};
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@ -0,0 +1,184 @@
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CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
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CONFIG_ARCH_DISCARD_MEMBLOCK=y
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CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
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CONFIG_ARCH_HAS_RESET_CONTROLLER=y
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CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
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CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
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CONFIG_ARCH_REQUIRE_GPIOLIB=y
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CONFIG_ARCH_SUSPEND_POSSIBLE=y
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CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
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CONFIG_AT803X_PHY=y
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CONFIG_CC_OPTIMIZE_FOR_SIZE=y
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CONFIG_CEVT_R4K=y
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CONFIG_CLKDEV_LOOKUP=y
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CONFIG_CLKEVT_RT3352=y
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CONFIG_CLKSRC_MMIO=y
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CONFIG_CLKSRC_OF=y
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CONFIG_CLONE_BACKWARDS=y
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CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
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CONFIG_CMDLINE_BOOL=y
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# CONFIG_CMDLINE_OVERRIDE is not set
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CONFIG_CPU_GENERIC_DUMP_TLB=y
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CONFIG_CPU_HAS_PREFETCH=y
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CONFIG_CPU_HAS_SYNC=y
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CONFIG_CPU_LITTLE_ENDIAN=y
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CONFIG_CPU_MIPS32=y
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# CONFIG_CPU_MIPS32_R1 is not set
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CONFIG_CPU_MIPS32_R2=y
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CONFIG_CPU_MIPSR2=y
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CONFIG_CPU_R4K_CACHE_TLB=y
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CONFIG_CPU_R4K_FPU=y
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CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
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CONFIG_CPU_SUPPORTS_HIGHMEM=y
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CONFIG_CSRC_R4K=y
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CONFIG_DEBUG_PINCTRL=y
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CONFIG_DMA_NONCOHERENT=y
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# CONFIG_DTB_MT7620A_EVAL is not set
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# CONFIG_DTB_MT7628AN_EVAL is not set
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CONFIG_DTB_RT_NONE=y
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CONFIG_DTC=y
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CONFIG_EARLY_PRINTK=y
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CONFIG_GENERIC_ATOMIC64=y
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
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CONFIG_GENERIC_CMOS_UPDATE=y
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CONFIG_GENERIC_IO=y
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CONFIG_GENERIC_IRQ_SHOW=y
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CONFIG_GENERIC_NET_UTILS=y
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CONFIG_GENERIC_PCI_IOMAP=y
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CONFIG_GENERIC_SMP_IDLE_THREAD=y
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CONFIG_GPIOLIB=y
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CONFIG_GPIO_DEVRES=y
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CONFIG_GPIO_MT7621=y
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# CONFIG_GPIO_RALINK is not set
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CONFIG_GPIO_SYSFS=y
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CONFIG_HARDWARE_WATCHPOINTS=y
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CONFIG_HAS_DMA=y
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CONFIG_HAS_IOMEM=y
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CONFIG_HAS_IOPORT=y
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# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
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CONFIG_HAVE_ARCH_JUMP_LABEL=y
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CONFIG_HAVE_ARCH_KGDB=y
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CONFIG_HAVE_ARCH_TRACEHOOK=y
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# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
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CONFIG_HAVE_CC_STACKPROTECTOR=y
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CONFIG_HAVE_CLK=y
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CONFIG_HAVE_CONTEXT_TRACKING=y
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CONFIG_HAVE_C_RECORDMCOUNT=y
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CONFIG_HAVE_DEBUG_KMEMLEAK=y
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CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
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CONFIG_HAVE_DMA_API_DEBUG=y
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CONFIG_HAVE_DMA_ATTRS=y
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CONFIG_HAVE_DYNAMIC_FTRACE=y
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CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
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CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
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CONFIG_HAVE_FUNCTION_TRACER=y
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CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
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CONFIG_HAVE_GENERIC_DMA_COHERENT=y
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CONFIG_HAVE_IDE=y
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CONFIG_HAVE_KVM=y
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CONFIG_HAVE_MACH_CLKDEV=y
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CONFIG_HAVE_MEMBLOCK=y
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CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
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CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
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CONFIG_HAVE_NET_DSA=y
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CONFIG_HAVE_OPROFILE=y
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CONFIG_HAVE_PERF_EVENTS=y
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CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
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CONFIG_HW_HAS_PCI=y
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CONFIG_HW_RANDOM=m
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CONFIG_HZ_PERIODIC=y
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CONFIG_ICPLUS_PHY=y
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CONFIG_IMAGE_CMDLINE_HACK=y
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CONFIG_INET_LRO=y
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CONFIG_INITRAMFS_SOURCE=""
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CONFIG_IRQCHIP=y
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CONFIG_IRQ_CPU=y
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CONFIG_IRQ_DOMAIN=y
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CONFIG_IRQ_FORCED_THREADING=y
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CONFIG_IRQ_INTC=y
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CONFIG_IRQ_WORK=y
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CONFIG_MDIO_BOARDINFO=y
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CONFIG_MIPS=y
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# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
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CONFIG_MIPS_L1_CACHE_SHIFT=5
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# CONFIG_MIPS_MACHINE is not set
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CONFIG_MIPS_MT_DISABLED=y
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# CONFIG_MIPS_O32_FP64_SUPPORT is not set
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CONFIG_MODULES_USE_ELF_REL=y
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CONFIG_MT7621_WDT=y
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# CONFIG_MTD_CFI_INTELEXT is not set
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CONFIG_MTD_CMDLINE_PARTS=y
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CONFIG_MTD_M25P80=y
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CONFIG_MTD_NAND_MT7620=y
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CONFIG_MTD_PHYSMAP=y
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CONFIG_MTD_SPLIT_FIRMWARE=y
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CONFIG_MTD_UIMAGE_SPLIT=y
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CONFIG_NEED_DMA_MAP_STATE=y
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CONFIG_NEED_PER_CPU_KM=y
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CONFIG_NET_RALINK=y
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CONFIG_NET_RALINK_ESW_RT3052=y
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# CONFIG_NET_RALINK_MT7620 is not set
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CONFIG_NET_RALINK_RT305X=y
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CONFIG_NLS=m
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CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
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CONFIG_OF=y
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CONFIG_OF_ADDRESS=y
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CONFIG_OF_EARLY_FLATTREE=y
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CONFIG_OF_FLATTREE=y
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CONFIG_OF_GPIO=y
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CONFIG_OF_IRQ=y
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CONFIG_OF_MDIO=y
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CONFIG_OF_MTD=y
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CONFIG_OF_NET=y
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CONFIG_OF_PCI=y
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CONFIG_OF_PCI_IRQ=y
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CONFIG_PAGEFLAGS_EXTENDED=y
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CONFIG_PCI=y
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CONFIG_PCI_DOMAINS=y
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CONFIG_PERF_USE_VMALLOC=y
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CONFIG_PHYLIB=y
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# CONFIG_PINCONF is not set
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_RT2880=y
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# CONFIG_PINCTRL_SINGLE is not set
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# CONFIG_PREEMPT_RCU is not set
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CONFIG_RALINK=y
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CONFIG_RALINK_USBPHY=y
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# CONFIG_RALINK_WDT is not set
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CONFIG_RA_NAT_NONE=y
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# CONFIG_RCU_STALL_COMMON is not set
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CONFIG_RESET_CONTROLLER=y
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# CONFIG_SCSI_DMA is not set
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CONFIG_SERIAL_8250_NR_UARTS=4
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CONFIG_SERIAL_8250_RT288X=y
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CONFIG_SERIAL_OF_PLATFORM=y
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# CONFIG_SLAB is not set
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CONFIG_SLUB=y
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CONFIG_SOC_MT7620=y
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# CONFIG_SOC_MT7621 is not set
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# CONFIG_SOC_RT288X is not set
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# CONFIG_SOC_RT305X is not set
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# CONFIG_SOC_RT3883 is not set
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CONFIG_SPI=y
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CONFIG_SPI_MASTER=y
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CONFIG_SPI_RT2880=y
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CONFIG_SWCONFIG=y
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CONFIG_SYS_HAS_CPU_MIPS32_R1=y
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CONFIG_SYS_HAS_CPU_MIPS32_R2=y
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CONFIG_SYS_HAS_EARLY_PRINTK=y
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CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
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CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
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CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
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CONFIG_TICK_CPU_ACCOUNTING=y
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CONFIG_USB=m
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CONFIG_USB_COMMON=m
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# CONFIG_USB_EHCI_HCD is not set
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CONFIG_USB_PHY=y
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CONFIG_USB_SUPPORT=y
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# CONFIG_USB_UHCI_HCD is not set
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CONFIG_USE_OF=y
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CONFIG_WATCHDOG_CORE=y
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CONFIG_ZONE_DMA_FLAG=0
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@ -0,0 +1,18 @@
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#
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# Copyright (C) 2011 OpenWrt.org
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#
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# This is free software, licensed under the GNU General Public License v2.
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# See /LICENSE for more information.
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#
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define Profile/Default
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NAME:=Default Profile
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PACKAGES:=\
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kmod-usb-core kmod-usb2 kmod-usb-ohci \
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kmod-ledtrig-usbdev
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endef
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define Profile/Default/Description
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Default package set compatible with most boards.
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endef
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$(eval $(call Profile,Default))
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@ -0,0 +1,15 @@
|
||||
#
|
||||
# Copyright (C) 2009 OpenWrt.org
|
||||
#
|
||||
|
||||
SUBTARGET:=mt7628
|
||||
BOARDNAME:=MT7628 based boards
|
||||
ARCH_PACKAGES:=ramips_24kec
|
||||
FEATURES+=usb
|
||||
CPU_TYPE:=24kec
|
||||
CPU_SUBTYPE:=dsp
|
||||
|
||||
define Target/Description
|
||||
Build firmware images for Ralink MT7628 based boards.
|
||||
endef
|
||||
|
||||
Loading…
Reference in New Issue