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ar71xx: add support for Wallys DR342

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Wallys DR342 is a 5 GHz, 2T2R AP/CPE board based on Atheros AR9342.

Short specification:

- 560/450/225 MHz (CPU/DDR/AHB)
- 1x Gbps Ethernet (AR8035) with passive PoE support (24-56 V)
- 64 MB of RAM (DDR2)
- 16 MB of FLASH
- 2T2R 5 GHz with external FEM (SKY85728-11), up to 30 dBm
- 2x MMCX connectors
- miniPCIe connector with PCIe and USB 2.0 buses
- optional miniSIM slot
- 7x LED, 1x button
- UART, (E)JTAG and LED headers
- 1x DC jack for main power (12-56 V)

Flash instruction (do it under U-Boot, using UART):

1. tftp 0x82000000 lede-ar71xx-generic-dr342-squashfs-sysupgrade.bin
2. erase 0x9f050000 +$filesize
3. cp.b $fileaddr 0x9f050000 $filesize
4. setenv bootcmd "bootm 0x9f050000"
5. saveenv && reset

Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
v19.07.3_mercusys_ac12_duma
Piotr Dymacz 7 years ago
parent fa36bea470
commit c83bdd094e
13 changed files with 123 additions and 45 deletions
Show Stats Download Patch File Download Diff File

1
target/linux/ar71xx/base-files/etc/board.d/02_network
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@ -70,6 +70,7 @@ ar71xx_setup_interfaces()
cap4200ag|\
cf-e380ac-v1|\
cf-e380ac-v2|\
dr342|\
eap120|\
eap300v2|\
eap7660d|\

1
target/linux/ar71xx/base-files/etc/diag.sh
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@ -38,6 +38,7 @@ get_status_led() {
ap531b0|\
cpe505n|\
db120|\
dr342|\
dr344|\
tew-632brp|\
tl-wr942n-v1|\

3
target/linux/ar71xx/base-files/lib/ar71xx.sh
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@ -603,6 +603,9 @@ ar71xx_board_detect() {
*"Domino Pi")
name="gl-domino"
;;
*"DR342")
name="dr342"
;;
*"DR344")
name="dr344"
;;

1
target/linux/ar71xx/base-files/lib/upgrade/platform.sh
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@ -238,6 +238,7 @@ platform_check_image() {
dlan-hotspot|\
dlan-pro-1200-ac|\
dlan-pro-500-wp|\
dr342|\
dr531|\
dragino2|\
ebr-2310-c1|\

1
target/linux/ar71xx/config-4.4
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@ -95,6 +95,7 @@ CONFIG_ATH79_MACH_DLAN_HOTSPOT=y
CONFIG_ATH79_MACH_DLAN_PRO_1200_AC=y
CONFIG_ATH79_MACH_DLAN_PRO_500_WP=y
# CONFIG_ATH79_MACH_DOMYWIFI_DW33D is not set
CONFIG_ATH79_MACH_DR342=y
CONFIG_ATH79_MACH_DR344=y
CONFIG_ATH79_MACH_DR531=y
CONFIG_ATH79_MACH_DRAGINO2=y

1
target/linux/ar71xx/config-4.9
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@ -93,6 +93,7 @@ CONFIG_ATH79_MACH_DLAN_HOTSPOT=y
CONFIG_ATH79_MACH_DLAN_PRO_1200_AC=y
CONFIG_ATH79_MACH_DLAN_PRO_500_WP=y
# CONFIG_ATH79_MACH_DOMYWIFI_DW33D is not set
CONFIG_ATH79_MACH_DR342=y
CONFIG_ATH79_MACH_DR344=y
CONFIG_ATH79_MACH_DR531=y
CONFIG_ATH79_MACH_DRAGINO2=y

12
target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt
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@ -638,9 +638,21 @@ config ATH79_MACH_DOMYWIFI_DW33D
select ATH79_DEV_WMAC
select ATH79_DEV_USB
config ATH79_MACH_DR342
bool "Wallys DR342 board support"
select SOC_AR934X
select ATH79_DEV_AP9X_PCI if PCI
select ATH79_DEV_ETH
select ATH79_DEV_GPIO_BUTTONS
select ATH79_DEV_LEDS_GPIO
select ATH79_DEV_M25P80
select ATH79_DEV_USB
select ATH79_DEV_WMAC
config ATH79_MACH_DR344
bool "Wallys DR344 board support"
select SOC_AR934X
select ATH79_DEV_AP9X_PCI if PCI
select ATH79_DEV_ETH
select ATH79_DEV_GPIO_BUTTONS
select ATH79_DEV_LEDS_GPIO

1
target/linux/ar71xx/files/arch/mips/ath79/Makefile
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@ -102,6 +102,7 @@ obj-$(CONFIG_ATH79_MACH_DLAN_HOTSPOT) += mach-dlan-hotspot.o
obj-$(CONFIG_ATH79_MACH_DLAN_PRO_1200_AC) += mach-dlan-pro-1200-ac.o
obj-$(CONFIG_ATH79_MACH_DLAN_PRO_500_WP) += mach-dlan-pro-500-wp.o
obj-$(CONFIG_ATH79_MACH_DOMYWIFI_DW33D) += mach-domywifi-dw33d.o
obj-$(CONFIG_ATH79_MACH_DR342) += mach-dr344.o
obj-$(CONFIG_ATH79_MACH_DR344) += mach-dr344.o
obj-$(CONFIG_ATH79_MACH_DR531) += mach-dr531.o
obj-$(CONFIG_ATH79_MACH_DRAGINO2) += mach-dragino2.o

135
target/linux/ar71xx/files/arch/mips/ath79/mach-dr344.c
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@ -1,9 +1,10 @@
/*
* Wallys DR344 board support
* Wallys DR342/DR344 boards support
*
* Copyright (c) 2011 Qualcomm Atheros
* Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
* Copyright (c) 2015 Philippe Duchein <wireless-dev@duchein.net>
* Copyright (c) 2017 Piotr Dymacz <pepe2k@gmail.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -39,24 +40,51 @@
#include "dev-wmac.h"
#include "machtypes.h"
#define DR344_GPIO_LED_SIG1 12
#define DR344_GPIO_LED_SIG2 13
#define DR344_GPIO_LED_SIG3 14
#define DR344_GPIO_LED_SIG4 15
#define DR344_GPIO_LED_STATUS 11
#define DR34X_GPIO_LED_SIG1 12
#define DR34X_GPIO_LED_SIG2 13
#define DR34X_GPIO_LED_SIG3 14
#define DR34X_GPIO_LED_SIG4 15
#define DR34X_GPIO_LED_STATUS 11
#define DR344_GPIO_LED_LAN 17
#define DR344_GPIO_EXTERNAL_LNA0 18
#define DR344_GPIO_EXTERNAL_LNA1 19
#define DR344_GPIO_BTN_RESET 16
#define DR34X_GPIO_BTN_RESET 16
#define DR344_KEYS_POLL_INTERVAL 20 /* msecs */
#define DR344_KEYS_DEBOUNCE_INTERVAL (3 * DR344_KEYS_POLL_INTERVAL)
#define DR344_MAC0_OFFSET 0
#define DR344_MAC1_OFFSET 8
#define DR344_WMAC_CALDATA_OFFSET 0x1000
#define DR344_PCIE_CALDATA_OFFSET 0x5000
#define DR34X_MAC0_OFFSET 0
#define DR34X_MAC1_OFFSET 8
#define DR34X_WMAC_CALDATA_OFFSET 0x1000
static struct gpio_led dr342_leds_gpio[] __initdata = {
{
.name = "dr342:green:status",
.gpio = DR34X_GPIO_LED_STATUS,
.active_low = 1,
},
{
.name = "dr342:green:sig1",
.gpio = DR34X_GPIO_LED_SIG1,
.active_low = 1,
},
{
.name = "dr342:green:sig2",
.gpio = DR34X_GPIO_LED_SIG2,
.active_low = 1,
},
{
.name = "dr342:green:sig3",
.gpio = DR34X_GPIO_LED_SIG3,
.active_low = 1,
},
{
.name = "dr342:green:sig4",
.gpio = DR34X_GPIO_LED_SIG4,
.active_low = 1,
}
};
static struct gpio_led dr344_leds_gpio[] __initdata = {
{
@ -66,96 +94,82 @@ static struct gpio_led dr344_leds_gpio[] __initdata = {
},
{
.name = "dr344:green:status",
.gpio = DR344_GPIO_LED_STATUS,
.gpio = DR34X_GPIO_LED_STATUS,
.active_low = 1,
},
{
.name = "dr344:green:sig1",
.gpio = DR344_GPIO_LED_SIG1,
.gpio = DR34X_GPIO_LED_SIG1,
.active_low = 1,
},
{
.name = "dr344:green:sig2",
.gpio = DR344_GPIO_LED_SIG2,
.gpio = DR34X_GPIO_LED_SIG2,
.active_low = 1,
},
{
.name = "dr344:green:sig3",
.gpio = DR344_GPIO_LED_SIG3,
.gpio = DR34X_GPIO_LED_SIG3,
.active_low = 1,
},
{
.name = "dr344:green:sig4",
.gpio = DR344_GPIO_LED_SIG4,
.gpio = DR34X_GPIO_LED_SIG4,
.active_low = 1,
}
};
static struct gpio_keys_button dr344_gpio_keys[] __initdata = {
static struct gpio_keys_button dr34x_gpio_keys[] __initdata = {
{
.desc = "reset",
.type = EV_KEY,
.code = KEY_RESTART,
.debounce_interval = DR344_KEYS_DEBOUNCE_INTERVAL,
.gpio = DR344_GPIO_BTN_RESET,
.gpio = DR34X_GPIO_BTN_RESET,
.active_low = 1,
},
};
static struct at803x_platform_data dr344_at803x_data = {
static struct at803x_platform_data dr34x_at803x_data = {
.disable_smarteee = 1,
.enable_rgmii_rx_delay = 1,
.enable_rgmii_tx_delay = 1,
};
static struct mdio_board_info dr344_mdio0_info[] = {
static struct mdio_board_info dr34x_mdio0_info[] = {
{
.bus_id = "ag71xx-mdio.0",
.phy_addr = 0,
.platform_data = &dr344_at803x_data,
.platform_data = &dr34x_at803x_data,
},
};
static void __init dr344_setup(void)
static void __init dr34x_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 *mac = (u8 *) KSEG1ADDR(0x1f03f810);
ath79_register_m25p80(NULL);
ath79_gpio_direction_select(DR344_GPIO_LED_STATUS, true);
gpio_set_value(DR344_GPIO_LED_STATUS, 1);
ath79_gpio_output_select(DR344_GPIO_LED_STATUS, 0);
ath79_gpio_direction_select(DR344_GPIO_LED_LAN, true);
gpio_set_value(DR344_GPIO_LED_LAN, 1);
ath79_gpio_output_select(DR344_GPIO_LED_LAN, 0);
ath79_gpio_direction_select(DR34X_GPIO_LED_STATUS, true);
gpio_set_value(DR34X_GPIO_LED_STATUS, 1);
ath79_gpio_output_select(DR34X_GPIO_LED_STATUS, 0);
ath79_register_leds_gpio(-1, ARRAY_SIZE(dr344_leds_gpio),
dr344_leds_gpio);
ath79_register_gpio_keys_polled(-1, DR344_KEYS_POLL_INTERVAL,
ARRAY_SIZE(dr344_gpio_keys),
dr344_gpio_keys);
ARRAY_SIZE(dr34x_gpio_keys),
dr34x_gpio_keys);
ath79_register_usb();
ath79_wmac_set_ext_lna_gpio(0, DR344_GPIO_EXTERNAL_LNA0);
ath79_wmac_set_ext_lna_gpio(1, DR344_GPIO_EXTERNAL_LNA1);
ath79_register_wmac(art + DR344_WMAC_CALDATA_OFFSET, NULL);
ath79_register_wmac(art + DR34X_WMAC_CALDATA_OFFSET, NULL);
ath79_register_pci();
mdiobus_register_board_info(dr344_mdio0_info,
ARRAY_SIZE(dr344_mdio0_info));
mdiobus_register_board_info(dr34x_mdio0_info,
ARRAY_SIZE(dr34x_mdio0_info));
ath79_register_mdio(1, 0x0);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac + DR344_MAC0_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac + DR344_MAC1_OFFSET, 0);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
AR934X_ETH_CFG_SW_ONLY_MODE);
@ -167,13 +181,44 @@ static void __init dr344_setup(void)
ath79_eth0_pll_data.pll_100 = 0x0101;
ath79_eth0_pll_data.pll_10 = 0x1313;
ath79_init_mac(ath79_eth0_data.mac_addr, mac + DR34X_MAC0_OFFSET, 0);
ath79_register_eth(0);
}
static void __init dr342_setup(void)
{
dr34x_setup();
ath79_register_leds_gpio(-1, ARRAY_SIZE(dr342_leds_gpio),
dr342_leds_gpio);
}
static void __init dr344_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f03f810);
dr34x_setup();
ath79_gpio_direction_select(DR344_GPIO_LED_LAN, true);
gpio_set_value(DR344_GPIO_LED_LAN, 1);
ath79_gpio_output_select(DR344_GPIO_LED_LAN, 0);
ath79_register_leds_gpio(-1, ARRAY_SIZE(dr344_leds_gpio),
dr344_leds_gpio);
ath79_wmac_set_ext_lna_gpio(0, DR344_GPIO_EXTERNAL_LNA0);
ath79_wmac_set_ext_lna_gpio(1, DR344_GPIO_EXTERNAL_LNA1);
ath79_register_mdio(1, 0x0);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_register_eth(0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac + DR34X_MAC1_OFFSET, 0);
ath79_register_eth(1);
}
MIPS_MACHINE(ATH79_MACH_DR342, "DR342", "Wallys DR342", dr342_setup);
MIPS_MACHINE(ATH79_MACH_DR344, "DR344", "Wallys DR344", dr344_setup);

1
target/linux/ar71xx/files/arch/mips/ath79/machtypes.h
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@ -92,6 +92,7 @@ enum ath79_mach_type {
ATH79_MACH_DLAN_PRO_1200_AC, /* devolo dLAN pro 1200+ WiFi ac*/
ATH79_MACH_DLAN_PRO_500_WP, /* devolo dLAN pro 500 Wireless+ */
ATH79_MACH_DOMYWIFI_DW33D, /* DomyWifi DW33D */
ATH79_MACH_DR342, /* Wallys DR342 */
ATH79_MACH_DR344, /* Wallys DR344 */
ATH79_MACH_DR531, /* Wallys DR531 */
ATH79_MACH_DRAGINO2, /* Dragino Version 2 */

9
target/linux/ar71xx/image/generic.mk
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@ -349,6 +349,15 @@ define Device/mr16
endef
TARGET_DEVICES += mr12 mr16
define Device/dr342
DEVICE_TITLE := Wallys DR342
DEVICE_PACKAGES := kmod-usb-core kmod-usb2 -swconfig
BOARDNAME := DR342
IMAGE_SIZE := 16000k
MTDPARTS := spi0.0:192k(u-boot)ro,64k(u-boot-env),64k(partition-table)ro,16000k(firmware),64k(art)ro
endef
TARGET_DEVICES += dr342
define Device/dr344
DEVICE_TITLE := Wallys DR344
BOARDNAME := DR344

1
target/linux/ar71xx/mikrotik/config-default
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@ -59,6 +59,7 @@
# CONFIG_ATH79_MACH_DLAN_HOTSPOT is not set
# CONFIG_ATH79_MACH_DLAN_PRO_1200_AC is not set
# CONFIG_ATH79_MACH_DLAN_PRO_500_WP is not set
# CONFIG_ATH79_MACH_DR342 is not set
# CONFIG_ATH79_MACH_DR344 is not set
# CONFIG_ATH79_MACH_DR531 is not set
# CONFIG_ATH79_MACH_DRAGINO2 is not set

1
target/linux/ar71xx/nand/config-default
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@ -60,6 +60,7 @@ CONFIG_ATH79_MACH_C60=y
# CONFIG_ATH79_MACH_DLAN_PRO_1200_AC is not set
# CONFIG_ATH79_MACH_DLAN_PRO_500_WP is not set
CONFIG_ATH79_MACH_DOMYWIFI_DW33D=y
# CONFIG_ATH79_MACH_DR342 is not set
# CONFIG_ATH79_MACH_DR344 is not set
# CONFIG_ATH79_MACH_DR531 is not set
# CONFIG_ATH79_MACH_DRAGINO2 is not set

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