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@ -0,0 +1,808 @@
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--- a/drivers/mtd/devices/m25p80.c
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+++ b/drivers/mtd/devices/m25p80.c
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@@ -31,7 +31,6 @@
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struct m25p {
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struct spi_device *spi;
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struct spi_nor spi_nor;
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- struct mtd_info mtd;
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u8 command[MAX_CMD_SIZE];
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};
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@@ -62,8 +61,7 @@ static int m25p_cmdsz(struct spi_nor *no
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return 1 + nor->addr_width;
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}
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-static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
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- int wr_en)
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+static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
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{
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struct m25p *flash = nor->priv;
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struct spi_device *spi = flash->spi;
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@@ -159,7 +157,7 @@ static int m25p80_erase(struct spi_nor *
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struct m25p *flash = nor->priv;
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dev_dbg(nor->dev, "%dKiB at 0x%08x\n",
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- flash->mtd.erasesize / 1024, (u32)offset);
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+ flash->spi_nor.mtd.erasesize / 1024, (u32)offset);
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/* Set up command buffer. */
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flash->command[0] = nor->erase_opcode;
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@@ -201,11 +199,10 @@ static int m25p_probe(struct spi_device
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nor->read_reg = m25p80_read_reg;
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nor->dev = &spi->dev;
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- nor->mtd = &flash->mtd;
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+ nor->flash_node = spi->dev.of_node;
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nor->priv = flash;
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spi_set_drvdata(spi, flash);
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- flash->mtd.priv = nor;
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flash->spi = spi;
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if (spi->mode & SPI_RX_QUAD)
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@@ -214,7 +211,7 @@ static int m25p_probe(struct spi_device
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mode = SPI_NOR_DUAL;
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if (data && data->name)
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- flash->mtd.name = data->name;
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+ nor->mtd.name = data->name;
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/* For some (historical?) reason many platforms provide two different
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* names in flash_platform_data: "name" and "type". Quite often name is
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@@ -232,7 +229,7 @@ static int m25p_probe(struct spi_device
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ppdata.of_node = spi->dev.of_node;
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- return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
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+ return mtd_device_parse_register(&nor->mtd, NULL, &ppdata,
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data ? data->parts : NULL,
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data ? data->nr_parts : 0);
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}
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@@ -243,7 +240,7 @@ static int m25p_remove(struct spi_device
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struct m25p *flash = spi_get_drvdata(spi);
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/* Clean up MTD stuff. */
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- return mtd_device_unregister(&flash->mtd);
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+ return mtd_device_unregister(&flash->spi_nor.mtd);
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}
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/*
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@@ -304,7 +301,6 @@ MODULE_DEVICE_TABLE(of, m25p_of_table);
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static struct spi_driver m25p80_driver = {
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.driver = {
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.name = "m25p80",
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- .owner = THIS_MODULE,
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.of_match_table = m25p_of_table,
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},
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.id_table = m25p_ids,
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--- a/drivers/mtd/spi-nor/spi-nor.c
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+++ b/drivers/mtd/spi-nor/spi-nor.c
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@@ -16,15 +16,26 @@
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#include <linux/device.h>
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#include <linux/mutex.h>
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#include <linux/math64.h>
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+#include <linux/sizes.h>
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-#include <linux/mtd/cfi.h>
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#include <linux/mtd/mtd.h>
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#include <linux/of_platform.h>
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#include <linux/spi/flash.h>
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#include <linux/mtd/spi-nor.h>
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/* Define max times to check status register before we give up. */
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-#define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
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+
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+/*
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+ * For everything but full-chip erase; probably could be much smaller, but kept
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+ * around for safety for now
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+ */
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+#define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
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+
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+/*
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+ * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
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+ * for larger flash
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+ */
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+#define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
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#define SPI_NOR_MAX_ID_LEN 6
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@@ -145,7 +156,7 @@ static inline int spi_nor_read_dummy_cyc
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static inline int write_sr(struct spi_nor *nor, u8 val)
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{
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nor->cmd_buf[0] = val;
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- return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
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+ return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
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}
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/*
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@@ -154,7 +165,7 @@ static inline int write_sr(struct spi_no
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*/
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static inline int write_enable(struct spi_nor *nor)
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{
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- return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0);
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+ return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
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}
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/*
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@@ -162,7 +173,7 @@ static inline int write_enable(struct sp
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*/
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static inline int write_disable(struct spi_nor *nor)
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{
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- return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0, 0);
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+ return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
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}
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static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
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@@ -179,16 +190,16 @@ static inline int set_4byte(struct spi_n
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u8 cmd;
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switch (JEDEC_MFR(info)) {
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|
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- case CFI_MFR_ST: /* Micron, actually */
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+ case SNOR_MFR_MICRON:
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/* Some Micron need WREN command; all will accept it */
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|
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need_wren = true;
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- case CFI_MFR_MACRONIX:
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- case 0xEF /* winbond */:
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+ case SNOR_MFR_MACRONIX:
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+ case SNOR_MFR_WINBOND:
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|
|
if (need_wren)
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|
|
write_enable(nor);
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cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
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- status = nor->write_reg(nor, cmd, NULL, 0, 0);
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+ status = nor->write_reg(nor, cmd, NULL, 0);
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|
|
if (need_wren)
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|
|
write_disable(nor);
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|
@@ -196,7 +207,7 @@ static inline int set_4byte(struct spi_n
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default:
|
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|
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/* Spansion style */
|
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|
|
nor->cmd_buf[0] = enable << 7;
|
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|
|
|
- return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1, 0);
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|
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+ return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
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|
|
}
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|
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}
|
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|
static inline int spi_nor_sr_ready(struct spi_nor *nor)
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@@ -233,12 +244,13 @@ static int spi_nor_ready(struct spi_nor
|
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* Service routine to read status register until ready, or timeout occurs.
|
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|
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* Returns non-zero if error.
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*/
|
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-static int spi_nor_wait_till_ready(struct spi_nor *nor)
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+static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
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|
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+ unsigned long timeout_jiffies)
|
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|
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{
|
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|
|
unsigned long deadline;
|
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|
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int timeout = 0, ret;
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|
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- deadline = jiffies + MAX_READY_WAIT_JIFFIES;
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+ deadline = jiffies + timeout_jiffies;
|
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|
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|
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while (!timeout) {
|
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|
|
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if (time_after_eq(jiffies, deadline))
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@@ -258,6 +270,12 @@ static int spi_nor_wait_till_ready(struc
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|
|
return -ETIMEDOUT;
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|
|
}
|
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|
|
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|
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+static int spi_nor_wait_till_ready(struct spi_nor *nor)
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+{
|
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|
|
+ return spi_nor_wait_till_ready_with_timeout(nor,
|
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|
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+ DEFAULT_READY_WAIT_JIFFIES);
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+}
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+
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|
|
/*
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|
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* Erase the whole flash memory
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*
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@@ -265,9 +283,9 @@ static int spi_nor_wait_till_ready(struc
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*/
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static int erase_chip(struct spi_nor *nor)
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{
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|
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- dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd->size >> 10));
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+ dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
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- return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0, 0);
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+ return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0);
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}
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|
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static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
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@@ -321,6 +339,8 @@ static int spi_nor_erase(struct mtd_info
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/* whole-chip erase? */
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if (len == mtd->size) {
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+ unsigned long timeout;
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+
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write_enable(nor);
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if (erase_chip(nor)) {
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@@ -328,7 +348,16 @@ static int spi_nor_erase(struct mtd_info
|
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|
|
goto erase_err;
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|
}
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|
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- ret = spi_nor_wait_till_ready(nor);
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|
|
+ /*
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|
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+ * Scale the timeout linearly with the size of the flash, with
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+ * a minimum calibrated to an old 2MB flash. We could try to
|
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|
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+ * pull these from CFI/SFDP, but these values should be good
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|
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+ * enough for now.
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+ */
|
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|
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+ timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
|
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|
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+ CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
|
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|
|
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+ (unsigned long)(mtd->size / SZ_2M));
|
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|
|
+ ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
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|
|
|
if (ret)
|
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|
|
|
goto erase_err;
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|
@@ -371,72 +400,171 @@ erase_err:
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|
|
return ret;
|
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|
|
|
}
|
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|
|
|
|
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|
|
+static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
|
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|
|
+ uint64_t *len)
|
|
|
|
|
+{
|
|
|
|
|
+ struct mtd_info *mtd = &nor->mtd;
|
|
|
|
|
+ u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
|
|
|
|
|
+ int shift = ffs(mask) - 1;
|
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|
|
|
+ int pow;
|
|
|
|
|
+
|
|
|
|
|
+ if (!(sr & mask)) {
|
|
|
|
|
+ /* No protection */
|
|
|
|
|
+ *ofs = 0;
|
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|
|
|
+ *len = 0;
|
|
|
|
|
+ } else {
|
|
|
|
|
+ pow = ((sr & mask) ^ mask) >> shift;
|
|
|
|
|
+ *len = mtd->size >> pow;
|
|
|
|
|
+ *ofs = mtd->size - *len;
|
|
|
|
|
+ }
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
+/*
|
|
|
|
|
+ * Return 1 if the entire region is locked, 0 otherwise
|
|
|
|
|
+ */
|
|
|
|
|
+static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
|
|
|
|
|
+ u8 sr)
|
|
|
|
|
+{
|
|
|
|
|
+ loff_t lock_offs;
|
|
|
|
|
+ uint64_t lock_len;
|
|
|
|
|
+
|
|
|
|
|
+ stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
|
|
|
|
|
+
|
|
|
|
|
+ return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
+/*
|
|
|
|
|
+ * Lock a region of the flash. Compatible with ST Micro and similar flash.
|
|
|
|
|
+ * Supports only the block protection bits BP{0,1,2} in the status register
|
|
|
|
|
+ * (SR). Does not support these features found in newer SR bitfields:
|
|
|
|
|
+ * - TB: top/bottom protect - only handle TB=0 (top protect)
|
|
|
|
|
+ * - SEC: sector/block protect - only handle SEC=0 (block protect)
|
|
|
|
|
+ * - CMP: complement protect - only support CMP=0 (range is not complemented)
|
|
|
|
|
+ *
|
|
|
|
|
+ * Sample table portion for 8MB flash (Winbond w25q64fw):
|
|
|
|
|
+ *
|
|
|
|
|
+ * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
|
|
|
|
|
+ * --------------------------------------------------------------------------
|
|
|
|
|
+ * X | X | 0 | 0 | 0 | NONE | NONE
|
|
|
|
|
+ * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
|
|
|
|
|
+ * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
|
|
|
|
|
+ * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
|
|
|
|
|
+ * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
|
|
|
|
|
+ * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
|
|
|
|
|
+ * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
|
|
|
|
|
+ * X | X | 1 | 1 | 1 | 8 MB | ALL
|
|
|
|
|
+ *
|
|
|
|
|
+ * Returns negative on errors, 0 on success.
|
|
|
|
|
+ */
|
|
|
|
|
static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
|
|
|
|
|
{
|
|
|
|
|
- struct mtd_info *mtd = nor->mtd;
|
|
|
|
|
- uint32_t offset = ofs;
|
|
|
|
|
- uint8_t status_old, status_new;
|
|
|
|
|
- int ret = 0;
|
|
|
|
|
+ struct mtd_info *mtd = &nor->mtd;
|
|
|
|
|
+ u8 status_old, status_new;
|
|
|
|
|
+ u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
|
|
|
|
|
+ u8 shift = ffs(mask) - 1, pow, val;
|
|
|
|
|
|
|
|
|
|
status_old = read_sr(nor);
|
|
|
|
|
|
|
|
|
|
- if (offset < mtd->size - (mtd->size / 2))
|
|
|
|
|
- status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0;
|
|
|
|
|
- else if (offset < mtd->size - (mtd->size / 4))
|
|
|
|
|
- status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
|
|
|
|
|
- else if (offset < mtd->size - (mtd->size / 8))
|
|
|
|
|
- status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
|
|
|
|
|
- else if (offset < mtd->size - (mtd->size / 16))
|
|
|
|
|
- status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2;
|
|
|
|
|
- else if (offset < mtd->size - (mtd->size / 32))
|
|
|
|
|
- status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
|
|
|
|
|
- else if (offset < mtd->size - (mtd->size / 64))
|
|
|
|
|
- status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1;
|
|
|
|
|
- else
|
|
|
|
|
- status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0;
|
|
|
|
|
+ /* SPI NOR always locks to the end */
|
|
|
|
|
+ if (ofs + len != mtd->size) {
|
|
|
|
|
+ /* Does combined region extend to end? */
|
|
|
|
|
+ if (!stm_is_locked_sr(nor, ofs + len, mtd->size - ofs - len,
|
|
|
|
|
+ status_old))
|
|
|
|
|
+ return -EINVAL;
|
|
|
|
|
+ len = mtd->size - ofs;
|
|
|
|
|
+ }
|
|
|
|
|
+
|
|
|
|
|
+ /*
|
|
|
|
|
+ * Need smallest pow such that:
|
|
|
|
|
+ *
|
|
|
|
|
+ * 1 / (2^pow) <= (len / size)
|
|
|
|
|
+ *
|
|
|
|
|
+ * so (assuming power-of-2 size) we do:
|
|
|
|
|
+ *
|
|
|
|
|
+ * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
|
|
|
|
|
+ */
|
|
|
|
|
+ pow = ilog2(mtd->size) - ilog2(len);
|
|
|
|
|
+ val = mask - (pow << shift);
|
|
|
|
|
+ if (val & ~mask)
|
|
|
|
|
+ return -EINVAL;
|
|
|
|
|
+ /* Don't "lock" with no region! */
|
|
|
|
|
+ if (!(val & mask))
|
|
|
|
|
+ return -EINVAL;
|
|
|
|
|
+
|
|
|
|
|
+ status_new = (status_old & ~mask) | val;
|
|
|
|
|
|
|
|
|
|
/* Only modify protection if it will not unlock other areas */
|
|
|
|
|
- if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) >
|
|
|
|
|
- (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) {
|
|
|
|
|
- write_enable(nor);
|
|
|
|
|
- ret = write_sr(nor, status_new);
|
|
|
|
|
- }
|
|
|
|
|
+ if ((status_new & mask) <= (status_old & mask))
|
|
|
|
|
+ return -EINVAL;
|
|
|
|
|
|
|
|
|
|
- return ret;
|
|
|
|
|
+ write_enable(nor);
|
|
|
|
|
+ return write_sr(nor, status_new);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
+/*
|
|
|
|
|
+ * Unlock a region of the flash. See stm_lock() for more info
|
|
|
|
|
+ *
|
|
|
|
|
+ * Returns negative on errors, 0 on success.
|
|
|
|
|
+ */
|
|
|
|
|
static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
|
|
|
|
|
{
|
|
|
|
|
- struct mtd_info *mtd = nor->mtd;
|
|
|
|
|
- uint32_t offset = ofs;
|
|
|
|
|
+ struct mtd_info *mtd = &nor->mtd;
|
|
|
|
|
uint8_t status_old, status_new;
|
|
|
|
|
- int ret = 0;
|
|
|
|
|
+ u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
|
|
|
|
|
+ u8 shift = ffs(mask) - 1, pow, val;
|
|
|
|
|
|
|
|
|
|
status_old = read_sr(nor);
|
|
|
|
|
|
|
|
|
|
- if (offset+len > mtd->size - (mtd->size / 64))
|
|
|
|
|
- status_new = status_old & ~(SR_BP2 | SR_BP1 | SR_BP0);
|
|
|
|
|
- else if (offset+len > mtd->size - (mtd->size / 32))
|
|
|
|
|
- status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0;
|
|
|
|
|
- else if (offset+len > mtd->size - (mtd->size / 16))
|
|
|
|
|
- status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1;
|
|
|
|
|
- else if (offset+len > mtd->size - (mtd->size / 8))
|
|
|
|
|
- status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
|
|
|
|
|
- else if (offset+len > mtd->size - (mtd->size / 4))
|
|
|
|
|
- status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2;
|
|
|
|
|
- else if (offset+len > mtd->size - (mtd->size / 2))
|
|
|
|
|
- status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
|
|
|
|
|
- else
|
|
|
|
|
- status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
|
|
|
|
|
+ /* Cannot unlock; would unlock larger region than requested */
|
|
|
|
|
+ if (stm_is_locked_sr(nor, status_old, ofs - mtd->erasesize,
|
|
|
|
|
+ mtd->erasesize))
|
|
|
|
|
+ return -EINVAL;
|
|
|
|
|
|
|
|
|
|
- /* Only modify protection if it will not lock other areas */
|
|
|
|
|
- if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) <
|
|
|
|
|
- (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) {
|
|
|
|
|
- write_enable(nor);
|
|
|
|
|
- ret = write_sr(nor, status_new);
|
|
|
|
|
+ /*
|
|
|
|
|
+ * Need largest pow such that:
|
|
|
|
|
+ *
|
|
|
|
|
+ * 1 / (2^pow) >= (len / size)
|
|
|
|
|
+ *
|
|
|
|
|
+ * so (assuming power-of-2 size) we do:
|
|
|
|
|
+ *
|
|
|
|
|
+ * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
|
|
|
|
|
+ */
|
|
|
|
|
+ pow = ilog2(mtd->size) - order_base_2(mtd->size - (ofs + len));
|
|
|
|
|
+ if (ofs + len == mtd->size) {
|
|
|
|
|
+ val = 0; /* fully unlocked */
|
|
|
|
|
+ } else {
|
|
|
|
|
+ val = mask - (pow << shift);
|
|
|
|
|
+ /* Some power-of-two sizes are not supported */
|
|
|
|
|
+ if (val & ~mask)
|
|
|
|
|
+ return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
- return ret;
|
|
|
|
|
+ status_new = (status_old & ~mask) | val;
|
|
|
|
|
+
|
|
|
|
|
+ /* Only modify protection if it will not lock other areas */
|
|
|
|
|
+ if ((status_new & mask) >= (status_old & mask))
|
|
|
|
|
+ return -EINVAL;
|
|
|
|
|
+
|
|
|
|
|
+ write_enable(nor);
|
|
|
|
|
+ return write_sr(nor, status_new);
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
+/*
|
|
|
|
|
+ * Check if a region of the flash is (completely) locked. See stm_lock() for
|
|
|
|
|
+ * more info.
|
|
|
|
|
+ *
|
|
|
|
|
+ * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
|
|
|
|
|
+ * negative on errors.
|
|
|
|
|
+ */
|
|
|
|
|
+static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
|
|
|
|
|
+{
|
|
|
|
|
+ int status;
|
|
|
|
|
+
|
|
|
|
|
+ status = read_sr(nor);
|
|
|
|
|
+ if (status < 0)
|
|
|
|
|
+ return status;
|
|
|
|
|
+
|
|
|
|
|
+ return stm_is_locked_sr(nor, ofs, len, status);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
|
|
|
|
|
@@ -469,6 +597,21 @@ static int spi_nor_unlock(struct mtd_inf
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
+static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
|
|
|
|
|
+{
|
|
|
|
|
+ struct spi_nor *nor = mtd_to_spi_nor(mtd);
|
|
|
|
|
+ int ret;
|
|
|
|
|
+
|
|
|
|
|
+ ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
|
|
|
|
|
+ if (ret)
|
|
|
|
|
+ return ret;
|
|
|
|
|
+
|
|
|
|
|
+ ret = nor->flash_is_locked(nor, ofs, len);
|
|
|
|
|
+
|
|
|
|
|
+ spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
|
|
|
|
|
+ return ret;
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
/* Used when the "_ext_id" is two bytes at most */
|
|
|
|
|
#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
|
|
|
|
|
.id = { \
|
|
|
|
|
@@ -585,6 +728,7 @@ static const struct flash_info spi_nor_i
|
|
|
|
|
|
|
|
|
|
/* Micron */
|
|
|
|
|
{ "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
|
|
|
|
|
+ { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
|
|
|
|
|
{ "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
|
|
|
|
|
{ "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
|
|
|
|
|
{ "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) },
|
|
|
|
|
@@ -618,12 +762,13 @@ static const struct flash_info spi_nor_i
|
|
|
|
|
{ "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
|
|
|
|
|
{ "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
|
|
|
|
|
{ "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
|
|
|
|
|
- { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
|
|
|
|
|
- { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) },
|
|
|
|
|
+ { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
|
|
|
|
+ { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
|
|
|
|
+ { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
|
|
|
|
{ "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
|
|
|
|
|
{ "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) },
|
|
|
|
|
{ "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
|
|
|
|
|
- { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K) },
|
|
|
|
|
+ { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ) },
|
|
|
|
|
|
|
|
|
|
/* SST -- large erase sizes are "overlays", "sectors" are 4K */
|
|
|
|
|
{ "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
|
|
|
|
|
@@ -635,6 +780,7 @@ static const struct flash_info spi_nor_i
|
|
|
|
|
{ "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
|
|
|
|
|
{ "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
|
|
|
|
|
{ "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) },
|
|
|
|
|
+ { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) },
|
|
|
|
|
{ "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
|
|
|
|
|
{ "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
|
|
|
|
|
|
|
|
|
|
@@ -683,10 +829,11 @@ static const struct flash_info spi_nor_i
|
|
|
|
|
{ "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
|
|
|
|
|
{ "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
|
|
|
|
|
{ "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
|
|
|
|
|
- { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) },
|
|
|
|
|
+ { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
|
|
|
|
{ "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
|
|
|
|
|
{ "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
|
|
|
|
|
- { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, SECT_4K) },
|
|
|
|
|
+ { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
|
|
|
|
+ { "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
|
|
|
|
{ "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
|
|
|
|
|
{ "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
|
|
|
|
|
{ "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
|
|
|
|
|
@@ -868,8 +1015,7 @@ static int macronix_quad_enable(struct s
|
|
|
|
|
val = read_sr(nor);
|
|
|
|
|
write_enable(nor);
|
|
|
|
|
|
|
|
|
|
- nor->cmd_buf[0] = val | SR_QUAD_EN_MX;
|
|
|
|
|
- nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
|
|
|
|
|
+ write_sr(nor, val | SR_QUAD_EN_MX);
|
|
|
|
|
|
|
|
|
|
if (spi_nor_wait_till_ready(nor))
|
|
|
|
|
return 1;
|
|
|
|
|
@@ -894,7 +1040,7 @@ static int write_sr_cr(struct spi_nor *n
|
|
|
|
|
nor->cmd_buf[0] = val & 0xff;
|
|
|
|
|
nor->cmd_buf[1] = (val >> 8);
|
|
|
|
|
|
|
|
|
|
- return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2, 0);
|
|
|
|
|
+ return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int spansion_quad_enable(struct spi_nor *nor)
|
|
|
|
|
@@ -936,7 +1082,7 @@ static int micron_quad_enable(struct spi
|
|
|
|
|
|
|
|
|
|
/* set EVCR, enable quad I/O */
|
|
|
|
|
nor->cmd_buf[0] = val & ~EVCR_QUAD_EN_MICRON;
|
|
|
|
|
- ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1, 0);
|
|
|
|
|
+ ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1);
|
|
|
|
|
if (ret < 0) {
|
|
|
|
|
dev_err(nor->dev, "error while writing EVCR register\n");
|
|
|
|
|
return ret;
|
|
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@@ -965,14 +1111,14 @@ static int set_quad_mode(struct spi_nor
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int status;
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switch (JEDEC_MFR(info)) {
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- case CFI_MFR_MACRONIX:
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+ case SNOR_MFR_MACRONIX:
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status = macronix_quad_enable(nor);
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if (status) {
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dev_err(nor->dev, "Macronix quad-read not enabled\n");
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return -EINVAL;
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}
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return status;
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- case CFI_MFR_ST:
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+ case SNOR_MFR_MICRON:
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status = micron_quad_enable(nor);
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if (status) {
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dev_err(nor->dev, "Micron quad-read not enabled\n");
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@@ -1004,8 +1150,8 @@ int spi_nor_scan(struct spi_nor *nor, co
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{
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const struct flash_info *info = NULL;
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struct device *dev = nor->dev;
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- struct mtd_info *mtd = nor->mtd;
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- struct device_node *np = dev->of_node;
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+ struct mtd_info *mtd = &nor->mtd;
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+ struct device_node *np = nor->flash_node;
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int ret;
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int i;
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@@ -1048,19 +1194,21 @@ int spi_nor_scan(struct spi_nor *nor, co
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mutex_init(&nor->lock);
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/*
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- * Atmel, SST and Intel/Numonyx serial nor tend to power
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- * up with the software protection bits set
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+ * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
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+ * with the software protection bits set
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*/
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- if (JEDEC_MFR(info) == CFI_MFR_ATMEL ||
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- JEDEC_MFR(info) == CFI_MFR_INTEL ||
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- JEDEC_MFR(info) == CFI_MFR_SST) {
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+ if (JEDEC_MFR(info) == SNOR_MFR_ATMEL ||
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+ JEDEC_MFR(info) == SNOR_MFR_INTEL ||
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+ JEDEC_MFR(info) == SNOR_MFR_SST ||
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+ JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
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write_enable(nor);
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write_sr(nor, 0);
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}
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if (!mtd->name)
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mtd->name = dev_name(dev);
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+ mtd->priv = nor;
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mtd->type = MTD_NORFLASH;
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mtd->writesize = 1;
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mtd->flags = MTD_CAP_NORFLASH;
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@@ -1068,15 +1216,18 @@ int spi_nor_scan(struct spi_nor *nor, co
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mtd->_erase = spi_nor_erase;
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mtd->_read = spi_nor_read;
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- /* nor protection support for STmicro chips */
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- if (JEDEC_MFR(info) == CFI_MFR_ST) {
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+ /* NOR protection support for STmicro/Micron chips and similar */
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+ if (JEDEC_MFR(info) == SNOR_MFR_MICRON ||
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+ JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
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nor->flash_lock = stm_lock;
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nor->flash_unlock = stm_unlock;
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+ nor->flash_is_locked = stm_is_locked;
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}
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- if (nor->flash_lock && nor->flash_unlock) {
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+ if (nor->flash_lock && nor->flash_unlock && nor->flash_is_locked) {
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mtd->_lock = spi_nor_lock;
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mtd->_unlock = spi_nor_unlock;
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+ mtd->_is_locked = spi_nor_is_locked;
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}
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/* sst nor chips use AAI word program */
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@@ -1163,7 +1314,7 @@ int spi_nor_scan(struct spi_nor *nor, co
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else if (mtd->size > 0x1000000) {
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/* enable 4-byte addressing if the device exceeds 16MiB */
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nor->addr_width = 4;
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- if (JEDEC_MFR(info) == CFI_MFR_AMD) {
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+ if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) {
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/* Dedicated 4-byte command set */
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switch (nor->flash_read) {
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case SPI_NOR_QUAD:
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--- a/include/linux/mtd/spi-nor.h
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+++ b/include/linux/mtd/spi-nor.h
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@@ -10,6 +10,23 @@
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#ifndef __LINUX_MTD_SPI_NOR_H
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#define __LINUX_MTD_SPI_NOR_H
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+#include <linux/bitops.h>
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+#include <linux/mtd/cfi.h>
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+
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+/*
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+ * Manufacturer IDs
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+ *
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+ * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
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+ * Sometimes these are the same as CFI IDs, but sometimes they aren't.
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+ */
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+#define SNOR_MFR_ATMEL CFI_MFR_ATMEL
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+#define SNOR_MFR_INTEL CFI_MFR_INTEL
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+#define SNOR_MFR_MICRON CFI_MFR_ST /* ST Micro <--> Micron */
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+#define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
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+#define SNOR_MFR_SPANSION CFI_MFR_AMD
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+#define SNOR_MFR_SST CFI_MFR_SST
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+#define SNOR_MFR_WINBOND 0xef
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+
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/*
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* Note on opcode nomenclature: some opcodes have a format like
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* SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
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@@ -61,24 +78,24 @@
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#define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
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/* Status Register bits. */
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-#define SR_WIP 1 /* Write in progress */
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-#define SR_WEL 2 /* Write enable latch */
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+#define SR_WIP BIT(0) /* Write in progress */
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+#define SR_WEL BIT(1) /* Write enable latch */
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/* meaning of other SR_* bits may differ between vendors */
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-#define SR_BP0 4 /* Block protect 0 */
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-#define SR_BP1 8 /* Block protect 1 */
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-#define SR_BP2 0x10 /* Block protect 2 */
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-#define SR_SRWD 0x80 /* SR write protect */
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+#define SR_BP0 BIT(2) /* Block protect 0 */
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+#define SR_BP1 BIT(3) /* Block protect 1 */
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+#define SR_BP2 BIT(4) /* Block protect 2 */
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+#define SR_SRWD BIT(7) /* SR write protect */
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-#define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */
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+#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
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/* Enhanced Volatile Configuration Register bits */
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-#define EVCR_QUAD_EN_MICRON 0x80 /* Micron Quad I/O */
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+#define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
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/* Flag Status Register bits */
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-#define FSR_READY 0x80
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+#define FSR_READY BIT(7)
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/* Configuration Register bits. */
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-#define CR_QUAD_EN_SPAN 0x2 /* Spansion Quad I/O */
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+#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
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enum read_mode {
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SPI_NOR_NORMAL = 0,
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@@ -87,33 +104,6 @@ enum read_mode {
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SPI_NOR_QUAD,
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};
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-/**
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- * struct spi_nor_xfer_cfg - Structure for defining a Serial Flash transfer
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- * @wren: command for "Write Enable", or 0x00 for not required
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- * @cmd: command for operation
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- * @cmd_pins: number of pins to send @cmd (1, 2, 4)
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- * @addr: address for operation
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- * @addr_pins: number of pins to send @addr (1, 2, 4)
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- * @addr_width: number of address bytes
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- * (3,4, or 0 for address not required)
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- * @mode: mode data
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- * @mode_pins: number of pins to send @mode (1, 2, 4)
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- * @mode_cycles: number of mode cycles (0 for mode not required)
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- * @dummy_cycles: number of dummy cycles (0 for dummy not required)
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- */
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-struct spi_nor_xfer_cfg {
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- u8 wren;
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- u8 cmd;
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- u8 cmd_pins;
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- u32 addr;
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- u8 addr_pins;
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- u8 addr_width;
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- u8 mode;
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- u8 mode_pins;
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- u8 mode_cycles;
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- u8 dummy_cycles;
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-};
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-
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#define SPI_NOR_MAX_CMD_SIZE 8
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enum spi_nor_ops {
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SPI_NOR_OPS_READ = 0,
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@@ -127,11 +117,14 @@ enum spi_nor_option_flags {
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SNOR_F_USE_FSR = BIT(0),
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};
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+struct mtd_info;
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+
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/**
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* struct spi_nor - Structure for defining a the SPI NOR layer
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* @mtd: point to a mtd_info structure
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* @lock: the lock for the read/write/erase/lock/unlock operations
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* @dev: point to a spi device, or a spi nor controller device.
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+ * @flash_node: point to a device node describing this flash instance.
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* @page_size: the page size of the SPI NOR
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* @addr_width: number of address bytes
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* @erase_opcode: the opcode for erasing a sector
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@@ -141,28 +134,28 @@ enum spi_nor_option_flags {
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* @flash_read: the mode of the read
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* @sst_write_second: used by the SST write operation
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* @flags: flag options for the current SPI-NOR (SNOR_F_*)
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- * @cfg: used by the read_xfer/write_xfer
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* @cmd_buf: used by the write_reg
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* @prepare: [OPTIONAL] do some preparations for the
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* read/write/erase/lock/unlock operations
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* @unprepare: [OPTIONAL] do some post work after the
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* read/write/erase/lock/unlock operations
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- * @read_xfer: [OPTIONAL] the read fundamental primitive
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- * @write_xfer: [OPTIONAL] the writefundamental primitive
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* @read_reg: [DRIVER-SPECIFIC] read out the register
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* @write_reg: [DRIVER-SPECIFIC] write data to the register
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* @read: [DRIVER-SPECIFIC] read data from the SPI NOR
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* @write: [DRIVER-SPECIFIC] write data to the SPI NOR
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* @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
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* at the offset @offs
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- * @lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
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- * @unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
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+ * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
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+ * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
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+ * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is
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+ * completely locked
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* @priv: the private data
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*/
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struct spi_nor {
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- struct mtd_info *mtd;
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+ struct mtd_info mtd;
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struct mutex lock;
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struct device *dev;
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+ struct device_node *flash_node;
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u32 page_size;
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u8 addr_width;
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u8 erase_opcode;
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@@ -172,18 +165,12 @@ struct spi_nor {
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enum read_mode flash_read;
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bool sst_write_second;
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u32 flags;
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- struct spi_nor_xfer_cfg cfg;
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u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
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int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
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void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
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- int (*read_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg,
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- u8 *buf, size_t len);
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- int (*write_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg,
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- u8 *buf, size_t len);
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int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
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- int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
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- int write_enable);
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+ int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
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int (*read)(struct spi_nor *nor, loff_t from,
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size_t len, size_t *retlen, u_char *read_buf);
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@@ -193,6 +180,7 @@ struct spi_nor {
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int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
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int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
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+ int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
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void *priv;
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};
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Felix Fietkau
9 years ago