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@ -35,7 +35,7 @@
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readl(mbox);
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}
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@@ -943,7 +946,7 @@ static void tg3_switch_clocks(struct tg3
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@@ -948,7 +951,7 @@ static void tg3_switch_clocks(struct tg3
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#define PHY_BUSY_LOOPS 5000
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@ -44,7 +44,7 @@
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{
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u32 frame_val;
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unsigned int loops;
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@@ -957,7 +960,7 @@ static int tg3_readphy(struct tg3 *tp, i
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@@ -962,7 +965,7 @@ static int tg3_readphy(struct tg3 *tp, i
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*val = 0x0;
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@ -53,7 +53,7 @@
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MI_COM_PHY_ADDR_MASK);
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frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
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MI_COM_REG_ADDR_MASK);
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@@ -992,7 +995,12 @@ static int tg3_readphy(struct tg3 *tp, i
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@@ -997,7 +1000,12 @@ static int tg3_readphy(struct tg3 *tp, i
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return ret;
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}
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@ -67,7 +67,7 @@
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{
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u32 frame_val;
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unsigned int loops;
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@@ -1008,7 +1016,7 @@ static int tg3_writephy(struct tg3 *tp,
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@@ -1013,7 +1021,7 @@ static int tg3_writephy(struct tg3 *tp,
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udelay(80);
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}
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@ -76,7 +76,7 @@
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MI_COM_PHY_ADDR_MASK);
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frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
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MI_COM_REG_ADDR_MASK);
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@@ -1041,6 +1049,11 @@ static int tg3_writephy(struct tg3 *tp,
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@@ -1046,6 +1054,11 @@ static int tg3_writephy(struct tg3 *tp,
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return ret;
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}
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@ -88,7 +88,7 @@
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static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
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{
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int err;
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@@ -1603,6 +1616,11 @@ static int tg3_poll_fw(struct tg3 *tp)
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@@ -1608,6 +1621,11 @@ static int tg3_poll_fw(struct tg3 *tp)
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int i;
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u32 val;
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@ -100,7 +100,7 @@
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
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/* Wait up to 20ms for init done. */
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for (i = 0; i < 200; i++) {
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@@ -3024,9 +3042,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
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@@ -3029,9 +3047,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
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return -ENODEV;
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}
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@ -116,7 +116,7 @@
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return 0;
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}
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@@ -3089,6 +3110,11 @@ static int tg3_load_5701_a0_firmware_fix
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@@ -3094,6 +3115,11 @@ static int tg3_load_5701_a0_firmware_fix
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const __be32 *fw_data;
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int err, i;
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@ -128,7 +128,7 @@
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fw_data = (void *)tp->fw->data;
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/* Firmware blob starts with version numbers, followed by
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@@ -3145,6 +3171,11 @@ static int tg3_load_tso_firmware(struct
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@@ -3150,6 +3176,11 @@ static int tg3_load_tso_firmware(struct
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unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
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int err, i;
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@ -140,7 +140,7 @@
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if (tg3_flag(tp, HW_TSO_1) ||
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tg3_flag(tp, HW_TSO_2) ||
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tg3_flag(tp, HW_TSO_3))
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@@ -3491,8 +3522,11 @@ static int tg3_power_down_prepare(struct
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@@ -3496,8 +3527,11 @@ static int tg3_power_down_prepare(struct
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tg3_frob_aux_power(tp, true);
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/* Workaround for unstable PLL clock */
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@ -154,7 +154,7 @@
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u32 val = tr32(0x7d00);
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val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
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@@ -4006,6 +4040,14 @@ relink:
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@@ -4011,6 +4045,14 @@ relink:
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if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
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tg3_phy_copper_begin(tp);
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@ -169,7 +169,7 @@
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tg3_readphy(tp, MII_BMSR, &bmsr);
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if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
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(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
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@@ -7819,6 +7861,14 @@ static int tg3_chip_reset(struct tg3 *tp
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@@ -7833,6 +7875,14 @@ static int tg3_chip_reset(struct tg3 *tp
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tw32(0x5000, 0x400);
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}
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@ -184,7 +184,7 @@
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tw32(GRC_MODE, tp->grc_mode);
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if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
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@@ -9233,6 +9283,11 @@ static void tg3_timer(unsigned long __op
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@@ -9247,6 +9297,11 @@ static void tg3_timer(unsigned long __op
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tg3_flag(tp, 57765_CLASS))
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|
tg3_chk_missed_msi(tp);
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@ -196,7 +196,7 @@
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|
if (!tg3_flag(tp, TAGGED_STATUS)) {
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|
/* All of this garbage is because when using non-tagged
|
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|
|
* IRQ status the mailbox/status_block protocol the chip
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|
@@ -10945,6 +11000,11 @@ static int tg3_test_nvram(struct tg3 *tp
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@@ -10959,6 +11014,11 @@ static int tg3_test_nvram(struct tg3 *tp
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|
|
if (tg3_flag(tp, NO_NVRAM))
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|
return 0;
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|
@ -208,7 +208,7 @@
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|
|
if (tg3_nvram_read(tp, 0, &magic) != 0)
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|
|
return -EIO;
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|
@@ -11902,11 +11962,11 @@ static int tg3_ioctl(struct net_device *
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@@ -11916,11 +11976,11 @@ static int tg3_ioctl(struct net_device *
|
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|
|
if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
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|
|
break; /* We have no PHY */
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|
@ -222,7 +222,7 @@
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|
|
spin_unlock_bh(&tp->lock);
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|
|
data->val_out = mii_regval;
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|
|
@@ -11918,11 +11978,11 @@ static int tg3_ioctl(struct net_device *
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|
@@ -11932,11 +11992,11 @@ static int tg3_ioctl(struct net_device *
|
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|
|
if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
|
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|
|
break; /* We have no PHY */
|
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|
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|
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|
|
@ -236,7 +236,7 @@
|
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|
|
|
spin_unlock_bh(&tp->lock);
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|
|
|
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|
|
|
|
return err;
|
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|
|
@@ -12656,6 +12716,13 @@ static void __devinit tg3_get_5720_nvram
|
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|
|
@@ -12670,6 +12730,13 @@ static void __devinit tg3_get_5720_nvram
|
|
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|
|
/* Chips other than 5700/5701 use the NVRAM for fetching info. */
|
|
|
|
|
static void __devinit tg3_nvram_init(struct tg3 *tp)
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|
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|
|
{
|
|
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|
|
@ -250,7 +250,7 @@
|
|
|
|
|
tw32_f(GRC_EEPROM_ADDR,
|
|
|
|
|
(EEPROM_ADDR_FSM_RESET |
|
|
|
|
|
(EEPROM_DEFAULT_CLOCK_PERIOD <<
|
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|
|
@@ -12922,6 +12989,9 @@ static int tg3_nvram_write_block(struct
|
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|
@@ -12936,6 +13003,9 @@ static int tg3_nvram_write_block(struct
|
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|
|
{
|
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|
|
int ret;
|
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|
|
@ -260,7 +260,7 @@
|
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|
|
|
if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
|
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|
|
|
tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
|
|
|
|
|
~GRC_LCLCTRL_GPIO_OUTPUT1);
|
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|
@@ -14368,6 +14438,11 @@ static int __devinit tg3_get_invariants(
|
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|
@@ -14382,6 +14452,11 @@ static int __devinit tg3_get_invariants(
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|
|
}
|
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|
|
}
|
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|
@ -272,7 +272,7 @@
|
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|
|
/* Get eeprom hw config before calling tg3_set_power_state().
|
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|
|
|
* In particular, the TG3_FLAG_IS_NIC flag must be
|
|
|
|
|
* determined before calling tg3_set_power_state() so that
|
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|
|
@@ -14784,6 +14859,10 @@ static int __devinit tg3_get_device_addr
|
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|
|
@@ -14798,6 +14873,10 @@ static int __devinit tg3_get_device_addr
|
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|
|
}
|
|
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|
|
|
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|
|
if (!is_valid_ether_addr(&dev->dev_addr[0])) {
|
|
|
|
|
@ -283,7 +283,7 @@
|
|
|
|
|
#ifdef CONFIG_SPARC
|
|
|
|
|
if (!tg3_get_default_macaddr_sparc(tp))
|
|
|
|
|
return 0;
|
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|
|
|
@@ -15282,6 +15361,8 @@ static char * __devinit tg3_phy_string(s
|
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|
@@ -15296,6 +15375,8 @@ static char * __devinit tg3_phy_string(s
|
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|
|
case TG3_PHY_ID_BCM5704: return "5704";
|
|
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|
|
case TG3_PHY_ID_BCM5705: return "5705";
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|
|
case TG3_PHY_ID_BCM5750: return "5750";
|
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|
|
@ -292,7 +292,7 @@
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|
|
case TG3_PHY_ID_BCM5752: return "5752";
|
|
|
|
|
case TG3_PHY_ID_BCM5714: return "5714";
|
|
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|
|
case TG3_PHY_ID_BCM5780: return "5780";
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|
|
@@ -15492,6 +15573,13 @@ static int __devinit tg3_init_one(struct
|
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|
|
@@ -15506,6 +15587,13 @@ static int __devinit tg3_init_one(struct
|
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|
|
tp->msg_enable = tg3_debug;
|
|
|
|
|
else
|
|
|
|
|
tp->msg_enable = TG3_DEF_MSG_ENABLE;
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Gabor Juhos
12 years ago