ramips: split mt7621 spi into a separate driver, increase maximum transfer size
Signed-off-by: Felix Fietkau <nbd@openwrt.org> SVN-Revision: 43807v19.07.3_mercusys_ac12_duma
Felix Fietkau
10 years ago
parent
cc5f89c66a
commit
aefd3c569c
@ -1,346 +0,0 @@
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From 27b11d4f1888e1a3d6d75b46d4d5a4d86fc03891 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Wed, 6 Aug 2014 10:53:40 +0200
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Subject: [PATCH 51/57] SPI: MIPS: ralink: add mt7621 support
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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drivers/spi/spi-rt2880.c | 218 +++++++++++++++++++++++++++++++++++++++++++---
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1 file changed, 205 insertions(+), 13 deletions(-)
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--- a/drivers/spi/spi-rt2880.c
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+++ b/drivers/spi/spi-rt2880.c
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@@ -21,8 +21,13 @@
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#include <linux/io.h>
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#include <linux/reset.h>
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#include <linux/spi/spi.h>
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+#include <linux/of_device.h>
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#include <linux/platform_device.h>
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+#include <ralink_regs.h>
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+
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+#define SPI_BPW_MASK(bits) BIT((bits) - 1)
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+
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#define DRIVER_NAME "spi-rt2880"
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/* only one slave is supported*/
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#define RALINK_NUM_CHIPSELECTS 1
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@@ -63,6 +68,25 @@
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/* SPIFIFOSTAT register bit field */
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#define SPIFIFOSTAT_TXFULL BIT(17)
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+#define MT7621_SPI_TRANS 0x00
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+#define SPITRANS_BUSY BIT(16)
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+#define MT7621_SPI_OPCODE 0x04
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+#define MT7621_SPI_DATA0 0x08
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+#define SPI_CTL_TX_RX_CNT_MASK 0xff
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+#define SPI_CTL_START BIT(8)
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+#define MT7621_SPI_POLAR 0x38
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+#define MT7621_SPI_MASTER 0x28
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+#define MT7621_SPI_SPACE 0x3c
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+
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+struct rt2880_spi;
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+
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+struct rt2880_spi_ops {
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+ void (*init_hw)(struct rt2880_spi *rs);
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+ void (*set_cs)(struct rt2880_spi *rs, int enable);
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+ int (*baudrate_set)(struct spi_device *spi, unsigned int speed);
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+ unsigned int (*write_read)(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer);
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+};
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+
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struct rt2880_spi {
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struct spi_master *master;
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void __iomem *base;
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@@ -70,6 +94,8 @@ struct rt2880_spi {
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unsigned int speed;
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struct clk *clk;
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spinlock_t lock;
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+
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+ struct rt2880_spi_ops *ops;
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};
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static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
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@@ -149,6 +175,17 @@ static int rt2880_spi_baudrate_set(struc
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return 0;
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}
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+static int mt7621_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
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+{
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+/* u32 master = rt2880_spi_read(rs, MT7621_SPI_MASTER);
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+
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+ // set default clock to hclk/5
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+ master &= ~(0xfff << 16);
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+ master |= 0x3 << 16;
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+*/
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+ return 0;
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+}
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+
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/*
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* called only when no transfer is active on the bus
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*/
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@@ -164,7 +201,7 @@ rt2880_spi_setup_transfer(struct spi_dev
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if (rs->speed != speed) {
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dev_dbg(&spi->dev, "speed_hz:%u\n", speed);
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- rc = rt2880_spi_baudrate_set(spi, speed);
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+ rc = rs->ops->baudrate_set(spi, speed);
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if (rc)
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return rc;
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}
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@@ -180,6 +217,17 @@ static void rt2880_spi_set_cs(struct rt2
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rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
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}
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+static void mt7621_spi_set_cs(struct rt2880_spi *rs, int enable)
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+{
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+ u32 polar = rt2880_spi_read(rs, MT7621_SPI_POLAR);
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+
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+ if (enable)
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+ polar |= 1;
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+ else
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+ polar &= ~1;
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+ rt2880_spi_write(rs, MT7621_SPI_POLAR, polar);
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+}
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+
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static inline int rt2880_spi_wait_till_ready(struct rt2880_spi *rs)
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{
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int i;
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@@ -198,8 +246,26 @@ static inline int rt2880_spi_wait_till_r
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return -ETIMEDOUT;
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}
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+static inline int mt7621_spi_wait_till_ready(struct rt2880_spi *rs)
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+{
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+ int i;
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+
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+ for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
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+ u32 status;
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+
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+ status = rt2880_spi_read(rs, MT7621_SPI_TRANS);
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+ if ((status & SPITRANS_BUSY) == 0) {
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+ return 0;
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+ }
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+ cpu_relax();
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+ udelay(1);
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+ }
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+
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+ return -ETIMEDOUT;
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+}
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+
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static unsigned int
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-rt2880_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
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+rt2880_spi_write_read(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer)
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{
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struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
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unsigned count = 0;
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@@ -239,6 +305,100 @@ out:
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return count;
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}
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+static unsigned int
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+mt7621_spi_write_read(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer)
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+{
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+ struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
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+ struct spi_transfer *next = NULL;
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+ const u8 *tx = xfer->tx_buf;
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+ u8 *rx = NULL;
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+ u32 trans;
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+ int len = xfer->len;
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+
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+ if (!tx)
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+ return 0;
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+
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+ if (!list_is_last(&xfer->transfer_list, list)) {
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+ next = list_entry(xfer->transfer_list.next, struct spi_transfer, transfer_list);
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+ rx = next->rx_buf;
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+ }
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+
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+ trans = rt2880_spi_read(rs, MT7621_SPI_TRANS);
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+ trans &= ~SPI_CTL_TX_RX_CNT_MASK;
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+
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+ if (tx) {
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+ u32 data0 = 0, opcode = 0;
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+
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+ switch (xfer->len) {
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+ case 8:
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+ data0 |= tx[7] << 24;
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+ case 7:
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+ data0 |= tx[6] << 16;
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+ case 6:
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+ data0 |= tx[5] << 8;
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+ case 5:
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+ data0 |= tx[4];
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+ case 4:
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+ opcode |= tx[3] << 8;
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+ case 3:
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+ opcode |= tx[2] << 16;
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+ case 2:
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+ opcode |= tx[1] << 24;
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+ case 1:
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+ opcode |= tx[0];
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+ break;
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+
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+ default:
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+ dev_err(&spi->dev, "trying to write too many bytes: %d\n", next->len);
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+ return -EINVAL;
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+ }
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+
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+ rt2880_spi_write(rs, MT7621_SPI_DATA0, data0);
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+ rt2880_spi_write(rs, MT7621_SPI_OPCODE, opcode);
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+ trans |= xfer->len;
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+ }
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+
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+ if (rx)
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+ trans |= (next->len << 4);
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+ rt2880_spi_write(rs, MT7621_SPI_TRANS, trans);
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+ trans |= SPI_CTL_START;
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+ rt2880_spi_write(rs, MT7621_SPI_TRANS, trans);
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+
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+ mt7621_spi_wait_till_ready(rs);
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+
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+ if (rx) {
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+ u32 data0 = rt2880_spi_read(rs, MT7621_SPI_DATA0);
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+ u32 opcode = rt2880_spi_read(rs, MT7621_SPI_OPCODE);
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+
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+ switch (next->len) {
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+ case 8:
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+ rx[7] = (opcode >> 24) & 0xff;
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+ case 7:
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+ rx[6] = (opcode >> 16) & 0xff;
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+ case 6:
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+ rx[5] = (opcode >> 8) & 0xff;
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+ case 5:
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+ rx[4] = opcode & 0xff;
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+ case 4:
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+ rx[3] = (data0 >> 24) & 0xff;
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+ case 3:
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+ rx[2] = (data0 >> 16) & 0xff;
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+ case 2:
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+ rx[1] = (data0 >> 8) & 0xff;
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+ case 1:
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+ rx[0] = data0 & 0xff;
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+ break;
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+
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+ default:
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+ dev_err(&spi->dev, "trying to read too many bytes: %d\n", next->len);
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+ return -EINVAL;
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+ }
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+ len += next->len;
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+ }
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+
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+ return len;
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+}
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+
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static int rt2880_spi_transfer_one_message(struct spi_master *master,
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struct spi_message *m)
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{
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@@ -280,25 +440,25 @@ static int rt2880_spi_transfer_one_messa
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}
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if (!cs_active) {
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- rt2880_spi_set_cs(rs, 1);
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+ rs->ops->set_cs(rs, 1);
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cs_active = 1;
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}
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if (t->len)
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- m->actual_length += rt2880_spi_write_read(spi, t);
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+ m->actual_length += rs->ops->write_read(spi, &m->transfers, t);
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if (t->delay_usecs)
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udelay(t->delay_usecs);
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if (t->cs_change) {
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- rt2880_spi_set_cs(rs, 0);
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+ rs->ops->set_cs(rs, 0);
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cs_active = 0;
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}
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}
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msg_done:
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if (cs_active)
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- rt2880_spi_set_cs(rs, 0);
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+ rs->ops->set_cs(rs, 0);
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m->status = status;
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spi_finalize_current_message(master);
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@@ -334,8 +494,41 @@ static void rt2880_spi_reset(struct rt28
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rt2880_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
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}
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+static void mt7621_spi_reset(struct rt2880_spi *rs)
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+{
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+ u32 master = rt2880_spi_read(rs, MT7621_SPI_MASTER);
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+
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+ master &= ~(0xfff << 16);
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+ master |= 3 << 16;
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+
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+ master |= 7 << 29;
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+ rt2880_spi_write(rs, MT7621_SPI_MASTER, master);
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+}
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+
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+static struct rt2880_spi_ops spi_ops[] = {
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+ {
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+ .init_hw = rt2880_spi_reset,
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+ .set_cs = rt2880_spi_set_cs,
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+ .baudrate_set = rt2880_spi_baudrate_set,
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+ .write_read = rt2880_spi_write_read,
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+ }, {
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+ .init_hw = mt7621_spi_reset,
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+ .set_cs = mt7621_spi_set_cs,
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+ .baudrate_set = mt7621_spi_baudrate_set,
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+ .write_read = mt7621_spi_write_read,
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+ },
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+};
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+
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+static const struct of_device_id rt2880_spi_match[] = {
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+ { .compatible = "ralink,rt2880-spi", .data = &spi_ops[0]},
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+ { .compatible = "ralink,mt7621-spi", .data = &spi_ops[1] },
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+ {},
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+};
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+MODULE_DEVICE_TABLE(of, rt2880_spi_match);
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+
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static int rt2880_spi_probe(struct platform_device *pdev)
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{
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+ const struct of_device_id *match;
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struct spi_master *master;
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struct rt2880_spi *rs;
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unsigned long flags;
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@@ -344,6 +537,10 @@ static int rt2880_spi_probe(struct platf
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int status = 0;
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struct clk *clk;
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+ match = of_match_device(rt2880_spi_match, &pdev->dev);
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+ if (!match)
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+ return -EINVAL;
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+
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(&pdev->dev, r);
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if (IS_ERR(base))
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@@ -382,12 +579,13 @@ static int rt2880_spi_probe(struct platf
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rs->clk = clk;
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rs->master = master;
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rs->sys_freq = clk_get_rate(rs->clk);
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+ rs->ops = (struct rt2880_spi_ops *) match->data;
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dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
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spin_lock_irqsave(&rs->lock, flags);
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device_reset(&pdev->dev);
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- rt2880_spi_reset(rs);
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+ rs->ops->init_hw(rs);
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return spi_register_master(master);
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}
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@@ -408,12 +606,6 @@ static int rt2880_spi_remove(struct plat
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MODULE_ALIAS("platform:" DRIVER_NAME);
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-static const struct of_device_id rt2880_spi_match[] = {
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- { .compatible = "ralink,rt2880-spi" },
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- {},
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-};
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-MODULE_DEVICE_TABLE(of, rt2880_spi_match);
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-
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static struct platform_driver rt2880_spi_driver = {
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.driver = {
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.name = DRIVER_NAME,
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@ -0,0 +1,343 @@
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--- a/drivers/spi/Kconfig
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+++ b/drivers/spi/Kconfig
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@@ -396,6 +396,12 @@ config SPI_RT2880
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help
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This selects a driver for the Ralink RT288x/RT305x SPI Controller.
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+config SPI_MT7621
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+ tristate "MediaTek MT7621 SPI Controller"
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+ depends on RALINK
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+ help
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+ This selects a driver for the MediaTek MT7621 SPI Controller.
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+
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config SPI_S3C24XX
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tristate "Samsung S3C24XX series SPI"
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depends on ARCH_S3C24XX
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--- a/drivers/spi/Makefile
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+++ b/drivers/spi/Makefile
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@@ -44,6 +44,7 @@ obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70l
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obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o
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obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o
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obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o
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+obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o
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obj-$(CONFIG_SPI_MXS) += spi-mxs.o
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obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o
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obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o
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--- /dev/null
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+++ b/drivers/spi/spi-mt7621.c
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@@ -0,0 +1,315 @@
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+/*
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+ * spi-mt7621.c -- MediaTek MT7621 SPI controller driver
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+ *
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+ * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
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+ * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
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+ * Copyright (C) 2014-2015 Felix Fietkau <nbd@openwrt.org>
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+ *
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+ * Some parts are based on spi-orion.c:
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+ * Author: Shadi Ammouri <shadi@marvell.com>
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+ * Copyright (C) 2007-2008 Marvell Ltd.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ */
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+
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+#include <linux/init.h>
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+#include <linux/module.h>
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+#include <linux/clk.h>
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+#include <linux/err.h>
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+#include <linux/delay.h>
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+#include <linux/io.h>
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+#include <linux/reset.h>
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+#include <linux/spi/spi.h>
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+#include <linux/of_device.h>
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+#include <linux/platform_device.h>
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+#include <linux/swab.h>
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+
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+#include <ralink_regs.h>
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+
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+#define SPI_BPW_MASK(bits) BIT((bits) - 1)
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+
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+#define DRIVER_NAME "spi-mt7621"
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+/* in usec */
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+#define RALINK_SPI_WAIT_MAX_LOOP 2000
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+
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+/* SPISTAT register bit field */
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+#define SPISTAT_BUSY BIT(0)
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+
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+#define MT7621_SPI_TRANS 0x00
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+#define SPITRANS_BUSY BIT(16)
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+
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+#define MT7621_SPI_OPCODE 0x04
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+#define MT7621_SPI_DATA0 0x08
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+#define SPI_CTL_TX_RX_CNT_MASK 0xff
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+#define SPI_CTL_START BIT(8)
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+
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+#define MT7621_SPI_POLAR 0x38
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+#define MT7621_SPI_MASTER 0x28
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+#define MT7621_SPI_MOREBUF 0x2c
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+#define MT7621_SPI_SPACE 0x3c
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+
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+#define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH)
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+
|
||||
+struct mt7621_spi;
|
||||
+
|
||||
+struct mt7621_spi {
|
||||
+ struct spi_master *master;
|
||||
+ void __iomem *base;
|
||||
+ unsigned int sys_freq;
|
||||
+ unsigned int speed;
|
||||
+ struct clk *clk;
|
||||
+ spinlock_t lock;
|
||||
+
|
||||
+ struct mt7621_spi_ops *ops;
|
||||
+};
|
||||
+
|
||||
+static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
|
||||
+{
|
||||
+ return spi_master_get_devdata(spi->master);
|
||||
+}
|
||||
+
|
||||
+static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
|
||||
+{
|
||||
+ return ioread32(rs->base + reg);
|
||||
+}
|
||||
+
|
||||
+static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
|
||||
+{
|
||||
+ iowrite32(val, rs->base + reg);
|
||||
+}
|
||||
+
|
||||
+static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
|
||||
+{
|
||||
+ struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
|
||||
+ u32 polar = mt7621_spi_read(rs, MT7621_SPI_POLAR);
|
||||
+
|
||||
+ if (enable)
|
||||
+ polar |= 1;
|
||||
+ else
|
||||
+ polar &= ~1;
|
||||
+ mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
|
||||
+}
|
||||
+
|
||||
+static inline int mt7621_spi_wait_till_ready(struct spi_device *spi)
|
||||
+{
|
||||
+ struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
|
||||
+ int i;
|
||||
+
|
||||
+ for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
|
||||
+ u32 status;
|
||||
+
|
||||
+ status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
|
||||
+ if ((status & SPITRANS_BUSY) == 0) {
|
||||
+ return 0;
|
||||
+ }
|
||||
+ cpu_relax();
|
||||
+ udelay(1);
|
||||
+ }
|
||||
+
|
||||
+ return -ETIMEDOUT;
|
||||
+}
|
||||
+
|
||||
+static int mt7621_spi_transfer_one_message(struct spi_master *master,
|
||||
+ struct spi_message *m)
|
||||
+{
|
||||
+ struct mt7621_spi *rs = spi_master_get_devdata(master);
|
||||
+ struct spi_device *spi = m->spi;
|
||||
+ struct spi_transfer *t = NULL;
|
||||
+ int status = 0;
|
||||
+ int i, len = 0;
|
||||
+ int rx_len = 0;
|
||||
+ u32 data[9] = { 0 };
|
||||
+ u32 val;
|
||||
+
|
||||
+ mt7621_spi_wait_till_ready(spi);
|
||||
+
|
||||
+ list_for_each_entry(t, &m->transfers, transfer_list) {
|
||||
+ const u8 *buf = t->tx_buf;
|
||||
+
|
||||
+ if (t->rx_buf)
|
||||
+ rx_len += t->len;
|
||||
+
|
||||
+ if (!buf)
|
||||
+ continue;
|
||||
+
|
||||
+ if (WARN_ON(len + t->len > 36)) {
|
||||
+ status = -EIO;
|
||||
+ goto msg_done;
|
||||
+ }
|
||||
+
|
||||
+ for (i = 0; i < t->len; i++, len++)
|
||||
+ data[len / 4] |= buf[i] << (8 * (len & 3));
|
||||
+ }
|
||||
+
|
||||
+ if (WARN_ON(rx_len > 32)) {
|
||||
+ status = -EIO;
|
||||
+ goto msg_done;
|
||||
+ }
|
||||
+
|
||||
+ data[0] = swab32(data[0]);
|
||||
+ if (len < 4)
|
||||
+ data[0] >>= (4 - len) * 8;
|
||||
+
|
||||
+ for (i = 0; i < len; i += 4)
|
||||
+ mt7621_spi_write(rs, MT7621_SPI_OPCODE + i, data[i / 4]);
|
||||
+
|
||||
+ val = (min_t(int, len, 4) * 8) << 24;
|
||||
+ if (len > 4)
|
||||
+ val |= (len - 4) * 8;
|
||||
+ val |= (rx_len * 8) << 12;
|
||||
+ mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
|
||||
+
|
||||
+ mt7621_spi_set_cs(spi, 1);
|
||||
+
|
||||
+ val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
|
||||
+ val |= SPI_CTL_START;
|
||||
+ mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
|
||||
+
|
||||
+ mt7621_spi_wait_till_ready(spi);
|
||||
+
|
||||
+ mt7621_spi_set_cs(spi, 0);
|
||||
+
|
||||
+ for (i = 0; i < rx_len; i += 4)
|
||||
+ data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
|
||||
+
|
||||
+ m->actual_length = len + rx_len;
|
||||
+
|
||||
+ len = 0;
|
||||
+ list_for_each_entry(t, &m->transfers, transfer_list) {
|
||||
+ u8 *buf = t->rx_buf;
|
||||
+
|
||||
+ if (!buf)
|
||||
+ continue;
|
||||
+
|
||||
+ for (i = 0; i < t->len; i++, len++)
|
||||
+ buf[i] = data[len / 4] >> (8 * (len & 3));
|
||||
+ }
|
||||
+
|
||||
+msg_done:
|
||||
+ m->status = status;
|
||||
+ spi_finalize_current_message(master);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int mt7621_spi_setup(struct spi_device *spi)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void mt7621_spi_reset(struct mt7621_spi *rs)
|
||||
+{
|
||||
+ u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
|
||||
+
|
||||
+ master &= ~(0xfff << 16);
|
||||
+ master |= 13 << 16;
|
||||
+ master |= 7 << 29;
|
||||
+ master |= 1 << 2;
|
||||
+
|
||||
+ mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id mt7621_spi_match[] = {
|
||||
+ { .compatible = "ralink,mt7621-spi" },
|
||||
+ {},
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, mt7621_spi_match);
|
||||
+
|
||||
+static int mt7621_spi_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ const struct of_device_id *match;
|
||||
+ struct spi_master *master;
|
||||
+ struct mt7621_spi *rs;
|
||||
+ unsigned long flags;
|
||||
+ void __iomem *base;
|
||||
+ struct resource *r;
|
||||
+ int status = 0;
|
||||
+ struct clk *clk;
|
||||
+ struct mt7621_spi_ops *ops;
|
||||
+
|
||||
+ match = of_match_device(mt7621_spi_match, &pdev->dev);
|
||||
+ if (!match)
|
||||
+ return -EINVAL;
|
||||
+ ops = (struct mt7621_spi_ops *)match->data;
|
||||
+
|
||||
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ base = devm_ioremap_resource(&pdev->dev, r);
|
||||
+ if (IS_ERR(base))
|
||||
+ return PTR_ERR(base);
|
||||
+
|
||||
+ clk = devm_clk_get(&pdev->dev, NULL);
|
||||
+ if (IS_ERR(clk)) {
|
||||
+ dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
|
||||
+ status);
|
||||
+ return PTR_ERR(clk);
|
||||
+ }
|
||||
+
|
||||
+ status = clk_prepare_enable(clk);
|
||||
+ if (status)
|
||||
+ return status;
|
||||
+
|
||||
+ master = spi_alloc_master(&pdev->dev, sizeof(*rs));
|
||||
+ if (master == NULL) {
|
||||
+ dev_dbg(&pdev->dev, "master allocation failed\n");
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+
|
||||
+ master->mode_bits = RT2880_SPI_MODE_BITS;
|
||||
+
|
||||
+ master->setup = mt7621_spi_setup;
|
||||
+ master->transfer_one_message = mt7621_spi_transfer_one_message;
|
||||
+ master->bits_per_word_mask = SPI_BPW_MASK(8);
|
||||
+ master->dev.of_node = pdev->dev.of_node;
|
||||
+ master->num_chipselect = 1;
|
||||
+
|
||||
+ dev_set_drvdata(&pdev->dev, master);
|
||||
+
|
||||
+ rs = spi_master_get_devdata(master);
|
||||
+ rs->base = base;
|
||||
+ rs->clk = clk;
|
||||
+ rs->master = master;
|
||||
+ rs->sys_freq = clk_get_rate(rs->clk);
|
||||
+ rs->ops = ops;
|
||||
+ dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
|
||||
+ spin_lock_irqsave(&rs->lock, flags);
|
||||
+
|
||||
+ device_reset(&pdev->dev);
|
||||
+
|
||||
+ mt7621_spi_reset(rs);
|
||||
+
|
||||
+ return spi_register_master(master);
|
||||
+}
|
||||
+
|
||||
+static int mt7621_spi_remove(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct spi_master *master;
|
||||
+ struct mt7621_spi *rs;
|
||||
+
|
||||
+ master = dev_get_drvdata(&pdev->dev);
|
||||
+ rs = spi_master_get_devdata(master);
|
||||
+
|
||||
+ clk_disable(rs->clk);
|
||||
+ spi_unregister_master(master);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+MODULE_ALIAS("platform:" DRIVER_NAME);
|
||||
+
|
||||
+static struct platform_driver mt7621_spi_driver = {
|
||||
+ .driver = {
|
||||
+ .name = DRIVER_NAME,
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .of_match_table = mt7621_spi_match,
|
||||
+ },
|
||||
+ .probe = mt7621_spi_probe,
|
||||
+ .remove = mt7621_spi_remove,
|
||||
+};
|
||||
+
|
||||
+module_platform_driver(mt7621_spi_driver);
|
||||
+
|
||||
+MODULE_DESCRIPTION("MT7621 SPI driver");
|
||||
+MODULE_AUTHOR("Felix Fietkau <nbd@openwrt.org>");
|
||||
+MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue