layerscape: add 64b/32b target for ls1046ardb device
Add support for NXP layerscape ls1046ardb 64b/32b Dev board. LS1046ARDB Specification: ------------------------- Memory subsystem: * 8GByte DDR4 SDRAM (64bit bus) * 512 Mbyte NAND flash * Two 64 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card * On-board 4G eMMC Ethernet: * Two XFI 10G ports * Two SGMII ports * Two RGMII ports PCIe: * PCIe1 (SerDes2 Lane0) to miniPCIe slot * PCIe2 (SerDes2 Lane1) to x2 PCIe slot * PCIe3 (SerDes2 Lane2) to x4 PCIe slot * USB 3.0: one super speed USB 3.0 type A port, one Micro-AB port * UART: supports two UARTs up to 115200 bps for console Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>v19.07.3_mercusys_ac12_duma
Yutang Jiang
8 years ago
committed by
John Crispin
parent
76fa771a78
commit
ad907e1c03
@ -0,0 +1,148 @@
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From 880b7aa2e2c62e54245fb77d92db502175232d86 Mon Sep 17 00:00:00 2001
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From: Zhao Qiang <qiang.zhao@nxp.com>
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Date: Wed, 12 Oct 2016 11:01:17 +0800
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Subject: [PATCH 140/141] config: add freescale config for amr64
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Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
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---
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arch/arm64/configs/freescale.config | 134 +++++++++++++++++++++++++++++++++++
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1 file changed, 134 insertions(+)
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create mode 100644 arch/arm64/configs/freescale.config
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--- /dev/null
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+++ b/arch/arm64/configs/freescale.config
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@@ -0,0 +1,134 @@
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+# general options
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+CONFIG_LOCALVERSION_AUTO=y
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+CONFIG_SLAB=y
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+CONFIG_MODULE_FORCE_LOAD=y
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+CONFIG_MODVERSIONS=y
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+CONFIG_ARM64_VA_BITS_48=y
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+CONFIG_BLK_DEV_RAM=y
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+CONFIG_BLK_DEV_RAM_SIZE=262144
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+CONFIG_PRINTK_TIME=y
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+CONFIG_PID_IN_CONTEXTIDR=y
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+CONFIG_IPV6=y
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+# iommu
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+CONFIG_IOMMU_SUPPORT=y
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+CONFIG_ARM_SMMU=y
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+# dpaa2
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+CONFIG_STAGING=y
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+CONFIG_FSL_MC_BUS=y
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+CONFIG_FSL_MC_RESTOOL=y
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+CONFIG_FSL_MC_DPIO=y
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+CONFIG_FSL_DPAA2=y
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+CONFIG_NET_NS=y
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+CONFIG_FSL_DPAA2_DCE=y
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+CONFIG_FSL_DCE_FLOW_LIMIT=65536
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+CONFIG_FSL_DCE_API_TIME_TRIAL=m
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+CONFIG_LS_SOC_DRIVERS=y
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+# mdio
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+CONFIG_FSL_XGMAC_MDIO=y
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+CONFIG_MDIO_BUS_MUX_MMIOREG=y
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+# phy
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+CONFIG_AQUANTIA_PHY=y
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+CONFIG_VITESSE_PHY=y
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+CONFIG_REALTEK_PHY=y
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+CONFIG_FIXED_PHY=y
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+# reset support
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+CONFIG_POWER_RESET_LAYERSCAPE=y
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+# pci
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+CONFIG_PCI_LAYERSCAPE=y
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+CONFIG_PCI_HOST_GENERIC=y
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+CONFIG_E1000=y
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+CONFIG_E1000E=y
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+# clock driver
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+CONFIG_CLK_QORIQ=y
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+# usb
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+CONFIG_USB_XHCI_HCD=y
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+CONFIG_USB_DWC3=y
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+CONFIG_DMADEVICES=y
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+# ahci/sata
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+CONFIG_AHCI_QORIQ=y
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+# esdhc
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+CONFIG_MMC_SDHCI_OF_ESDHC=y
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+# virtualization
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+CONFIG_VHOST_NET=y
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+CONFIG_KVM_ARM_MAX_VCPUS=8
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+# I2C
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+CONFIG_I2C=y
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+CONFIG_I2C_CHARDEV=y
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+CONFIG_I2C_MUX=y
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+CONFIG_I2C_MUX_PCA954x=y
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+CONFIG_I2C_IMX=y
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+# hardware monitor
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+CONFIG_SENSORS_LM90=y
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+CONFIG_SENSORS_INA2XX=y
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+# DPAA 1
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+CONFIG_HAS_FSL_QBMAN=y
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+CONFIG_CRYPTO_DEV_FSL_CAAM=y
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+# network
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+CONFIG_BRIDGE=m
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+CONFIG_MACVLAN=y
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+CONFIG_FSL_SDK_FMAN=y
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+CONFIG_FMAN_ARM=y
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+CONFIG_FSL_SDK_DPAA_ETH=y
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+CONFIG_INET_ESP=y
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+CONFIG_XFRM_USER=y
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+CONFIG_NET_KEY=y
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+# vfio
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+CONFIG_VFIO=y
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+CONFIG_VFIO_PCI=y
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+CONFIG_VFIO_FSL_MC=y
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+# CPU Frequency scaling
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+CONFIG_CPU_FREQ=y
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+CONFIG_CPU_FREQ_GOV_COMMON=y
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+CONFIG_CPU_FREQ_STAT=y
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+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
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+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
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+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
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+CONFIG_CPU_FREQ_GOV_USERSPACE=y
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+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
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+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
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+CONFIG_QORIQ_CPUFREQ=y
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+#ifc
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+CONFIG_MTD_OF_PARTS=y
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+CONFIG_MTD_GEN_PROBE=y
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+CONFIG_MTD=y
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+CONFIG_MTD_CMDLINE_PARTS=y
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+CONFIG_MTD_BLOCK=y
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+CONFIG_MTD_CFI=y
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+CONFIG_MTD_CFI_ADV_OPTIONS=y
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+CONFIG_MTD_CFI_INTELEXT=y
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+CONFIG_MTD_CFI_AMDSTD=y
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+CONFIG_MTD_CFI_STAA=y
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+CONFIG_MTD_PHYSMAP_OF=y
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+CONFIG_MTD_NAND=y
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+CONFIG_MTD_NAND_FSL_IFC=y
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+#spi
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+CONFIG_SPI_FSL_DSPI=y
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+CONFIG_MTD_SPI_NOR=y
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+CONFIG_MTD_DATAFLASH=y
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+CONFIG_MTD_M25P80=y
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+CONFIG_MTD_SST25L=y
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+#RTC
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+CONFIG_RTC_DRV_DS3232=y
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+#CryptoAPI
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+CONFIG_CRYPTO_SHA256=y
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+CONFIG_CRYPTO_SHA512=y
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+# ls1046a
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+CONFIG_MTD_CFI_BE_BYTE_SWAP=y
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+CONFIG_SPI_FSL_QUADSPI=y
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+CONFIG_RTC_DRV_PCF2127=y
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+CONFIG_WATCHDOG=y
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+CONFIG_IMX2_WDT=y
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+CONFIG_HWMON=y
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+CONFIG_SENSORS_LM90=y
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+CONFIG_SENSORS_INA2XX=y
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+CONFIG_EEPROM_AT24=y
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+# lpuart
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+CONFIG_SERIAL_FSL_LPUART=y
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+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
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+# ftm
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+CONFIG_FTM_ALARM=y
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+# qDMA
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+CONFIG_FSL_QDMA=y
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+CONFIG_DMATEST=y
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+#NVMe
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+CONFIG_BLK_DEV_NVME=y
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,557 @@
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From feb12cb699adbac2d4619401c7ff4fcc2fc97b6c Mon Sep 17 00:00:00 2001
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From: Mingkai Hu <mingkai.hu@nxp.com>
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Date: Mon, 26 Sep 2016 12:33:42 +0800
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Subject: [PATCH 132/141] dts/ls1046a: add LS1046ARDB board support
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commit e95a28cfd9a392fe5dc189a9ae097bbaaccd1228
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[context adjustment]
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Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
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Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
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---
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arch/arm64/boot/dts/freescale/Makefile | 1 +
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arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 198 +++++++++++++++++++++
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arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 178 +++++++++++++-----
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3 files changed, 328 insertions(+), 49 deletions(-)
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create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
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--- a/arch/arm64/boot/dts/freescale/Makefile
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+++ b/arch/arm64/boot/dts/freescale/Makefile
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@@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
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+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
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always := $(dtb-y)
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subdir-y := $(dts-dirs)
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--- /dev/null
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
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@@ -0,0 +1,198 @@
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+/*
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+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
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+ *
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+ * Copyright 2016, Freescale Semiconductor
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+ *
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+ * Mingkai Hu <mingkai.hu@nxp.com>
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+ *
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+ * This file is dual-licensed: you can use it either under the terms
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+ * of the GPLv2 or the X11 license, at your option. Note that this dual
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+ * licensing only applies to this file, and not this project as a
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+ * whole.
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+ *
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+ * a) This library is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of the
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+ * License, or (at your option) any later version.
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+ *
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+ * This library is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * Or, alternatively,
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+ *
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+ * b) Permission is hereby granted, free of charge, to any person
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+ * obtaining a copy of this software and associated documentation
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+ * files (the "Software"), to deal in the Software without
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+ * restriction, including without limitation the rights to use,
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+ * copy, modify, merge, publish, distribute, sublicense, and/or
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+ * sell copies of the Software, and to permit persons to whom the
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+ * Software is furnished to do so, subject to the following
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+ * conditions:
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+ *
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+ * The above copyright notice and this permission notice shall be
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+ * included in all copies or substantial portions of the Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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+ * OTHER DEALINGS IN THE SOFTWARE.
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+ */
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+
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+/dts-v1/;
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+#include "fsl-ls1046a.dtsi"
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+
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+/ {
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+ model = "LS1046A RDB Board";
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+ compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
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+
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+ aliases {
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+ ethernet0 = &fm1mac3;
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+ ethernet1 = &fm1mac4;
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+ ethernet2 = &fm1mac5;
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+ ethernet3 = &fm1mac6;
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+ ethernet4 = &fm1mac9;
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+ ethernet5 = &fm1mac10;
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+ };
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+};
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+
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+&i2c0 {
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+ status = "okay";
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+ ina220@40 {
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+ compatible = "ti,ina220";
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+ reg = <0x40>;
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+ shunt-resistor = <1000>;
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+ };
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+ adt7461a@4c {
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+ compatible = "adi,adt7461";
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+ reg = <0x4c>;
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+ };
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+ eeprom@56 {
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+ compatible = "at24,24c512";
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+ reg = <0x52>;
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+ };
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+ eeprom@57 {
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+ compatible = "at24,24c512";
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+ reg = <0x53>;
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+ };
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+};
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+
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+&i2c3 {
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+ status = "okay";
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+ rtc@51 {
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+ compatible = "nxp,pcf2129";
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+ reg = <0x51>;
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+ };
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+};
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+
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+&ifc {
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+ status = "okay";
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+ #address-cells = <2>;
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+ #size-cells = <1>;
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+ /* NAND Flashe and CPLD on board */
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+ ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
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+ 0x2 0x0 0x0 0x7fb00000 0x00000100>;
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+
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+ nand@0,0 {
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+ compatible = "fsl,ifc-nand";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ reg = <0x0 0x0 0x10000>;
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+ };
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+
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+ cpld: board-control@2,0 {
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+ compatible = "fsl,ls1046ardb-cpld";
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+ reg = <0x2 0x0 0x0000100>;
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+ };
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+};
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+
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+&qspi {
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+ num-cs = <2>;
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+ bus-num = <0>;
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+ status = "okay";
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+
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+ qflash0: s25fs128s@0 {
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+ compatible = "spansion,m25p80";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ spi-max-frequency = <20000000>;
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+ reg = <0>;
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+ };
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+
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+ qflash1: s25fs128s@1 {
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+ compatible = "spansion,m25p80";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ spi-max-frequency = <20000000>;
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+ reg = <1>;
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+ };
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+
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+};
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+
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+&duart0 {
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+ status = "okay";
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+};
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+
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+&duart1 {
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+ status = "okay";
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+};
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+
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+&fman0 {
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+ ethernet@e4000 {
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+ phy-handle = <&rgmii_phy1>;
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+ phy-connection-type = "rgmii";
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+ };
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+
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+ ethernet@e6000 {
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+ phy-handle = <&rgmii_phy2>;
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+ phy-connection-type = "rgmii";
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+ };
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+
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+ ethernet@e8000 {
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+ phy-handle = <&sgmii_phy1>;
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+ phy-connection-type = "sgmii";
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+ };
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+
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+ ethernet@ea000 {
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+ phy-handle = <&sgmii_phy2>;
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+ phy-connection-type = "sgmii";
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+ };
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+
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+ ethernet@f0000 { /* 10GEC1 */
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+ phy-handle = <&aqr106_phy>;
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+ phy-connection-type = "xgmii";
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+ };
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+
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+ ethernet@f2000 { /* 10GEC2 */
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+ fixed-link = <0 1 10000 0 0>;
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+ phy-connection-type = "xgmii";
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+ };
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+
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+ mdio@fc000 {
|
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+ rgmii_phy1: ethernet-phy@1 {
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+ reg = <0x1>;
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+ };
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+ rgmii_phy2: ethernet-phy@2 {
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+ reg = <0x2>;
|
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+ };
|
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+ sgmii_phy1: ethernet-phy@3 {
|
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+ reg = <0x3>;
|
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+ };
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+ sgmii_phy2: ethernet-phy@4 {
|
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+ reg = <0x4>;
|
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+ };
|
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+ };
|
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+
|
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+ mdio@fd000 {
|
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+ aqr106_phy: ethernet-phy@1 {
|
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+ compatible = "ethernet-phy-ieee802.3-c45";
|
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+ interrupts = <0 131 4>;
|
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+ reg = <0x0>;
|
||||
+ };
|
||||
+ };
|
||||
+};
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
|
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@@ -51,13 +51,7 @@
|
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#size-cells = <2>;
|
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|
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aliases {
|
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- ethernet0 = &fm1mac1;
|
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- ethernet1 = &fm1mac2;
|
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- ethernet2 = &fm1mac3;
|
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- ethernet3 = &fm1mac4;
|
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- ethernet4 = &fm1mac5;
|
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- ethernet5 = &fm1mac6;
|
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- ethernet6 = &fm1mac9;
|
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+ crypto = &crypto;
|
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};
|
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|
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cpus {
|
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@@ -70,6 +64,7 @@
|
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reg = <0x0>;
|
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clocks = <&clockgen 1 0>;
|
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next-level-cache = <&l2>;
|
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+ cpu-idle-states = <&CPU_PH20>;
|
||||
};
|
||||
|
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cpu1: cpu@1 {
|
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@@ -78,6 +73,7 @@
|
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reg = <0x1>;
|
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clocks = <&clockgen 1 0>;
|
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next-level-cache = <&l2>;
|
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+ cpu-idle-states = <&CPU_PH20>;
|
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};
|
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|
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cpu2: cpu@2 {
|
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@@ -86,6 +82,7 @@
|
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reg = <0x2>;
|
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clocks = <&clockgen 1 0>;
|
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next-level-cache = <&l2>;
|
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+ cpu-idle-states = <&CPU_PH20>;
|
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};
|
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|
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cpu3: cpu@3 {
|
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@@ -94,6 +91,7 @@
|
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reg = <0x3>;
|
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clocks = <&clockgen 1 0>;
|
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next-level-cache = <&l2>;
|
||||
+ cpu-idle-states = <&CPU_PH20>;
|
||||
};
|
||||
|
||||
l2: l2-cache {
|
||||
@@ -101,6 +99,19 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ idle-states {
|
||||
+ entry-method = "arm,psci";
|
||||
+
|
||||
+ CPU_PH20: cpu-ph20 {
|
||||
+ compatible = "arm,idle-state";
|
||||
+ idle-state-name = "PH20";
|
||||
+ arm,psci-suspend-param = <0x00010000>;
|
||||
+ entry-latency-us = <1000>;
|
||||
+ exit-latency-us = <1000>;
|
||||
+ min-residency-us = <3000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0 0x80000000>;
|
||||
@@ -193,6 +204,49 @@
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
+ crypto: crypto@1700000 {
|
||||
+ compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
|
||||
+ "fsl,sec-v4.0";
|
||||
+ fsl,sec-era = <8>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges = <0x0 0x00 0x1700000 0x100000>;
|
||||
+ reg = <0x00 0x1700000 0x0 0x100000>;
|
||||
+ interrupts = <0 75 0x4>;
|
||||
+
|
||||
+ sec_jr0: jr@10000 {
|
||||
+ compatible = "fsl,sec-v5.4-job-ring",
|
||||
+ "fsl,sec-v5.0-job-ring",
|
||||
+ "fsl,sec-v4.0-job-ring";
|
||||
+ reg = <0x10000 0x10000>;
|
||||
+ interrupts = <0 71 0x4>;
|
||||
+ };
|
||||
+
|
||||
+ sec_jr1: jr@20000 {
|
||||
+ compatible = "fsl,sec-v5.4-job-ring",
|
||||
+ "fsl,sec-v5.0-job-ring",
|
||||
+ "fsl,sec-v4.0-job-ring";
|
||||
+ reg = <0x20000 0x10000>;
|
||||
+ interrupts = <0 72 0x4>;
|
||||
+ };
|
||||
+
|
||||
+ sec_jr2: jr@30000 {
|
||||
+ compatible = "fsl,sec-v5.4-job-ring",
|
||||
+ "fsl,sec-v5.0-job-ring",
|
||||
+ "fsl,sec-v4.0-job-ring";
|
||||
+ reg = <0x30000 0x10000>;
|
||||
+ interrupts = <0 73 0x4>;
|
||||
+ };
|
||||
+
|
||||
+ sec_jr3: jr@40000 {
|
||||
+ compatible = "fsl,sec-v5.4-job-ring",
|
||||
+ "fsl,sec-v5.0-job-ring",
|
||||
+ "fsl,sec-v4.0-job-ring";
|
||||
+ reg = <0x40000 0x10000>;
|
||||
+ interrupts = <0 74 0x4>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
qman: qman@1880000 {
|
||||
compatible = "fsl,qman";
|
||||
reg = <0x00 0x1880000 0x0 0x10000>;
|
||||
@@ -490,6 +544,19 @@
|
||||
fsl,qman-channel-id = <0x800>;
|
||||
};
|
||||
|
||||
+ fman0_10g_rx1: port@91000 {
|
||||
+ cell-index = <1>;
|
||||
+ compatible = "fsl,fman-port-10g-rx";
|
||||
+ reg = <0x91000 0x1000>;
|
||||
+ };
|
||||
+
|
||||
+ fman0_10g_tx1: port@b1000 {
|
||||
+ cell-index = <1>;
|
||||
+ compatible = "fsl,fman-port-10g-tx";
|
||||
+ reg = <0xb1000 0x1000>;
|
||||
+ fsl,qman-channel-id = <0x801>;
|
||||
+ };
|
||||
+
|
||||
fm1mac9: ethernet@f0000 {
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,fman-memac";
|
||||
@@ -497,6 +564,13 @@
|
||||
fsl,port-handles = <&fman0_10g_rx0 &fman0_10g_tx0>;
|
||||
};
|
||||
|
||||
+ fm1mac10: ethernet@f2000 {
|
||||
+ cell-index = <1>;
|
||||
+ compatible = "fsl,fman-memac";
|
||||
+ reg = <0xf2000 0x1000>;
|
||||
+ fsl,port-handles = <&fman0_10g_rx1 &fman0_10g_tx1>;
|
||||
+ };
|
||||
+
|
||||
mdio@f1000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@@ -504,6 +578,13 @@
|
||||
reg = <0xf1000 0x1000>;
|
||||
};
|
||||
|
||||
+ mdio@f3000 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ compatible = "fsl,fman-memac-mdio";
|
||||
+ reg = <0xf3000 0x1000>;
|
||||
+ };
|
||||
+
|
||||
ptp_timer0: rtc@fe000 {
|
||||
compatible = "fsl,fman-rtc";
|
||||
reg = <0xfe000 0x1000>;
|
||||
@@ -657,7 +738,7 @@
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2950000 0x0 0x1000>;
|
||||
interrupts = <0 48 0x4>;
|
||||
- clocks = <&clockgen 0 0>;
|
||||
+ clocks = <&clockgen 4 0>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
@@ -712,7 +793,7 @@
|
||||
reg = <0x0 0x29d0000 0x0 0x10000>;
|
||||
interrupts = <0 86 0x4>;
|
||||
big-endian;
|
||||
- rcpm-wakeup = <&rcpm 0x0 0x20000000>;
|
||||
+ rcpm-wakeup = <&rcpm 0x00020000 0x0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -789,34 +870,34 @@
|
||||
big-endian;
|
||||
};
|
||||
|
||||
- msi1: msi-controller@1580000 {
|
||||
- compatible = "fsl,1s1046a-msi";
|
||||
- reg = <0x0 0x1580000 0x0 0x10000>;
|
||||
+ msi: msi-controller@1580000 {
|
||||
+ compatible = "fsl,ls1046a-msi";
|
||||
+ #address-cells = <2>;
|
||||
+ #size-cells = <2>;
|
||||
+ ranges;
|
||||
msi-controller;
|
||||
- interrupts = <0 116 0x4>,
|
||||
- <0 111 0x4>,
|
||||
- <0 112 0x4>,
|
||||
- <0 113 0x4>;
|
||||
- };
|
||||
|
||||
- msi2: msi-controller@1590000 {
|
||||
- compatible = "fsl,1s1046a-msi";
|
||||
- reg = <0x0 0x1590000 0x0 0x10000>;
|
||||
- msi-controller;
|
||||
- interrupts = <0 126 0x4>,
|
||||
- <0 121 0x4>,
|
||||
- <0 122 0x4>,
|
||||
- <0 123 0x4>;
|
||||
- };
|
||||
-
|
||||
- msi3: msi-controller@15a0000 {
|
||||
- compatible = "fsl,1s1046a-msi";
|
||||
- reg = <0x0 0x15a0000 0x0 0x10000>;
|
||||
- msi-controller;
|
||||
- interrupts = <0 160 0x4>,
|
||||
- <0 155 0x4>,
|
||||
- <0 156 0x4>,
|
||||
- <0 157 0x4>;
|
||||
+ msi-bank@1580000 {
|
||||
+ reg = <0x0 0x1580000 0x0 0x10000>;
|
||||
+ interrupts = <0 116 0x4>,
|
||||
+ <0 111 0x4>,
|
||||
+ <0 112 0x4>,
|
||||
+ <0 113 0x4>;
|
||||
+ };
|
||||
+ msi-bank@1590000 {
|
||||
+ reg = <0x0 0x1590000 0x0 0x10000>;
|
||||
+ interrupts = <0 126 0x4>,
|
||||
+ <0 121 0x4>,
|
||||
+ <0 122 0x4>,
|
||||
+ <0 123 0x4>;
|
||||
+ };
|
||||
+ msi-bank@15a0000 {
|
||||
+ reg = <0x0 0x15a0000 0x0 0x10000>;
|
||||
+ interrupts = <0 160 0x4>,
|
||||
+ <0 155 0x4>,
|
||||
+ <0 156 0x4>,
|
||||
+ <0 157 0x4>;
|
||||
+ };
|
||||
};
|
||||
|
||||
pcie@3400000 {
|
||||
@@ -826,15 +907,16 @@
|
||||
reg-names = "regs", "config";
|
||||
interrupts = <0 118 0x4>, /* controller interrupt */
|
||||
<0 117 0x4>; /* PME interrupt */
|
||||
- interrupt-names = "intr", "pme";
|
||||
+ interrupt-names = "aer";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
+ dma-coherent;
|
||||
num-lanes = <4>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
- msi-parent = <&msi1>;
|
||||
+ msi-parent = <&msi>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
|
||||
@@ -850,15 +932,16 @@
|
||||
reg-names = "regs", "config";
|
||||
interrupts = <0 128 0x4>,
|
||||
<0 127 0x4>;
|
||||
- interrupt-names = "intr", "pme";
|
||||
+ interrupt-names = "aer";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
+ dma-coherent;
|
||||
num-lanes = <2>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
- msi-parent = <&msi2>;
|
||||
+ msi-parent = <&msi>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
|
||||
@@ -874,15 +957,16 @@
|
||||
reg-names = "regs", "config";
|
||||
interrupts = <0 162 0x4>,
|
||||
<0 161 0x4>;
|
||||
- interrupt-names = "intr", "pme";
|
||||
+ interrupt-names = "aer";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
+ dma-coherent;
|
||||
num-lanes = <2>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
- msi-parent = <&msi3>;
|
||||
+ msi-parent = <&msi>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
|
||||
@@ -894,14 +978,6 @@
|
||||
|
||||
fsl,dpaa {
|
||||
compatible = "fsl,ls1046a-dpaa", "simple-bus", "fsl,dpaa";
|
||||
- ethernet@0 {
|
||||
- compatible = "fsl,dpa-ethernet";
|
||||
- fsl,fman-mac = <&fm1mac1>;
|
||||
- };
|
||||
- ethernet@1 {
|
||||
- compatible = "fsl,dpa-ethernet";
|
||||
- fsl,fman-mac = <&fm1mac2>;
|
||||
- };
|
||||
ethernet@2 {
|
||||
compatible = "fsl,dpa-ethernet";
|
||||
fsl,fman-mac = <&fm1mac3>;
|
||||
@@ -922,6 +998,10 @@
|
||||
compatible = "fsl,dpa-ethernet";
|
||||
fsl,fman-mac = <&fm1mac9>;
|
||||
};
|
||||
+ ethernet@9 {
|
||||
+ compatible = "fsl,dpa-ethernet";
|
||||
+ fsl,fman-mac = <&fm1mac10>;
|
||||
+ };
|
||||
};
|
||||
|
||||
qportals: qman-portals@500000000 {
|
||||
@ -0,0 +1,69 @@
|
||||
From 1a831d848c88f1bb9e599abc641a201be6b03ef7 Mon Sep 17 00:00:00 2001
|
||||
From: Mingkai Hu <mingkai.hu@nxp.com>
|
||||
Date: Mon, 18 Apr 2016 15:38:24 +0800
|
||||
Subject: [PATCH 133/141] ls1046ardb: add ITS file
|
||||
|
||||
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
|
||||
---
|
||||
kernel-ls1046a-rdb.its | 55 ++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
1 file changed, 55 insertions(+)
|
||||
create mode 100644 kernel-ls1046a-rdb.its
|
||||
|
||||
--- /dev/null
|
||||
+++ b/kernel-ls1046a-rdb.its
|
||||
@@ -0,0 +1,55 @@
|
||||
+/*
|
||||
+ * Copyright (C) 2016, Freescale Semiconductor
|
||||
+ *
|
||||
+ * Mingkai Hu <mingkai.hu@nxp.com>
|
||||
+ *
|
||||
+ * This file is licensed under the terms of the GNU General Public
|
||||
+ * License version 2. This program is licensed "as is" without any
|
||||
+ * warranty of any kind, whether express or implied.
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+/ {
|
||||
+ description = "Image file for the LS1046A Linux Kernel";
|
||||
+ #address-cells = <1>;
|
||||
+
|
||||
+ images {
|
||||
+ kernel@1 {
|
||||
+ description = "ARM64 Linux kernel";
|
||||
+ data = /incbin/("./arch/arm64/boot/Image.gz");
|
||||
+ type = "kernel";
|
||||
+ arch = "arm64";
|
||||
+ os = "linux";
|
||||
+ compression = "gzip";
|
||||
+ load = <0x80080000>;
|
||||
+ entry = <0x80080000>;
|
||||
+ };
|
||||
+ fdt@1 {
|
||||
+ description = "Flattened Device Tree blob";
|
||||
+ data = /incbin/("./arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dtb");
|
||||
+ type = "flat_dt";
|
||||
+ arch = "arm64";
|
||||
+ compression = "none";
|
||||
+ load = <0x90000000>;
|
||||
+ };
|
||||
+ ramdisk@1 {
|
||||
+ description = "LS1046 Ramdisk";
|
||||
+ data = /incbin/("./fsl-image-core-ls1046ardb-be.ext2.gz");
|
||||
+ type = "ramdisk";
|
||||
+ arch = "arm64";
|
||||
+ os = "linux";
|
||||
+ compression = "gzip";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ configurations {
|
||||
+ default = "config@1";
|
||||
+ config@1 {
|
||||
+ description = "Boot Linux kernel";
|
||||
+ kernel = "kernel@1";
|
||||
+ fdt = "fdt@1";
|
||||
+ ramdisk = "ramdisk@1";
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
@ -0,0 +1,32 @@
|
||||
From 887fd872791ce6e60045f4c6a97926365c6c817c Mon Sep 17 00:00:00 2001
|
||||
From: Yutang Jiang <yutang.jiang@nxp.com>
|
||||
Date: Wed, 7 Dec 2016 00:47:35 +0800
|
||||
Subject: [PATCH] armv8: aarch32: Execute 32-bit Linux for ls1046a
|
||||
|
||||
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
|
||||
---
|
||||
arch/arm/mach-imx/mach-layerscape.c | 4 +++-
|
||||
1 file changed, 3 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/arch/arm/mach-imx/mach-layerscape.c b/arch/arm/mach-imx/mach-layerscape.c
|
||||
index b87a90a..cbc541e 100644
|
||||
--- a/arch/arm/mach-imx/mach-layerscape.c
|
||||
+++ b/arch/arm/mach-imx/mach-layerscape.c
|
||||
@@ -12,11 +12,13 @@
|
||||
#include "common.h"
|
||||
|
||||
static const char * const layerscape_dt_compat[] __initconst = {
|
||||
- "fsl,ls1043a",
|
||||
"fsl,ls1012a",
|
||||
+ "fsl,ls1043a",
|
||||
+ "fsl,ls1046a",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(LAYERSCAPE, "Freescale LAYERSCAPE")
|
||||
+ .smp = smp_ops(layerscape_smp_ops),
|
||||
.dt_compat = layerscape_dt_compat,
|
||||
MACHINE_END
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
@ -0,0 +1,63 @@
|
||||
From 637a6e183edf302111b28461c0c98b9634b30437 Mon Sep 17 00:00:00 2001
|
||||
From: Mingkai Hu <mingkai.hu@nxp.com>
|
||||
Date: Fri, 1 Apr 2016 17:11:10 +0800
|
||||
Subject: [PATCH 126/141] net: phy: add driver for aquantia AQR106/107 phy
|
||||
|
||||
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
|
||||
---
|
||||
drivers/net/phy/aquantia.c | 30 ++++++++++++++++++++++++++++++
|
||||
1 file changed, 30 insertions(+)
|
||||
|
||||
--- a/drivers/net/phy/aquantia.c
|
||||
+++ b/drivers/net/phy/aquantia.c
|
||||
@@ -21,6 +21,8 @@
|
||||
#define PHY_ID_AQ1202 0x03a1b445
|
||||
#define PHY_ID_AQ2104 0x03a1b460
|
||||
#define PHY_ID_AQR105 0x03a1b4a2
|
||||
+#define PHY_ID_AQR106 0x03a1b4d0
|
||||
+#define PHY_ID_AQR107 0x03a1b4e0
|
||||
#define PHY_ID_AQR405 0x03a1b4b0
|
||||
|
||||
#define PHY_AQUANTIA_FEATURES (SUPPORTED_10000baseT_Full | \
|
||||
@@ -157,6 +159,32 @@ static struct phy_driver aquantia_driver
|
||||
.driver = { .owner = THIS_MODULE,},
|
||||
},
|
||||
{
|
||||
+ .phy_id = PHY_ID_AQR106,
|
||||
+ .phy_id_mask = 0xfffffff0,
|
||||
+ .name = "Aquantia AQR106",
|
||||
+ .features = PHY_AQUANTIA_FEATURES,
|
||||
+ .flags = PHY_HAS_INTERRUPT,
|
||||
+ .aneg_done = aquantia_aneg_done,
|
||||
+ .config_aneg = aquantia_config_aneg,
|
||||
+ .config_intr = aquantia_config_intr,
|
||||
+ .ack_interrupt = aquantia_ack_interrupt,
|
||||
+ .read_status = aquantia_read_status,
|
||||
+ .driver = { .owner = THIS_MODULE,},
|
||||
+},
|
||||
+{
|
||||
+ .phy_id = PHY_ID_AQR107,
|
||||
+ .phy_id_mask = 0xfffffff0,
|
||||
+ .name = "Aquantia AQR107",
|
||||
+ .features = PHY_AQUANTIA_FEATURES,
|
||||
+ .flags = PHY_HAS_INTERRUPT,
|
||||
+ .aneg_done = aquantia_aneg_done,
|
||||
+ .config_aneg = aquantia_config_aneg,
|
||||
+ .config_intr = aquantia_config_intr,
|
||||
+ .ack_interrupt = aquantia_ack_interrupt,
|
||||
+ .read_status = aquantia_read_status,
|
||||
+ .driver = { .owner = THIS_MODULE,},
|
||||
+},
|
||||
+{
|
||||
.phy_id = PHY_ID_AQR405,
|
||||
.phy_id_mask = 0xfffffff0,
|
||||
.name = "Aquantia AQR405",
|
||||
@@ -177,6 +205,8 @@ static struct mdio_device_id __maybe_unu
|
||||
{ PHY_ID_AQ1202, 0xfffffff0 },
|
||||
{ PHY_ID_AQ2104, 0xfffffff0 },
|
||||
{ PHY_ID_AQR105, 0xfffffff0 },
|
||||
+ { PHY_ID_AQR106, 0xfffffff0 },
|
||||
+ { PHY_ID_AQR107, 0xfffffff0 },
|
||||
{ PHY_ID_AQR405, 0xfffffff0 },
|
||||
{ }
|
||||
};
|
||||
@ -0,0 +1,63 @@
|
||||
From 228d15f0c525d1d62540539ebb8d311feddb79f5 Mon Sep 17 00:00:00 2001
|
||||
From: Akinobu Mita <akinobu.mita@gmail.com>
|
||||
Date: Mon, 26 Sep 2016 11:26:11 +0800
|
||||
Subject: [PATCH 125/141] rtc: pcf2127: add pcf2129 device id
|
||||
|
||||
commit e8bf83a7f9454ed1026f100139ebd10eace0e280
|
||||
[context adjustment]
|
||||
|
||||
There are only a few differences between PCF2127 and PCF2129 (PCF2127
|
||||
has 512 bytes of general purpose SRAM and count-down timer).
|
||||
|
||||
The rtc-pcf2127 driver currently doesn't use the PCF2127 specific
|
||||
functionality and Kconfig help text already says this driver supports
|
||||
PCF2127/29, so we can simply add pcf2129 to device id list.
|
||||
|
||||
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
|
||||
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
|
||||
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
|
||||
Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
|
||||
---
|
||||
drivers/rtc/rtc-pcf2127.c | 8 +++++---
|
||||
1 file changed, 5 insertions(+), 3 deletions(-)
|
||||
|
||||
--- a/drivers/rtc/rtc-pcf2127.c
|
||||
+++ b/drivers/rtc/rtc-pcf2127.c
|
||||
@@ -1,12 +1,12 @@
|
||||
/*
|
||||
- * An I2C driver for the NXP PCF2127 RTC
|
||||
+ * An I2C and SPI driver for the NXP PCF2127/29 RTC
|
||||
* Copyright 2013 Til-Technologies
|
||||
*
|
||||
* Author: Renaud Cerrato <r.cerrato@til-technologies.fr>
|
||||
*
|
||||
* based on the other drivers in this same directory.
|
||||
*
|
||||
- * http://www.nxp.com/documents/data_sheet/PCF2127AT.pdf
|
||||
+ * Datasheet: http://cache.nxp.com/documents/data_sheet/PCF2127.pdf
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
@@ -216,6 +216,7 @@ static int pcf2127_probe(struct i2c_clie
|
||||
|
||||
static const struct i2c_device_id pcf2127_id[] = {
|
||||
{ "pcf2127", 0 },
|
||||
+ { "pcf2129", 0 },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(i2c, pcf2127_id);
|
||||
@@ -223,6 +224,7 @@ MODULE_DEVICE_TABLE(i2c, pcf2127_id);
|
||||
#ifdef CONFIG_OF
|
||||
static const struct of_device_id pcf2127_of_match[] = {
|
||||
{ .compatible = "nxp,pcf2127" },
|
||||
+ { .compatible = "nxp,pcf2129" },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, pcf2127_of_match);
|
||||
@@ -240,5 +242,5 @@ static struct i2c_driver pcf2127_driver
|
||||
module_i2c_driver(pcf2127_driver);
|
||||
|
||||
MODULE_AUTHOR("Renaud Cerrato <r.cerrato@til-technologies.fr>");
|
||||
-MODULE_DESCRIPTION("NXP PCF2127 RTC driver");
|
||||
+MODULE_DESCRIPTION("NXP PCF2127/29 RTC driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
@ -0,0 +1,25 @@
|
||||
From 51ab89c787184d47dbff37c3c69ea2c82cc4749c Mon Sep 17 00:00:00 2001
|
||||
From: Mingkai Hu <mingkai.hu@nxp.com>
|
||||
Date: Mon, 26 Sep 2016 12:13:56 +0800
|
||||
Subject: [PATCH 127/141] ls1046a/msi: Add LS1046A MSI support
|
||||
|
||||
commit 2b5a00d46a8f8762b9f78b727eab6fc0e12f3fd7
|
||||
[context adjustment]
|
||||
|
||||
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
|
||||
Integated-by: Zhao Qiang <qiang.zhao@nxp.com>
|
||||
Integated-by: Yutang Jiang <yutang.jiang@nxp.com>
|
||||
---
|
||||
drivers/irqchip/irq-ls-scfg-msi.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/drivers/irqchip/irq-ls-scfg-msi.c
|
||||
+++ b/drivers/irqchip/irq-ls-scfg-msi.c
|
||||
@@ -222,6 +222,7 @@ static const struct of_device_id ls_scfg
|
||||
{ .compatible = "fsl,ls1012a-msi", },
|
||||
{ .compatible = "fsl,1s1021a-msi", },
|
||||
{ .compatible = "fsl,1s1043a-msi", },
|
||||
+ { .compatible = "fsl,ls1046a-msi", },
|
||||
{},
|
||||
};
|
||||
|
||||
@ -0,0 +1,38 @@
|
||||
From 5a95e58e58da417ca8a8f4ae11347ad9a66803cd Mon Sep 17 00:00:00 2001
|
||||
From: Mingkai Hu <mingkai.hu@nxp.com>
|
||||
Date: Mon, 26 Sep 2016 12:17:36 +0800
|
||||
Subject: [PATCH 128/141] pci/layerscape: add LS1046A support
|
||||
|
||||
commit a52797fe443a79c53d0b63c505c99f65264de8b7
|
||||
[context adjustment]
|
||||
|
||||
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
|
||||
Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
|
||||
Integrated-by: Yutang Jiang <yutang.jiang@nxp.com>
|
||||
---
|
||||
drivers/pci/host/pci-layerscape.c | 7 +++++++
|
||||
1 file changed, 7 insertions(+)
|
||||
|
||||
--- a/drivers/pci/host/pci-layerscape.c
|
||||
+++ b/drivers/pci/host/pci-layerscape.c
|
||||
@@ -205,6 +205,12 @@ static struct ls_pcie_drvdata ls1043_drv
|
||||
.ops = &ls_pcie_host_ops,
|
||||
};
|
||||
|
||||
+static struct ls_pcie_drvdata ls1046_drvdata = {
|
||||
+ .lut_offset = 0x10000,
|
||||
+ .ltssm_shift = 24,
|
||||
+ .ops = &ls_pcie_host_ops,
|
||||
+};
|
||||
+
|
||||
static struct ls_pcie_drvdata ls2080_drvdata = {
|
||||
.lut_offset = 0x80000,
|
||||
.ltssm_shift = 0,
|
||||
@@ -215,6 +221,7 @@ static const struct of_device_id ls_pcie
|
||||
{ .compatible = "fsl,ls1012a-pcie", .data = &ls1012_drvdata },
|
||||
{ .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
|
||||
{ .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
|
||||
+ { .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
|
||||
{ .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
|
||||
{ .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
|
||||
{ },
|
||||
@ -0,0 +1,75 @@
|
||||
From 4fe33d4f4dc608fc5013390db58df06723282d01 Mon Sep 17 00:00:00 2001
|
||||
From: Mingkai Hu <mingkai.hu@nxp.com>
|
||||
Date: Thu, 2 Jun 2016 11:15:58 +0800
|
||||
Subject: [PATCH 129/141] clk: qoriq: add ls1046a support
|
||||
|
||||
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
|
||||
Integated-by: Yutang Jiang <yutang.jiang@nxp.com>
|
||||
---
|
||||
drivers/clk/clk-qoriq.c | 41 +++++++++++++++++++++++++++++++++++++++++
|
||||
1 file changed, 41 insertions(+)
|
||||
|
||||
--- a/drivers/clk/clk-qoriq.c
|
||||
+++ b/drivers/clk/clk-qoriq.c
|
||||
@@ -275,6 +275,31 @@ static const struct clockgen_muxinfo ls1
|
||||
},
|
||||
};
|
||||
|
||||
+static const struct clockgen_muxinfo ls1046a_hwa1 = {
|
||||
+ {
|
||||
+ {},
|
||||
+ {},
|
||||
+ { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
|
||||
+ { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
|
||||
+ { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
|
||||
+ { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
|
||||
+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
|
||||
+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static const struct clockgen_muxinfo ls1046a_hwa2 = {
|
||||
+ {
|
||||
+ {},
|
||||
+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
|
||||
+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
|
||||
+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
|
||||
+ {},
|
||||
+ {},
|
||||
+ { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
static const struct clockgen_muxinfo t1023_hwa1 = {
|
||||
{
|
||||
{},
|
||||
@@ -508,6 +533,21 @@ static const struct clockgen_chipinfo ch
|
||||
.flags = CG_PLL_8BIT,
|
||||
},
|
||||
{
|
||||
+ .compat = "fsl,ls1046a-clockgen",
|
||||
+ .init_periph = t2080_init_periph,
|
||||
+ .cmux_groups = {
|
||||
+ &t1040_cmux
|
||||
+ },
|
||||
+ .hwaccel = {
|
||||
+ &ls1046a_hwa1, &ls1046a_hwa2
|
||||
+ },
|
||||
+ .cmux_to_group = {
|
||||
+ 0, -1
|
||||
+ },
|
||||
+ .pll_mask = 0x07,
|
||||
+ .flags = CG_PLL_8BIT,
|
||||
+ },
|
||||
+ {
|
||||
.compat = "fsl,ls2080a-clockgen",
|
||||
.cmux_groups = {
|
||||
&clockgen2_cmux_cga12, &clockgen2_cmux_cgb
|
||||
@@ -1285,6 +1325,7 @@ CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qo
|
||||
CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
|
||||
CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
|
||||
CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
|
||||
+CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
|
||||
CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
|
||||
CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
|
||||
|
||||
@ -0,0 +1,53 @@
|
||||
From 5cd461cd17c3e27e5501e499d5d865b60ee58257 Mon Sep 17 00:00:00 2001
|
||||
From: Gong Qianyu <Qianyu.Gong@nxp.com>
|
||||
Date: Mon, 26 Sep 2016 12:29:24 +0800
|
||||
Subject: [PATCH 130/141] ls1046a/sata: Add LS1046A sata support
|
||||
|
||||
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
|
||||
Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
|
||||
Integated-by: Yutang Jiang <yutang.jiang@nxp.com>
|
||||
---
|
||||
drivers/ata/ahci_qoriq.c | 13 +++++++++++++
|
||||
1 file changed, 13 insertions(+)
|
||||
|
||||
--- a/drivers/ata/ahci_qoriq.c
|
||||
+++ b/drivers/ata/ahci_qoriq.c
|
||||
@@ -40,11 +40,16 @@
|
||||
#define AHCI_PORT_PHY_5_CFG 0x192c96a4
|
||||
#define AHCI_PORT_TRANS_CFG 0x08000025
|
||||
|
||||
+/* for ls1046a */
|
||||
+#define LS1046A_PORT_PHY2 0x28184d1f
|
||||
+#define LS1046A_PORT_PHY3 0x0e081509
|
||||
+
|
||||
#define SATA_ECC_DISABLE 0x00020000
|
||||
|
||||
enum ahci_qoriq_type {
|
||||
AHCI_LS1021A,
|
||||
AHCI_LS1043A,
|
||||
+ AHCI_LS1046A,
|
||||
AHCI_LS2080A,
|
||||
};
|
||||
|
||||
@@ -57,6 +62,7 @@ struct ahci_qoriq_priv {
|
||||
static const struct of_device_id ahci_qoriq_of_match[] = {
|
||||
{ .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
|
||||
{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
|
||||
+ { .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
|
||||
{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
|
||||
{},
|
||||
};
|
||||
@@ -158,6 +164,13 @@ static int ahci_qoriq_phy_init(struct ah
|
||||
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
|
||||
break;
|
||||
|
||||
+ case AHCI_LS1046A:
|
||||
+ writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
|
||||
+ writel(LS1046A_PORT_PHY2, reg_base + PORT_PHY2);
|
||||
+ writel(LS1046A_PORT_PHY3, reg_base + PORT_PHY3);
|
||||
+ writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
|
||||
+ break;
|
||||
+
|
||||
case AHCI_LS1043A:
|
||||
case AHCI_LS2080A:
|
||||
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
|
||||
@ -0,0 +1,67 @@
|
||||
From 57d147c02fdcbae5e61ba322d51c5734f9511fd7 Mon Sep 17 00:00:00 2001
|
||||
From: Mingkai Hu <mingkai.hu@nxp.com>
|
||||
Date: Mon, 26 Sep 2016 14:19:32 +0800
|
||||
Subject: [PATCH 134/141] pci/layerscape: add LUT DBG reigster offset member
|
||||
|
||||
commit 59ab37d6f46356a5b9755fcec74b23616dfdd62f
|
||||
[doesn't apply pm part]
|
||||
|
||||
Different chip have different LUT debug register offset,
|
||||
so add a member to avoid macro redifinition.
|
||||
|
||||
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
|
||||
Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
|
||||
Integrated-by: Yutang Jiang <yutang.jiang@nxp.com>
|
||||
---
|
||||
drivers/pci/host/pci-layerscape.c | 8 ++++++--
|
||||
1 file changed, 6 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/pci/host/pci-layerscape.c
|
||||
+++ b/drivers/pci/host/pci-layerscape.c
|
||||
@@ -41,6 +41,7 @@
|
||||
struct ls_pcie_drvdata {
|
||||
u32 lut_offset;
|
||||
u32 ltssm_shift;
|
||||
+ u32 lut_dbg;
|
||||
struct pcie_host_ops *ops;
|
||||
};
|
||||
|
||||
@@ -134,7 +135,7 @@ static int ls_pcie_link_up(struct pcie_p
|
||||
struct ls_pcie *pcie = to_ls_pcie(pp);
|
||||
u32 state;
|
||||
|
||||
- state = (ioread32(pcie->lut + PCIE_LUT_DBG) >>
|
||||
+ state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >>
|
||||
pcie->drvdata->ltssm_shift) &
|
||||
LTSSM_STATE_MASK;
|
||||
|
||||
@@ -196,24 +197,28 @@ static struct ls_pcie_drvdata ls1021_drvdata = {
|
||||
static struct ls_pcie_drvdata ls1012_drvdata = {
|
||||
.lut_offset = 0xC0000,
|
||||
.ltssm_shift = 24,
|
||||
+ .lut_dbg = 0x7fc,
|
||||
.ops = &ls_pcie_host_ops,
|
||||
};
|
||||
|
||||
static struct ls_pcie_drvdata ls1043_drvdata = {
|
||||
.lut_offset = 0x10000,
|
||||
.ltssm_shift = 24,
|
||||
+ .lut_dbg = 0x7fc,
|
||||
.ops = &ls_pcie_host_ops,
|
||||
};
|
||||
|
||||
static struct ls_pcie_drvdata ls1046_drvdata = {
|
||||
- .lut_offset = 0x10000,
|
||||
+ .lut_offset = 0x80000,
|
||||
.ltssm_shift = 24,
|
||||
+ .lut_dbg = 0x407fc,
|
||||
.ops = &ls_pcie_host_ops,
|
||||
};
|
||||
|
||||
static struct ls_pcie_drvdata ls2080_drvdata = {
|
||||
.lut_offset = 0x80000,
|
||||
.ltssm_shift = 0,
|
||||
+ .lut_dbg = 0x7fc,
|
||||
.ops = &ls_pcie_host_ops,
|
||||
};
|
||||
|
||||
@ -0,0 +1,259 @@
|
||||
From b0e74277164b17bb0d207ffe16056e13e558f6ba Mon Sep 17 00:00:00 2001
|
||||
From: Zhao Qiang <qiang.zhao@nxp.com>
|
||||
Date: Tue, 11 Oct 2016 16:25:07 +0800
|
||||
Subject: [PATCH 138/141] pci-layerscape: add MSI interrupt support
|
||||
|
||||
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
|
||||
---
|
||||
drivers/iommu/amd_iommu.c | 5 +++--
|
||||
drivers/iommu/arm-smmu.c | 21 ++++++++++++++++++
|
||||
drivers/iommu/iommu.c | 8 +++----
|
||||
drivers/pci/host/pci-layerscape.c | 43 +++++++++++++++++++++++++++++++++++++
|
||||
drivers/pci/host/pci-layerscape.h | 17 +++++++++++++++
|
||||
drivers/pci/quirks.c | 19 +++++++++-------
|
||||
drivers/pci/search.c | 5 ++---
|
||||
include/linux/pci.h | 6 +++---
|
||||
8 files changed, 104 insertions(+), 20 deletions(-)
|
||||
create mode 100644 drivers/pci/host/pci-layerscape.h
|
||||
|
||||
--- a/drivers/iommu/amd_iommu.c
|
||||
+++ b/drivers/iommu/amd_iommu.c
|
||||
@@ -222,8 +222,9 @@ static u16 get_alias(struct device *dev)
|
||||
*/
|
||||
if (pci_alias == devid &&
|
||||
PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
|
||||
- pdev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
|
||||
- pdev->dma_alias_devfn = ivrs_alias & 0xff;
|
||||
+ pdev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVID;
|
||||
+ pdev->dma_alias_devid = PCI_DEVID(pdev->bus->number,
|
||||
+ ivrs_alias & 0xff);
|
||||
pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
|
||||
PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
|
||||
dev_name(dev));
|
||||
--- a/drivers/iommu/arm-smmu.c
|
||||
+++ b/drivers/iommu/arm-smmu.c
|
||||
@@ -45,6 +45,10 @@
|
||||
|
||||
#include <linux/amba/bus.h>
|
||||
|
||||
+#ifdef CONFIG_PCI_LAYERSCAPE
|
||||
+#include <../drivers/pci/host/pci-layerscape.h>
|
||||
+#endif
|
||||
+
|
||||
#include "io-pgtable.h"
|
||||
|
||||
/* Maximum number of stream IDs assigned to a single device */
|
||||
@@ -1352,6 +1356,23 @@ static int arm_smmu_init_platform_device
|
||||
static int arm_smmu_add_device(struct device *dev)
|
||||
{
|
||||
struct iommu_group *group;
|
||||
+#ifdef CONFIG_PCI_LAYERSCAPE
|
||||
+ u16 sid;
|
||||
+ u32 streamid;
|
||||
+ struct pci_dev *pdev;
|
||||
+ if (dev_is_pci(dev)) {
|
||||
+ pdev = to_pci_dev(dev);
|
||||
+
|
||||
+ pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid, &sid);
|
||||
+ streamid = set_pcie_streamid_translation(pdev, sid);
|
||||
+ if (~streamid == 0) {
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+
|
||||
+ pdev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVID;
|
||||
+ pdev->dma_alias_devid = streamid;
|
||||
+ }
|
||||
+#endif
|
||||
|
||||
group = iommu_group_get_for_dev(dev);
|
||||
if (IS_ERR(group))
|
||||
--- a/drivers/iommu/iommu.c
|
||||
+++ b/drivers/iommu/iommu.c
|
||||
@@ -686,10 +686,10 @@ static struct iommu_group *get_pci_alias
|
||||
continue;
|
||||
|
||||
/* We alias them or they alias us */
|
||||
- if (((pdev->dev_flags & PCI_DEV_FLAGS_DMA_ALIAS_DEVFN) &&
|
||||
- pdev->dma_alias_devfn == tmp->devfn) ||
|
||||
- ((tmp->dev_flags & PCI_DEV_FLAGS_DMA_ALIAS_DEVFN) &&
|
||||
- tmp->dma_alias_devfn == pdev->devfn)) {
|
||||
+ if (((pdev->dev_flags & PCI_DEV_FLAGS_DMA_ALIAS_DEVID) &&
|
||||
+ (pdev->dma_alias_devid & 0xff) == tmp->devfn) ||
|
||||
+ ((tmp->dev_flags & PCI_DEV_FLAGS_DMA_ALIAS_DEVID) &&
|
||||
+ (tmp->dma_alias_devid & 0xff) == pdev->devfn)) {
|
||||
|
||||
group = get_pci_alias_group(tmp, devfns);
|
||||
if (group) {
|
||||
--- a/drivers/pci/host/pci-layerscape.c
|
||||
+++ b/drivers/pci/host/pci-layerscape.c
|
||||
@@ -37,6 +37,11 @@
|
||||
|
||||
/* PEX LUT registers */
|
||||
#define PCIE_LUT_DBG 0x7FC /* PEX LUT Debug Register */
|
||||
+#define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
|
||||
+#define PCIE_LUT_LDR(n) (0x804 + (n) * 8)
|
||||
+#define PCIE_LUT_MASK_ALL 0xffff
|
||||
+#define PCIE_LUT_DR_NUM 32
|
||||
+#define PCIE_LUT_ENABLE (1 << 31)
|
||||
|
||||
struct ls_pcie_drvdata {
|
||||
u32 lut_offset;
|
||||
@@ -52,10 +57,30 @@ struct ls_pcie {
|
||||
struct pcie_port pp;
|
||||
const struct ls_pcie_drvdata *drvdata;
|
||||
int index;
|
||||
+ const u32 *avail_streamids;
|
||||
+ int streamid_index;
|
||||
};
|
||||
|
||||
#define to_ls_pcie(x) container_of(x, struct ls_pcie, pp)
|
||||
|
||||
+u32 set_pcie_streamid_translation(struct pci_dev *pdev, u32 devid)
|
||||
+{
|
||||
+ u32 index, streamid;
|
||||
+ struct pcie_port *pp = pdev->bus->sysdata;
|
||||
+ struct ls_pcie *pcie = to_ls_pcie(pp);
|
||||
+
|
||||
+ if (!pcie->avail_streamids || !pcie->streamid_index)
|
||||
+ return ~(u32)0;
|
||||
+
|
||||
+ index = --pcie->streamid_index;
|
||||
+ /* mask is set as all zeroes, want to match all bits */
|
||||
+ iowrite32((devid << 16), pcie->lut + PCIE_LUT_UDR(index));
|
||||
+ streamid = be32_to_cpup(&pcie->avail_streamids[index]);
|
||||
+ iowrite32(streamid | PCIE_LUT_ENABLE, pcie->lut + PCIE_LUT_LDR(index));
|
||||
+
|
||||
+ return streamid;
|
||||
+}
|
||||
+
|
||||
static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
|
||||
{
|
||||
u32 header_type;
|
||||
@@ -283,10 +308,28 @@ static int __init ls_pcie_probe(struct p
|
||||
|
||||
pcie->drvdata = match->data;
|
||||
pcie->lut = pcie->dbi + pcie->drvdata->lut_offset;
|
||||
+ /* Disable LDR zero */
|
||||
+ iowrite32(0, pcie->lut + PCIE_LUT_LDR(0));
|
||||
|
||||
if (!ls_pcie_is_bridge(pcie))
|
||||
return -ENODEV;
|
||||
|
||||
+ if (of_device_is_compatible(pdev->dev.of_node, "fsl,ls2085a-pcie") ||
|
||||
+ of_device_is_compatible(pdev->dev.of_node, "fsl,ls2080a-pcie") ||
|
||||
+ of_device_is_compatible(pdev->dev.of_node, "fsl,ls1088a-pcie")) {
|
||||
+ int len;
|
||||
+ const u32 *prop;
|
||||
+ struct device_node *np;
|
||||
+
|
||||
+ np = pdev->dev.of_node;
|
||||
+ prop = (u32 *)of_get_property(np, "available-stream-ids", &len);
|
||||
+ if (prop) {
|
||||
+ pcie->avail_streamids = prop;
|
||||
+ pcie->streamid_index = len/sizeof(u32);
|
||||
+ } else
|
||||
+ dev_err(&pdev->dev, "PCIe endpoint partitioning not possible\n");
|
||||
+ }
|
||||
+
|
||||
ret = ls_add_pcie_port(&pcie->pp, pdev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
--- /dev/null
|
||||
+++ b/drivers/pci/host/pci-layerscape.h
|
||||
@@ -0,0 +1,17 @@
|
||||
+/*
|
||||
+ * Copyright (C) 2015 Freescale Semiconductor.
|
||||
+ *
|
||||
+ * Author: Varun Sethi <Varun.Sethi@freescale.com>
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify
|
||||
+ * it under the terms of the GNU General Public License version 2 as
|
||||
+ * published by the Free Software Foundation.
|
||||
+ */
|
||||
+
|
||||
+#ifndef _PCI_LAYERSCAPE_H
|
||||
+#define _PCI_LAYERSCAPE_H
|
||||
+
|
||||
+/* function for setting up stream id to device id translation */
|
||||
+u32 set_pcie_streamid_translation(struct pci_dev *pdev, u32 devid);
|
||||
+
|
||||
+#endif /* _PCI_LAYERSCAPE_H */
|
||||
--- a/drivers/pci/quirks.c
|
||||
+++ b/drivers/pci/quirks.c
|
||||
@@ -3589,8 +3589,9 @@ int pci_dev_specific_reset(struct pci_de
|
||||
static void quirk_dma_func0_alias(struct pci_dev *dev)
|
||||
{
|
||||
if (PCI_FUNC(dev->devfn) != 0) {
|
||||
- dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0);
|
||||
- dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
|
||||
+ dev->dma_alias_devid = PCI_DEVID(dev->bus->number,
|
||||
+ PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
|
||||
+ dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVID;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -3605,8 +3606,9 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_R
|
||||
static void quirk_dma_func1_alias(struct pci_dev *dev)
|
||||
{
|
||||
if (PCI_FUNC(dev->devfn) != 1) {
|
||||
- dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 1);
|
||||
- dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
|
||||
+ dev->dma_alias_devid = PCI_DEVID(dev->bus->number,
|
||||
+ PCI_DEVFN(PCI_SLOT(dev->devfn), 1));
|
||||
+ dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVID;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -3670,11 +3672,12 @@ static void quirk_fixed_dma_alias(struct
|
||||
|
||||
id = pci_match_id(fixed_dma_alias_tbl, dev);
|
||||
if (id) {
|
||||
- dev->dma_alias_devfn = id->driver_data;
|
||||
- dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
|
||||
+ dev->dma_alias_devid = PCI_DEVID(dev->bus->number,
|
||||
+ id->driver_data);
|
||||
+ dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVID;
|
||||
dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n",
|
||||
- PCI_SLOT(dev->dma_alias_devfn),
|
||||
- PCI_FUNC(dev->dma_alias_devfn));
|
||||
+ PCI_SLOT(dev->dma_alias_devid),
|
||||
+ PCI_FUNC(dev->dma_alias_devid));
|
||||
}
|
||||
}
|
||||
|
||||
--- a/drivers/pci/search.c
|
||||
+++ b/drivers/pci/search.c
|
||||
@@ -40,9 +40,8 @@ int pci_for_each_dma_alias(struct pci_de
|
||||
* If the device is broken and uses an alias requester ID for
|
||||
* DMA, iterate over that too.
|
||||
*/
|
||||
- if (unlikely(pdev->dev_flags & PCI_DEV_FLAGS_DMA_ALIAS_DEVFN)) {
|
||||
- ret = fn(pdev, PCI_DEVID(pdev->bus->number,
|
||||
- pdev->dma_alias_devfn), data);
|
||||
+ if (unlikely(pdev->dev_flags & PCI_DEV_FLAGS_DMA_ALIAS_DEVID)) {
|
||||
+ ret = fn(pdev, pdev->dma_alias_devid, data);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
--- a/include/linux/pci.h
|
||||
+++ b/include/linux/pci.h
|
||||
@@ -172,8 +172,8 @@ enum pci_dev_flags {
|
||||
PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
|
||||
/* Flag for quirk use to store if quirk-specific ACS is enabled */
|
||||
PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
|
||||
- /* Flag to indicate the device uses dma_alias_devfn */
|
||||
- PCI_DEV_FLAGS_DMA_ALIAS_DEVFN = (__force pci_dev_flags_t) (1 << 4),
|
||||
+ /* Flag to indicate the device uses dma_alias_devid */
|
||||
+ PCI_DEV_FLAGS_DMA_ALIAS_DEVID = (__force pci_dev_flags_t) (1 << 4),
|
||||
/* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
|
||||
PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
|
||||
/* Do not use bus resets for device */
|
||||
@@ -279,7 +279,7 @@ struct pci_dev {
|
||||
u8 rom_base_reg; /* which config register controls the ROM */
|
||||
u8 pin; /* which interrupt pin this device uses */
|
||||
u16 pcie_flags_reg; /* cached PCIe Capabilities Register */
|
||||
- u8 dma_alias_devfn;/* devfn of DMA alias, if any */
|
||||
+ u32 dma_alias_devid;/* devid of DMA alias */
|
||||
|
||||
struct pci_driver *driver; /* which driver has allocated this device */
|
||||
u64 dma_mask; /* Mask of the bits of bus address this
|
||||
@ -0,0 +1,25 @@
|
||||
From 81c67bb120106c4fbd9b7191ab057b48e13e3e5e Mon Sep 17 00:00:00 2001
|
||||
From: Yutang Jiang <yutang.jiang@nxp.com>
|
||||
Date: Tue, 8 Nov 2016 01:27:50 +0800
|
||||
Subject: [PATCH 142/142] drivers/mmc: Add compatible string for LS1046A
|
||||
|
||||
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
|
||||
---
|
||||
drivers/mmc/host/sdhci-of-esdhc.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
|
||||
index a04ed4e..1116d38 100644
|
||||
--- a/drivers/mmc/host/sdhci-of-esdhc.c
|
||||
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
|
||||
@@ -607,6 +607,7 @@ static int sdhci_esdhc_probe(struct platform_device *pdev)
|
||||
of_device_is_compatible(np, "fsl,p4080-esdhc") ||
|
||||
of_device_is_compatible(np, "fsl,p1020-esdhc") ||
|
||||
of_device_is_compatible(np, "fsl,t1040-esdhc") ||
|
||||
+ of_device_is_compatible(np, "fsl,ls1046a-esdhc") ||
|
||||
of_device_is_compatible(np, "fsl,ls1021a-esdhc"))
|
||||
host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
|
||||
|
||||
--
|
||||
1.7.9.5
|
||||
|
||||
Loading…
Reference in New Issue