mediatek: add mt7531 DSA support

Signed-off-by: John Crispin <john@phrozen.org>
master
John Crispin 4 years ago
parent f72a2b004c
commit ad39d06df7

@ -53,13 +53,6 @@
};
};
gsw: gsw@0 {
compatible = "mediatek,mt753x";
mediatek,ethsys = <&ethsys>;
#address-cells = <1>;
#size-cells = <0>;
};
leds {
compatible = "gpio-leds";
@ -150,37 +143,57 @@
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
};
};
&gsw {
mediatek,mdio = <&mdio>;
mediatek,portmap = "wllll";
mediatek,mdio_master_pinmux = <0>;
reset-gpios = <&pio 54 0>;
interrupt-parent = <&pio>;
interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
port5: port@5 {
compatible = "mediatek,mt753x-port";
reg = <5>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
port6: port@6 {
compatible = "mediatek,mt753x-port";
reg = <6>;
phy-mode = "sgmii";
fixed-link {
speed = <2500>;
full-duplex;
};
};
switch@1f {
compatible = "mediatek,mt7531";
reg = <0x1f>;
reset-gpios = <&pio 54 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
wan: port@0 {
reg = <0>;
label = "wan";
};
port@1 {
reg = <1>;
label = "lan0";
};
port@2 {
reg = <2>;
label = "lan1";
};
port@3 {
reg = <3>;
label = "lan2";
};
port@4 {
reg = <4>;
label = "lan3";
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
};
};
&i2c1 {

@ -9,6 +9,10 @@ mediatek_setup_interfaces()
local board="$1"
case $board in
bananapi,bpi-r64-rootdisk|\
bananapi,bpi-r64)
ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" wan
;;
*)
ucidef_add_switch "switch0" \
"0:lan" "1:lan" "2:lan" "3:lan" "4:wan" "6u@eth0" "5u@eth1"

@ -393,7 +393,7 @@ CONFIG_MMC_MTK=y
# CONFIG_MMC_TIFM_SD is not set
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_MT753X_GSW=y
# CONFIG_MT753X_GSW is not set
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
CONFIG_MTD_NAND_MTK=y
@ -415,8 +415,13 @@ CONFIG_MTK_TIMER=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NET_DEVLINK=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_MT7530=y
CONFIG_NET_DSA_TAG_MTK=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_MEDIATEK_SOC=y
CONFIG_NET_SWITCHDEV=y
CONFIG_NET_VENDOR_MEDIATEK=y
CONFIG_NLS=y
CONFIG_NO_HZ_COMMON=y

@ -0,0 +1,100 @@
From patchwork Tue Dec 10 08:14:37 2019
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
X-Patchwork-Submitter: Landen Chao <landen.chao@mediatek.com>
X-Patchwork-Id: 1206962
X-Patchwork-Delegate: davem@davemloft.net
Return-Path: <netdev-owner@vger.kernel.org>
X-Original-To: patchwork-incoming-netdev@ozlabs.org
Delivered-To: patchwork-incoming-netdev@ozlabs.org
Authentication-Results: ozlabs.org; spf=none (no SPF record)
smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67;
helo=vger.kernel.org;
envelope-from=netdev-owner@vger.kernel.org;
receiver=<UNKNOWN>)
Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none)
header.from=mediatek.com
Authentication-Results: ozlabs.org; dkim=pass (1024-bit key;
unprotected) header.d=mediatek.com header.i=@mediatek.com
header.b="pTp2PPKi"; dkim-atps=neutral
Received: from vger.kernel.org (vger.kernel.org [209.132.180.67])
by ozlabs.org (Postfix) with ESMTP id 47XCY42hJqz9sRf
for <patchwork-incoming-netdev@ozlabs.org>;
Tue, 10 Dec 2019 19:15:20 +1100 (AEDT)
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
id S1727061AbfLJIO5 (ORCPT
<rfc822;patchwork-incoming-netdev@ozlabs.org>);
Tue, 10 Dec 2019 03:14:57 -0500
Received: from mailgw02.mediatek.com ([210.61.82.184]:45567 "EHLO
mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by
vger.kernel.org with ESMTP id S1726932AbfLJIO4 (ORCPT
<rfc822;netdev@vger.kernel.org>); Tue, 10 Dec 2019 03:14:56 -0500
X-UUID: f5656f2ff80846ebb40e3da87d60fb90-20191210
DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;
d=mediatek.com; s=dk;
h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From;
bh=THbuVAlbiUyMgTyO0rwrKX/mskzsxNwDv9gxXp2O2c8=;
b=pTp2PPKiPwR8QPOOf5yohf9lFERpEDlo/g/t2ChREfzFb9c+wylx++/div4hAB337+Ja2KIzbSu4URgdj5XHXUly8yuxrD8OBvV+ox0jlNLiRIN2dkCgL4fyzPr7ZPSk9lObJW05Yx2LY6Jy6eJZZXSShLlqLd0lDKwy6FT+hSI=;
X-UUID: f5656f2ff80846ebb40e3da87d60fb90-20191210
Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by
mailgw02.mediatek.com (envelope-from <landen.chao@mediatek.com>)
(Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS)
with ESMTP id 565263134; Tue, 10 Dec 2019 16:14:47 +0800
Received: from mtkcas08.mediatek.inc (172.21.101.126) by
mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server
(TLS) id 15.0.1395.4; Tue, 10 Dec 2019 16:14:38 +0800
Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc
(172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via
Frontend Transport; Tue, 10 Dec 2019 16:14:26 +0800
From: Landen Chao <landen.chao@mediatek.com>
To: <andrew@lunn.ch>, <f.fainelli@gmail.com>,
<vivien.didelot@savoirfairelinux.com>, <matthias.bgg@gmail.com>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>
CC: <devicetree@vger.kernel.org>, <netdev@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>, <davem@davemloft.net>,
<sean.wang@mediatek.com>, <opensource@vdorst.com>,
<frank-w@public-files.de>, Landen Chao <landen.chao@mediatek.com>
Subject: [PATCH net-next 1/6] net: dsa: mt7530: Refine message in Kconfig
Date: Tue, 10 Dec 2019 16:14:37 +0800
Message-ID: <6ecf6cbf38223f35854bc361c2eefa1d85c724d2.1575914275.git.landen.chao@mediatek.com>
X-Mailer: git-send-email 2.18.0
In-Reply-To: <cover.1575914275.git.landen.chao@mediatek.com>
References: <cover.1575914275.git.landen.chao@mediatek.com>
MIME-Version: 1.0
X-MTK: N
Sender: netdev-owner@vger.kernel.org
Precedence: bulk
List-ID: <netdev.vger.kernel.org>
X-Mailing-List: netdev@vger.kernel.org
Refine message in Kconfig with fixing typo and an explicit MT7621 support.
Signed-off-by: Landen Chao <landen.chao@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
---
drivers/net/dsa/Kconfig | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig
index c7667645f04a..467f80157acf 100644
--- a/drivers/net/dsa/Kconfig
+++ b/drivers/net/dsa/Kconfig
@@ -33,12 +33,12 @@ config NET_DSA_LANTIQ_GSWIP
the xrx200 / VR9 SoC.
config NET_DSA_MT7530
- tristate "Mediatek MT7530 Ethernet switch support"
+ tristate "MediaTek MT7530 and MT7621 Ethernet switch support"
depends on NET_DSA
select NET_DSA_TAG_MTK
---help---
- This enables support for the Mediatek MT7530 Ethernet switch
- chip.
+ This enables support for the MediaTek MT7530 and MT7621 Ethernet
+ switch chip.
config NET_DSA_MV88E6060
tristate "Marvell 88E6060 ethernet switch chip support"

@ -0,0 +1,445 @@
From patchwork Tue Dec 10 08:14:38 2019
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
X-Patchwork-Submitter: Landen Chao <landen.chao@mediatek.com>
X-Patchwork-Id: 1206963
X-Patchwork-Delegate: davem@davemloft.net
Return-Path: <netdev-owner@vger.kernel.org>
X-Original-To: patchwork-incoming-netdev@ozlabs.org
Delivered-To: patchwork-incoming-netdev@ozlabs.org
Authentication-Results: ozlabs.org; spf=none (no SPF record)
smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67;
helo=vger.kernel.org;
envelope-from=netdev-owner@vger.kernel.org;
receiver=<UNKNOWN>)
Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none)
header.from=mediatek.com
Authentication-Results: ozlabs.org; dkim=pass (1024-bit key;
unprotected) header.d=mediatek.com header.i=@mediatek.com
header.b="UJ5NATux"; dkim-atps=neutral
Received: from vger.kernel.org (vger.kernel.org [209.132.180.67])
by ozlabs.org (Postfix) with ESMTP id 47XCY92tBkz9sR7
for <patchwork-incoming-netdev@ozlabs.org>;
Tue, 10 Dec 2019 19:15:25 +1100 (AEDT)
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
id S1727003AbfLJIO4 (ORCPT
<rfc822;patchwork-incoming-netdev@ozlabs.org>);
Tue, 10 Dec 2019 03:14:56 -0500
Received: from mailgw02.mediatek.com ([210.61.82.184]:45567 "EHLO
mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by
vger.kernel.org with ESMTP id S1726071AbfLJIOy (ORCPT
<rfc822;netdev@vger.kernel.org>); Tue, 10 Dec 2019 03:14:54 -0500
X-UUID: a18674d7b33c423e9e67b7440f4771cf-20191210
DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;
d=mediatek.com; s=dk;
h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From;
bh=c2C/fEHYw/8uqadmiP2m2xa2hsUpAd52urXVJTPlYck=;
b=UJ5NATuxMtqHln5i6BTpWiLnxGKgWvp4DpRsKVO2xdnz2cJaT4XL8F/T5fK3CTF4nAai0EKPAcqp+rr8eCLq7uURJv5e5h+ZIzKLSAB4zgnchXesQLo0uFS8vs5w2yp49j6bez1z3v/uN+1+Lpq0uYid9awCqzvbnovrooEysu4=;
X-UUID: a18674d7b33c423e9e67b7440f4771cf-20191210
Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by
mailgw02.mediatek.com (envelope-from <landen.chao@mediatek.com>)
(Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS)
with ESMTP id 1965641267; Tue, 10 Dec 2019 16:14:46 +0800
Received: from mtkcas08.mediatek.inc (172.21.101.126) by
mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server
(TLS) id 15.0.1395.4; Tue, 10 Dec 2019 16:14:31 +0800
Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc
(172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via
Frontend Transport; Tue, 10 Dec 2019 16:14:26 +0800
From: Landen Chao <landen.chao@mediatek.com>
To: <andrew@lunn.ch>, <f.fainelli@gmail.com>,
<vivien.didelot@savoirfairelinux.com>, <matthias.bgg@gmail.com>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>
CC: <devicetree@vger.kernel.org>, <netdev@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>, <davem@davemloft.net>,
<sean.wang@mediatek.com>, <opensource@vdorst.com>,
<frank-w@public-files.de>, Landen Chao <landen.chao@mediatek.com>
Subject: [PATCH net-next 2/6] net: dsa: mt7530: Extend device data ready for
adding a new hardware
Date: Tue, 10 Dec 2019 16:14:38 +0800
Message-ID: <2d546d6bb15ff8b4b75af2220e20db4e634f4145.1575914275.git.landen.chao@mediatek.com>
X-Mailer: git-send-email 2.18.0
In-Reply-To: <cover.1575914275.git.landen.chao@mediatek.com>
References: <cover.1575914275.git.landen.chao@mediatek.com>
MIME-Version: 1.0
X-MTK: N
Sender: netdev-owner@vger.kernel.org
Precedence: bulk
List-ID: <netdev.vger.kernel.org>
X-Mailing-List: netdev@vger.kernel.org
Add a structure holding required operations for each device such as device
initialization, PHY port read or write, a checker whether PHY interface is
supported on a certain port, MAC port setup for either bus pad or a
specific PHY interface.
The patch is done for ready adding a new hardware MT7531.
Signed-off-by: Landen Chao <landen.chao@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
drivers/net/dsa/mt7530.c | 231 +++++++++++++++++++++++++++++----------
drivers/net/dsa/mt7530.h | 29 ++++-
2 files changed, 203 insertions(+), 57 deletions(-)
Index: linux-5.4.43/drivers/net/dsa/mt7530.c
===================================================================
--- linux-5.4.43.orig/drivers/net/dsa/mt7530.c
+++ linux-5.4.43/drivers/net/dsa/mt7530.c
@@ -373,7 +373,7 @@ mt7530_fdb_write(struct mt7530_priv *pri
}
static int
-mt7530_pad_clk_setup(struct dsa_switch *ds, int mode)
+mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t mode)
{
struct mt7530_priv *priv = ds->priv;
u32 ncpo1, ssc_delta, trgint, i, xtal;
@@ -1355,13 +1355,111 @@ mt7530_setup(struct dsa_switch *ds)
return 0;
}
-static void mt7530_phylink_mac_config(struct dsa_switch *ds, int port,
+static bool mt7530_phy_supported(struct dsa_switch *ds, int port,
+ const struct phylink_link_state *state)
+{
+ struct mt7530_priv *priv = ds->priv;
+
+ switch (port) {
+ case 0: /* Internal phy */
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ if (state->interface != PHY_INTERFACE_MODE_GMII)
+ goto unsupported;
+ break;
+ case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
+ if (!phy_interface_mode_is_rgmii(state->interface) &&
+ state->interface != PHY_INTERFACE_MODE_MII &&
+ state->interface != PHY_INTERFACE_MODE_GMII)
+ goto unsupported;
+ break;
+ case 6: /* 1st cpu port */
+ if (state->interface != PHY_INTERFACE_MODE_RGMII &&
+ state->interface != PHY_INTERFACE_MODE_TRGMII)
+ goto unsupported;
+ break;
+ default:
+ dev_err(priv->dev, "%s: unsupported port: %i\n", __func__,
+ port);
+ goto unsupported;
+ }
+
+ return true;
+
+unsupported:
+ return false;
+}
+
+static bool mt753x_phy_supported(struct dsa_switch *ds, int port,
+ const struct phylink_link_state *state)
+{
+ struct mt7530_priv *priv = ds->priv;
+
+ return priv->info->phy_supported(ds, port, state);
+}
+
+static int
+mt7530_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
+{
+ struct mt7530_priv *priv = ds->priv;
+
+ /* Setup TX circuit incluing relevant PAD and driving */
+ mt7530_pad_clk_setup(ds, state->interface);
+
+ if (priv->id == ID_MT7530) {
+ /* Setup RX circuit, relevant PAD and driving on the
+ * host which must be placed after the setup on the
+ * device side is all finished.
+ */
+ mt7623_pad_clk_setup(ds);
+ }
+
+ return 0;
+}
+
+static int
+mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
+{
+ struct mt7530_priv *priv = ds->priv;
+
+ return priv->info->pad_setup(ds, state);
+}
+
+static int
+mt7530_mac_setup(struct dsa_switch *ds, int port, unsigned int mode,
+ const struct phylink_link_state *state)
+{
+ struct mt7530_priv *priv = ds->priv;
+
+ /* Only need to setup port5. */
+ if (port != 5)
+ return 0;
+
+ mt7530_setup_port5(priv->ds, state->interface);
+
+ return 0;
+}
+
+static int mt753x_mac_setup(struct dsa_switch *ds, int port, unsigned int mode,
+ const struct phylink_link_state *state)
+{
+ struct mt7530_priv *priv = ds->priv;
+
+ return priv->info->mac_setup(ds, port, mode, state);
+}
+
+static void mt753x_phylink_mac_config(struct dsa_switch *ds, int port,
unsigned int mode,
const struct phylink_link_state *state)
{
struct mt7530_priv *priv = ds->priv;
u32 mcr_cur, mcr_new;
+ if (!mt753x_phy_supported(ds, port, state))
+ return;
+
switch (port) {
case 0: /* Internal phy */
case 1:
@@ -1374,24 +1472,15 @@ static void mt7530_phylink_mac_config(st
case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
if (priv->p5_interface == state->interface)
break;
- if (!phy_interface_mode_is_rgmii(state->interface) &&
- state->interface != PHY_INTERFACE_MODE_MII &&
- state->interface != PHY_INTERFACE_MODE_GMII)
- return;
-
- mt7530_setup_port5(ds, state->interface);
+ if (mt753x_mac_setup(ds, port, mode, state) < 0)
+ goto unsupported;
break;
case 6: /* 1st cpu port */
if (priv->p6_interface == state->interface)
break;
-
- if (state->interface != PHY_INTERFACE_MODE_RGMII &&
- state->interface != PHY_INTERFACE_MODE_TRGMII)
- return;
-
- /* Setup TX circuit incluing relevant PAD and driving */
- mt7530_pad_clk_setup(ds, state->interface);
-
+ mt753x_pad_setup(ds, state);
+ if (mt753x_mac_setup(ds, port, mode, state) < 0)
+ goto unsupported;
priv->p6_interface = state->interface;
break;
default:
@@ -1459,38 +1548,14 @@ static void mt7530_phylink_mac_link_up(s
mt7530_port_set_status(priv, port, 1);
}
-static void mt7530_phylink_validate(struct dsa_switch *ds, int port,
+static void mt753x_phylink_validate(struct dsa_switch *ds, int port,
unsigned long *supported,
struct phylink_link_state *state)
{
__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
- switch (port) {
- case 0: /* Internal phy */
- case 1:
- case 2:
- case 3:
- case 4:
- if (state->interface != PHY_INTERFACE_MODE_NA &&
- state->interface != PHY_INTERFACE_MODE_GMII)
- goto unsupported;
- break;
- case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
- if (state->interface != PHY_INTERFACE_MODE_NA &&
- !phy_interface_mode_is_rgmii(state->interface) &&
- state->interface != PHY_INTERFACE_MODE_MII &&
- state->interface != PHY_INTERFACE_MODE_GMII)
- goto unsupported;
- break;
- case 6: /* 1st cpu port */
- if (state->interface != PHY_INTERFACE_MODE_NA &&
- state->interface != PHY_INTERFACE_MODE_RGMII &&
- state->interface != PHY_INTERFACE_MODE_TRGMII)
- goto unsupported;
- break;
- default:
- dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
-unsupported:
+ if (state->interface != PHY_INTERFACE_MODE_NA &&
+ !mt753x_phy_supported(ds, port, state)) {
linkmode_zero(supported);
return;
}
@@ -1609,12 +1674,36 @@ static int mt7530_set_mac_eee(struct dsa
return 0;
}
+static int
+mt753x_setup(struct dsa_switch *ds)
+{
+ struct mt7530_priv *priv = ds->priv;
+
+ return priv->info->setup(ds);
+}
+
+static int
+mt753x_phy_read(struct dsa_switch *ds, int port, int regnum)
+{
+ struct mt7530_priv *priv = ds->priv;
+
+ return priv->info->phy_read(ds, port, regnum);
+}
+
+static int
+mt753x_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
+{
+ struct mt7530_priv *priv = ds->priv;
+
+ return priv->info->phy_write(ds, port, regnum, val);
+}
+
static const struct dsa_switch_ops mt7530_switch_ops = {
.get_tag_protocol = mtk_get_tag_protocol,
- .setup = mt7530_setup,
+ .setup = mt753x_setup,
.get_strings = mt7530_get_strings,
- .phy_read = mt7530_phy_read,
- .phy_write = mt7530_phy_write,
+ .phy_read = mt753x_phy_read,
+ .phy_write = mt753x_phy_write,
.get_ethtool_stats = mt7530_get_ethtool_stats,
.get_sset_count = mt7530_get_sset_count,
.port_enable = mt7530_port_enable,
@@ -1631,18 +1720,39 @@ static const struct dsa_switch_ops mt753
.port_vlan_del = mt7530_port_vlan_del,
.port_mirror_add = mt7530_port_mirror_add,
.port_mirror_del = mt7530_port_mirror_del,
- .phylink_validate = mt7530_phylink_validate,
+ .phylink_validate = mt753x_phylink_validate,
.phylink_mac_link_state = mt7530_phylink_mac_link_state,
- .phylink_mac_config = mt7530_phylink_mac_config,
+ .phylink_mac_config = mt753x_phylink_mac_config,
.phylink_mac_link_down = mt7530_phylink_mac_link_down,
.phylink_mac_link_up = mt7530_phylink_mac_link_up,
.get_mac_eee = mt7530_get_mac_eee,
.set_mac_eee = mt7530_set_mac_eee,
};
-static const struct of_device_id mt7530_of_match[] = {
- { .compatible = "mediatek,mt7621", .data = (void *)ID_MT7621, },
- { .compatible = "mediatek,mt7530", .data = (void *)ID_MT7530, },
+static const struct mt753x_info mt753x_table[] = {
+ [ID_MT7621] = {
+ .id = ID_MT7621,
+ .setup = mt7530_setup,
+ .phy_read = mt7530_phy_read,
+ .phy_write = mt7530_phy_write,
+ .phy_supported = mt7530_phy_supported,
+ .pad_setup = mt7530_pad_setup,
+ .mac_setup = mt7530_mac_setup,
+ },
+ [ID_MT7530] = {
+ .id = ID_MT7530,
+ .setup = mt7530_setup,
+ .phy_read = mt7530_phy_read,
+ .phy_write = mt7530_phy_write,
+ .phy_supported = mt7530_phy_supported,
+ .pad_setup = mt7530_pad_setup,
+ .mac_setup = mt7530_mac_setup,
+ },
+};
+
+ static const struct of_device_id mt7530_of_match[] = {
+ { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], },
+ { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, mt7530_of_match);
@@ -1680,8 +1790,19 @@ mt7530_probe(struct mdio_device *mdiodev
/* Get the hardware identifier from the devicetree node.
* We will need it for some of the clock and regulator setup.
*/
- priv->id = (unsigned int)(unsigned long)
- of_device_get_match_data(&mdiodev->dev);
+ priv->info = of_device_get_match_data(&mdiodev->dev);
+ if (!priv->info)
+ return -EINVAL;
+
+ /* Sanity check if these required device operstaions are filled
+ * properly.
+ */
+ if (!priv->info->setup || !priv->info->phy_read ||
+ !priv->info->phy_write || !priv->info->phy_supported ||
+ !priv->info->pad_setup || !priv->info->mac_setup)
+ return -EINVAL;
+
+ priv->id = priv->info->id;
if (priv->id == ID_MT7530) {
priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
Index: linux-5.4.43/drivers/net/dsa/mt7530.h
===================================================================
--- linux-5.4.43.orig/drivers/net/dsa/mt7530.h
+++ linux-5.4.43/drivers/net/dsa/mt7530.h
@@ -11,7 +11,7 @@
#define MT7530_NUM_FDB_RECORDS 2048
#define MT7530_ALL_MEMBERS 0xff
-enum {
+enum mt753x_id {
ID_MT7530 = 0,
ID_MT7621 = 1,
};
@@ -447,6 +447,32 @@ static const char *p5_intf_modes(unsigne
}
}
+/* struct mt753x_info - This is the main data structure for holding the specific
+ * part for each supported device
+ * @setup: Holding the handler to a device initialization
+ * @phy_read: Holding the way reading PHY port
+ * @phy_write: Holding the way writing PHY port
+ * @phy_supported: Check if the PHY type is being supported on a certain
+ * port
+ * @pad_setup: Holding the way setting up the bus pad for a certain MAC
+ * port
+ * @mac_setup: Holding the way setting up the PHY attribute for a
+ * certain MAC port
+ */
+struct mt753x_info {
+ enum mt753x_id id;
+
+ int (*setup)(struct dsa_switch *ds);
+ int (*phy_read)(struct dsa_switch *ds, int port, int regnum);
+ int (*phy_write)(struct dsa_switch *ds, int port, int regnum, u16 val);
+ bool (*phy_supported)(struct dsa_switch *ds, int port,
+ const struct phylink_link_state *state);
+ int (*pad_setup)(struct dsa_switch *ds,
+ const struct phylink_link_state *state);
+ int (*mac_setup)(struct dsa_switch *ds, int port, unsigned int mode,
+ const struct phylink_link_state *state);
+};
+
/* struct mt7530_priv - This is the main data structure for holding the state
* of the driver
* @dev: The device pointer
@@ -472,6 +498,7 @@ struct mt7530_priv {
struct regulator *core_pwr;
struct regulator *io_pwr;
struct gpio_desc *reset;
+ const struct mt753x_info *info;
unsigned int id;
bool mcm;
phy_interface_t p6_interface;

@ -0,0 +1,181 @@
From patchwork Tue Dec 10 08:14:39 2019
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
X-Patchwork-Submitter: Landen Chao <landen.chao@mediatek.com>
X-Patchwork-Id: 1206955
X-Patchwork-Delegate: davem@davemloft.net
Return-Path: <netdev-owner@vger.kernel.org>
X-Original-To: patchwork-incoming-netdev@ozlabs.org
Delivered-To: patchwork-incoming-netdev@ozlabs.org
Authentication-Results: ozlabs.org; spf=none (no SPF record)
smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67;
helo=vger.kernel.org;
envelope-from=netdev-owner@vger.kernel.org;
receiver=<UNKNOWN>)
Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none)
header.from=mediatek.com
Authentication-Results: ozlabs.org; dkim=pass (1024-bit key;
unprotected) header.d=mediatek.com header.i=@mediatek.com
header.b="SuczJHZp"; dkim-atps=neutral
Received: from vger.kernel.org (vger.kernel.org [209.132.180.67])
by ozlabs.org (Postfix) with ESMTP id 47XCXj3BBNz9sPh
for <patchwork-incoming-netdev@ozlabs.org>;
Tue, 10 Dec 2019 19:15:01 +1100 (AEDT)
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
id S1727133AbfLJIPA (ORCPT
<rfc822;patchwork-incoming-netdev@ozlabs.org>);
Tue, 10 Dec 2019 03:15:00 -0500
Received: from mailgw02.mediatek.com ([210.61.82.184]:45567 "EHLO
mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by
vger.kernel.org with ESMTP id S1727022AbfLJIO7 (ORCPT
<rfc822;netdev@vger.kernel.org>); Tue, 10 Dec 2019 03:14:59 -0500
X-UUID: a1d9a42928d44d63b201d5ad84c05baa-20191210
DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;
d=mediatek.com; s=dk;
h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From;
bh=KJqQ2m7z9H4vre+SZyxgKEGRWb9Edp5pJlYnepJNMyM=;
b=SuczJHZpeY7vF8UsCGorYUAcT2lEUX2E0ciiyQBS1rDLPzTYnufK8OXyAw5Uq8U1m72TGWYCaq1o0VWtI1meJpEmCL2TVK/d+Y+IaacHlO716BmX77+0MU0crczE8zx1Nz2pNh+GicsB6AoC9qbBU+p5egbKDMBhpRaGQNAeBww=;
X-UUID: a1d9a42928d44d63b201d5ad84c05baa-20191210
Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by
mailgw02.mediatek.com (envelope-from <landen.chao@mediatek.com>)
(Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS)
with ESMTP id 297826603; Tue, 10 Dec 2019 16:14:47 +0800
Received: from mtkcas08.mediatek.inc (172.21.101.126) by
mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server
(TLS) id 15.0.1395.4; Tue, 10 Dec 2019 16:14:38 +0800
Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc
(172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via
Frontend Transport; Tue, 10 Dec 2019 16:14:26 +0800
From: Landen Chao <landen.chao@mediatek.com>
To: <andrew@lunn.ch>, <f.fainelli@gmail.com>,
<vivien.didelot@savoirfairelinux.com>, <matthias.bgg@gmail.com>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>
CC: <devicetree@vger.kernel.org>, <netdev@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>, <davem@davemloft.net>,
<sean.wang@mediatek.com>, <opensource@vdorst.com>,
<frank-w@public-files.de>, Landen Chao <landen.chao@mediatek.com>
Subject: [PATCH net-next 3/6] dt-bindings: net: dsa: add new MT7531 binding
to support MT7531
Date: Tue, 10 Dec 2019 16:14:39 +0800
Message-ID: <1c382fd916b66bfe3ce8ef18c12f954dbcbddbbc.1575914275.git.landen.chao@mediatek.com>
X-Mailer: git-send-email 2.18.0
In-Reply-To: <cover.1575914275.git.landen.chao@mediatek.com>
References: <cover.1575914275.git.landen.chao@mediatek.com>
MIME-Version: 1.0
X-MTK: N
Sender: netdev-owner@vger.kernel.org
Precedence: bulk
List-ID: <netdev.vger.kernel.org>
X-Mailing-List: netdev@vger.kernel.org
Add devicetree binding to support the compatible mt7531 switch as used
in the MediaTek MT7531 switch.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Landen Chao <landen.chao@mediatek.com>
---
.../devicetree/bindings/net/dsa/mt7530.txt | 77 ++++++++++++++++++-
1 file changed, 74 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/dsa/mt7530.txt b/Documentation/devicetree/bindings/net/dsa/mt7530.txt
index c5ed5d25f642..dc226a4e402a 100644
--- a/Documentation/devicetree/bindings/net/dsa/mt7530.txt
+++ b/Documentation/devicetree/bindings/net/dsa/mt7530.txt
@@ -5,6 +5,7 @@ Required properties:
- compatible: may be compatible = "mediatek,mt7530"
or compatible = "mediatek,mt7621"
+ or compatible = "mediatek,mt7531"
- #address-cells: Must be 1.
- #size-cells: Must be 0.
- mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part
@@ -32,10 +33,13 @@ Required properties for the child nodes within ports container:
- reg: Port address described must be 6 for CPU port and from 0 to 5 for
user ports.
-- phy-mode: String, must be either "trgmii" or "rgmii" for port labeled
- "cpu".
+- phy-mode: String, the follow value would be acceptable for port labeled "cpu"
+ If compatible mediatek,mt7530 or mediatek,mt7621 is set,
+ must be either "trgmii" or "rgmii"
+ If compatible mediatek,mt7531 is set,
+ must be either "sgmii", "1000base-x" or "2500base-x"
-Port 5 of the switch is muxed between:
+Port 5 of mt7530 and mt7621 switch is muxed between:
1. GMAC5: GMAC5 can interface with another external MAC or PHY.
2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC
of the SOC. Used in many setups where port 0/4 becomes the WAN port.
@@ -308,3 +312,70 @@ Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> external PHY.
};
};
};
+
+Example 4:
+
+&eth {
+ gmac0: mac@0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+ };
+
+ &mdio0 {
+ switch@0 {
+ compatible = "mediatek,mt7531";
+ reg = <0>;
+ reset-gpios = <&pio 54 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan0";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan1";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan2";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan3";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "wan";
+ };
+
+ port@6 {
+ reg = <6>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+ };
+ };

@ -0,0 +1,140 @@
From patchwork Tue Dec 10 08:14:42 2019
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
X-Patchwork-Submitter: Landen Chao <landen.chao@mediatek.com>
X-Patchwork-Id: 1206964
X-Patchwork-Delegate: davem@davemloft.net
Return-Path: <netdev-owner@vger.kernel.org>
X-Original-To: patchwork-incoming-netdev@ozlabs.org
Delivered-To: patchwork-incoming-netdev@ozlabs.org
Authentication-Results: ozlabs.org; spf=none (no SPF record)
smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67;
helo=vger.kernel.org;
envelope-from=netdev-owner@vger.kernel.org;
receiver=<UNKNOWN>)
Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none)
header.from=mediatek.com
Authentication-Results: ozlabs.org; dkim=pass (1024-bit key;
unprotected) header.d=mediatek.com header.i=@mediatek.com
header.b="eagJVm76"; dkim-atps=neutral
Received: from vger.kernel.org (vger.kernel.org [209.132.180.67])
by ozlabs.org (Postfix) with ESMTP id 47XCYF2fNjz9sR7
for <patchwork-incoming-netdev@ozlabs.org>;
Tue, 10 Dec 2019 19:15:29 +1100 (AEDT)
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
id S1727295AbfLJIP0 (ORCPT
<rfc822;patchwork-incoming-netdev@ozlabs.org>);
Tue, 10 Dec 2019 03:15:26 -0500
Received: from mailgw01.mediatek.com ([210.61.82.183]:21469 "EHLO
mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by
vger.kernel.org with ESMTP id S1726062AbfLJIO4 (ORCPT
<rfc822;netdev@vger.kernel.org>); Tue, 10 Dec 2019 03:14:56 -0500
X-UUID: f9b456136baf42daba0957485d388010-20191210
DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;
d=mediatek.com; s=dk;
h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From;
bh=BT+q/z4xoeKXCk+y25bvARvW/z0vRa1uB7kHqAjvpaw=;
b=eagJVm76XNgnVVvxDHR4QtcIyynPPYY4k7twyvlRAQeSnsJbABh1afLK+LlxnJ0TM069F+hNNzWXq7ZGru/I+gYhmqZcYCt/SkEYgxdTb0VNE+DIW0hmNAOoJ0i23gobJ3xa7JVRfIfeZcbjwRJSuqwzLBRZBLIFzqSs71VZx1Y=;
X-UUID: f9b456136baf42daba0957485d388010-20191210
Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by
mailgw01.mediatek.com (envelope-from <landen.chao@mediatek.com>)
(Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS)
with ESMTP id 1831961689; Tue, 10 Dec 2019 16:14:48 +0800
Received: from mtkcas08.mediatek.inc (172.21.101.126) by
mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server
(TLS) id 15.0.1395.4; Tue, 10 Dec 2019 16:14:32 +0800
Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc
(172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via
Frontend Transport; Tue, 10 Dec 2019 16:14:27 +0800
From: Landen Chao <landen.chao@mediatek.com>
To: <andrew@lunn.ch>, <f.fainelli@gmail.com>,
<vivien.didelot@savoirfairelinux.com>, <matthias.bgg@gmail.com>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>
CC: <devicetree@vger.kernel.org>, <netdev@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>, <davem@davemloft.net>,
<sean.wang@mediatek.com>, <opensource@vdorst.com>,
<frank-w@public-files.de>, Landen Chao <landen.chao@mediatek.com>
Subject: [PATCH net-next 6/6] arm64: dts: mt7622: add mt7531 dsa to
bananapi-bpi-r64 board
Date: Tue, 10 Dec 2019 16:14:42 +0800
Message-ID: <62eef5503c117f48d4b41e94fd28d75e123590b4.1575914275.git.landen.chao@mediatek.com>
X-Mailer: git-send-email 2.18.0
In-Reply-To: <cover.1575914275.git.landen.chao@mediatek.com>
References: <cover.1575914275.git.landen.chao@mediatek.com>
MIME-Version: 1.0
X-MTK: N
Sender: netdev-owner@vger.kernel.org
Precedence: bulk
List-ID: <netdev.vger.kernel.org>
X-Mailing-List: netdev@vger.kernel.org
Add mt7531 dsa to bananapi-bpi-r64 board for 5 giga Ethernet ports support.
Signed-off-by: Landen Chao <landen.chao@mediatek.com>
---
.../dts/mediatek/mt7622-bananapi-bpi-r64.dts | 50 +++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
index 83e10591e0e5..ffacefee8e2a 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -143,6 +143,56 @@
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
+
+ switch@0 {
+ compatible = "mediatek,mt7531";
+ reg = <0>;
+ reset-gpios = <&pio 54 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "wan";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan0";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan1";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan2";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan3";
+ };
+
+ port@6 {
+ reg = <6>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+ };
+
};
};
Loading…
Cancel
Save