parent
b5516603dd
commit
abb0452cd8
@ -0,0 +1,94 @@
|
||||
diff -urN a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
|
||||
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c 2020-04-21 14:33:05.702816632 +0800
|
||||
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c 2020-04-21 14:33:19.590328084 +0800
|
||||
@@ -2191,6 +2191,31 @@
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static void mtk_gdm_config(struct mtk_eth *eth, u32 config)
|
||||
+{
|
||||
+ int i;
|
||||
+
|
||||
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
|
||||
+ return;
|
||||
+
|
||||
+ for (i = 0; i < MTK_MAC_COUNT; i++) {
|
||||
+ u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
|
||||
+
|
||||
+ /* default setup the forward port to send frame to PDMA */
|
||||
+ val &= ~0xffff;
|
||||
+
|
||||
+ /* Enable RX checksum */
|
||||
+ val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
|
||||
+
|
||||
+ val |= config;
|
||||
+
|
||||
+ mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
|
||||
+ }
|
||||
+ /* Reset and enable PSE */
|
||||
+ mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
|
||||
+ mtk_w32(eth, 0, MTK_RST_GL);
|
||||
+}
|
||||
+
|
||||
static int mtk_open(struct net_device *dev)
|
||||
{
|
||||
struct mtk_mac *mac = netdev_priv(dev);
|
||||
@@ -2211,6 +2236,8 @@
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
+ mtk_gdm_config(eth, MTK_GDMA_TO_PDMA);
|
||||
+
|
||||
napi_enable(ð->tx_napi);
|
||||
napi_enable(ð->rx_napi);
|
||||
mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
|
||||
@@ -2266,6 +2293,8 @@
|
||||
if (!refcount_dec_and_test(ð->dma_refcnt))
|
||||
return 0;
|
||||
|
||||
+ mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
|
||||
+
|
||||
mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
|
||||
mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
|
||||
napi_disable(ð->tx_napi);
|
||||
@@ -2392,8 +2421,6 @@
|
||||
mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
|
||||
mtk_tx_irq_disable(eth, ~0);
|
||||
mtk_rx_irq_disable(eth, ~0);
|
||||
- mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
|
||||
- mtk_w32(eth, 0, MTK_RST_GL);
|
||||
|
||||
/* FE int grouping */
|
||||
mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
|
||||
@@ -2402,19 +2429,6 @@
|
||||
mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
|
||||
mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
|
||||
|
||||
- for (i = 0; i < MTK_MAC_COUNT; i++) {
|
||||
- u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
|
||||
-
|
||||
- /* setup the forward port to send frame to PDMA */
|
||||
- val &= ~0xffff;
|
||||
-
|
||||
- /* Enable RX checksum */
|
||||
- val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
|
||||
-
|
||||
- /* setup the mac dma */
|
||||
- mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
|
||||
- }
|
||||
-
|
||||
return 0;
|
||||
|
||||
err_disable_pm:
|
||||
diff -urN a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
|
||||
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h 2020-04-21 14:33:10.702640743 +0800
|
||||
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h 2020-04-21 14:33:24.902141220 +0800
|
||||
@@ -84,6 +84,8 @@
|
||||
#define MTK_GDMA_ICS_EN BIT(22)
|
||||
#define MTK_GDMA_TCS_EN BIT(21)
|
||||
#define MTK_GDMA_UCS_EN BIT(20)
|
||||
+#define MTK_GDMA_TO_PDMA 0x0
|
||||
+#define MTK_GDMA_DROP_ALL 0x7777
|
||||
|
||||
/* Unicast Filter MAC Address Register - Low */
|
||||
#define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000))
|
@ -0,0 +1,25 @@
|
||||
diff -urN a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
|
||||
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c 2020-04-21 14:33:05.702816632 +0800
|
||||
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c 2020-04-21 14:33:19.590328084 +0800
|
||||
@@ -1345,10 +1345,11 @@
|
||||
u32 next_cpu = desc->txd2;
|
||||
int mac = 0;
|
||||
|
||||
- desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
|
||||
if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
|
||||
break;
|
||||
|
||||
+ desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
|
||||
+
|
||||
tx_buf = mtk_desc_to_tx_buf(ring, desc);
|
||||
if (tx_buf->flags & MTK_TX_FLAGS_FPORT1)
|
||||
mac = 1;
|
||||
@@ -2172,7 +2173,7 @@
|
||||
|
||||
if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
|
||||
mtk_w32(eth,
|
||||
- MTK_TX_WB_DDONE | MTK_TX_DMA_EN |
|
||||
+ MTK_TX_DMA_EN |
|
||||
MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO |
|
||||
MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
|
||||
MTK_RX_BT_32DWORDS,
|
Loading…
Reference in New Issue