ramips: update v3.10 patches
Sync the patches with those sent upstream for v3.12. Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 37778v19.07.3_mercusys_ac12_duma
John Crispin
11 years ago
parent
2864fb107f
commit
9e5b0cc19c
@ -1,173 +0,0 @@
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CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
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CONFIG_ARCH_DISCARD_MEMBLOCK=y
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CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
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CONFIG_ARCH_HAS_RESET_CONTROLLER=y
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CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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CONFIG_ARCH_REQUIRE_GPIOLIB=y
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CONFIG_ARCH_SUSPEND_POSSIBLE=y
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CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
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CONFIG_CC_OPTIMIZE_FOR_SIZE=y
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CONFIG_CEVT_R4K=y
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CONFIG_CLKDEV_LOOKUP=y
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CONFIG_CLKEVT_RT3352=y
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CONFIG_CLKSRC_MMIO=y
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CONFIG_CLKSRC_OF=y
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CONFIG_CLONE_BACKWARDS=y
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CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
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CONFIG_CMDLINE_BOOL=y
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# CONFIG_CMDLINE_OVERRIDE is not set
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CONFIG_CPU_GENERIC_DUMP_TLB=y
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CONFIG_CPU_HAS_PREFETCH=y
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CONFIG_CPU_HAS_SYNC=y
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CONFIG_CPU_LITTLE_ENDIAN=y
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CONFIG_CPU_MIPS32=y
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# CONFIG_CPU_MIPS32_R1 is not set
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CONFIG_CPU_MIPS32_R2=y
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CONFIG_CPU_MIPSR2=y
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CONFIG_CPU_R4K_CACHE_TLB=y
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CONFIG_CPU_R4K_FPU=y
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CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
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CONFIG_CPU_SUPPORTS_HIGHMEM=y
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CONFIG_CSRC_R4K=y
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CONFIG_DECOMPRESS_LZMA=y
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CONFIG_DMA_NONCOHERENT=y
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# CONFIG_DTB_MT7620A_EVAL is not set
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# CONFIG_DTB_MT7620A_MT7610E_EVAL is not set
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CONFIG_DTB_RT_NONE=y
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CONFIG_DTC=y
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CONFIG_EARLY_PRINTK=y
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CONFIG_GENERIC_ATOMIC64=y
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
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CONFIG_GENERIC_CMOS_UPDATE=y
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CONFIG_GENERIC_GPIO=y
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CONFIG_GENERIC_IO=y
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CONFIG_GENERIC_IRQ_SHOW=y
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CONFIG_GENERIC_PCI_IOMAP=y
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CONFIG_GENERIC_SMP_IDLE_THREAD=y
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CONFIG_GPIOLIB=y
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CONFIG_GPIO_DEVRES=y
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CONFIG_GPIO_RALINK=y
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CONFIG_GPIO_SYSFS=y
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CONFIG_HARDWARE_WATCHPOINTS=y
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CONFIG_HAS_DMA=y
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CONFIG_HAS_IOMEM=y
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CONFIG_HAS_IOPORT=y
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# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
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CONFIG_HAVE_ARCH_JUMP_LABEL=y
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CONFIG_HAVE_ARCH_KGDB=y
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# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
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CONFIG_HAVE_CLK=y
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CONFIG_HAVE_C_RECORDMCOUNT=y
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CONFIG_HAVE_DEBUG_KMEMLEAK=y
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CONFIG_HAVE_DMA_API_DEBUG=y
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CONFIG_HAVE_DMA_ATTRS=y
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CONFIG_HAVE_DYNAMIC_FTRACE=y
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CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
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CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
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CONFIG_HAVE_FUNCTION_TRACER=y
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CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
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CONFIG_HAVE_GENERIC_DMA_COHERENT=y
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CONFIG_HAVE_GENERIC_HARDIRQS=y
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CONFIG_HAVE_IDE=y
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CONFIG_HAVE_MACH_CLKDEV=y
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CONFIG_HAVE_MEMBLOCK=y
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CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
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CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
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CONFIG_HAVE_NET_DSA=y
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CONFIG_HAVE_OPROFILE=y
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CONFIG_HAVE_PERF_EVENTS=y
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CONFIG_HW_HAS_PCI=y
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CONFIG_HW_RANDOM=m
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CONFIG_IMAGE_CMDLINE_HACK=y
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CONFIG_INITRAMFS_SOURCE=""
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CONFIG_IRQCHIP=y
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CONFIG_IRQ_CPU=y
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CONFIG_IRQ_DOMAIN=y
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CONFIG_IRQ_FORCED_THREADING=y
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CONFIG_IRQ_WORK=y
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CONFIG_M25PXX_USE_FAST_READ=y
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CONFIG_MDIO_BOARDINFO=y
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# CONFIG_MII is not set
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CONFIG_MIPS=y
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# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
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CONFIG_MIPS_L1_CACHE_SHIFT=5
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# CONFIG_MIPS_MACHINE is not set
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CONFIG_MIPS_MT_DISABLED=y
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CONFIG_MMC=y
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CONFIG_MMC_BLOCK=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_IO_ACCESSORS=y
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CONFIG_MMC_SDHCI_MT7620=y
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# CONFIG_MMC_SDHCI_PCI is not set
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CONFIG_MMC_SDHCI_PLTFM=y
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# CONFIG_MMC_TIFM_SD is not set
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CONFIG_MODULES_USE_ELF_REL=y
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# CONFIG_MTD_CFI_INTELEXT is not set
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CONFIG_MTD_CMDLINE_PARTS=y
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CONFIG_MTD_M25P80=y
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CONFIG_MTD_OF_PARTS=y
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CONFIG_MTD_PHYSMAP=y
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CONFIG_MTD_PHYSMAP_OF=y
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CONFIG_MTD_UIMAGE_SPLIT=y
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CONFIG_NEED_DMA_MAP_STATE=y
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CONFIG_NEED_PER_CPU_KM=y
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CONFIG_NET_RALINK=y
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CONFIG_NET_RALINK_GSW_MT7620=y
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CONFIG_NET_RALINK_MDIO=y
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CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
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CONFIG_OF=y
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CONFIG_OF_ADDRESS=y
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CONFIG_OF_DEVICE=y
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# CONFIG_OF_DISPLAY_TIMING is not set
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CONFIG_OF_EARLY_FLATTREE=y
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CONFIG_OF_FLATTREE=y
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CONFIG_OF_GPIO=y
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CONFIG_OF_IRQ=y
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CONFIG_OF_MDIO=y
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CONFIG_OF_MTD=y
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CONFIG_OF_NET=y
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CONFIG_OF_PCI=y
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CONFIG_OF_PCI_IRQ=y
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# CONFIG_OF_VIDEOMODE is not set
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CONFIG_PAGEFLAGS_EXTENDED=y
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CONFIG_PCI=y
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CONFIG_PCI_DOMAINS=y
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CONFIG_PERF_USE_VMALLOC=y
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CONFIG_PHYLIB=y
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# CONFIG_PREEMPT_RCU is not set
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CONFIG_RALINK=y
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# CONFIG_RALINK_ILL_ACC is not set
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CONFIG_RALINK_USBPHY=y
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CONFIG_RALINK_WDT=y
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# CONFIG_RCU_STALL_COMMON is not set
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CONFIG_RESET_CONTROLLER=y
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# CONFIG_SCSI_DMA is not set
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CONFIG_SERIAL_8250_NR_UARTS=4
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CONFIG_SERIAL_8250_RT288X=y
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CONFIG_SERIAL_OF_PLATFORM=y
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# CONFIG_SLAB is not set
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CONFIG_SLUB=y
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CONFIG_SOC_MT7620=y
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# CONFIG_SOC_RT288X is not set
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# CONFIG_SOC_RT305X is not set
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# CONFIG_SOC_RT3883 is not set
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CONFIG_SPI=y
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CONFIG_SPI_MASTER=y
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CONFIG_SPI_RALINK=y
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CONFIG_SWCONFIG=y
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CONFIG_SYS_HAS_CPU_MIPS32_R1=y
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CONFIG_SYS_HAS_CPU_MIPS32_R2=y
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CONFIG_SYS_HAS_EARLY_PRINTK=y
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CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
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CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
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CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
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CONFIG_TICK_CPU_ACCOUNTING=y
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CONFIG_UIDGID_CONVERTED=y
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CONFIG_USB_ARCH_HAS_XHCI=y
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CONFIG_USB_OTG_UTILS=y
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CONFIG_USB_SUPPORT=y
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CONFIG_USE_OF=y
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CONFIG_WATCHDOG_CORE=y
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CONFIG_ZONE_DMA_FLAG=0
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@ -0,0 +1,39 @@
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From d11f6e47eb748f27ba325bd843cc88bae3ad0e8a Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Tue, 29 Jan 2013 21:11:55 +0100
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Subject: [PATCH 01/25] MTD: m25p80: allow loading mtd name from OF
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In accordance with the physmap flash we should honour the linux,mtd-name
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property when deciding what name the mtd device has.
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Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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drivers/mtd/devices/m25p80.c | 5 +++++
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1 file changed, 5 insertions(+)
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--- a/drivers/mtd/devices/m25p80.c
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+++ b/drivers/mtd/devices/m25p80.c
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@@ -926,10 +926,13 @@ static int m25p_probe(struct spi_device
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unsigned i;
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struct mtd_part_parser_data ppdata;
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struct device_node __maybe_unused *np = spi->dev.of_node;
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+ const char __maybe_unused *of_mtd_name = NULL;
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#ifdef CONFIG_MTD_OF_PARTS
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if (!of_device_is_available(np))
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return -ENODEV;
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+ of_property_read_string(spi->dev.of_node,
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+ "linux,mtd-name", &of_mtd_name);
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#endif
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/* Platform data helps sort out which chip type we have, as
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@@ -1005,6 +1008,8 @@ static int m25p_probe(struct spi_device
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if (data && data->name)
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flash->mtd.name = data->name;
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+ else if (of_mtd_name)
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+ flash->mtd.name = of_mtd_name;
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else
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flash->mtd.name = dev_name(&spi->dev);
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@ -0,0 +1,105 @@
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From 080f1a0c539180a88066fb004a8c31eefdf74161 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Fri, 9 Aug 2013 18:47:27 +0200
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Subject: [PATCH 02/25] reset: Fix compile when reset RESET_CONTROLLER is not
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selected
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Drivers need to protect their reset api calls with #ifdef to avoid compile
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errors.
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This patch adds dummy wrappers in the same way that linux/of.h does it.
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Cc: linux-kernel@vger.kernel.org
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Cc: Philipp Zabel <p.zabel@pengutronix.de>
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Cc: Gabor Juhos <juhosg@openwrt.org>
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---
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include/linux/reset-controller.h | 16 ++++++++++++++
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include/linux/reset.h | 43 ++++++++++++++++++++++++++++++++++++++
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2 files changed, 59 insertions(+)
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--- a/include/linux/reset-controller.h
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+++ b/include/linux/reset-controller.h
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@@ -45,7 +45,23 @@ struct reset_controller_dev {
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unsigned int nr_resets;
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};
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+#if defined(CONFIG_RESET_CONTROLLER)
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+
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int reset_controller_register(struct reset_controller_dev *rcdev);
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void reset_controller_unregister(struct reset_controller_dev *rcdev);
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+#else
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+
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+static inline int reset_controller_register(struct reset_controller_dev *rcdev)
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+{
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+ return -ENOSYS;
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+}
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+
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+void reset_controller_unregister(struct reset_controller_dev *rcdev)
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+{
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+
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+}
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+
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+#endif
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+
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#endif
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--- a/include/linux/reset.h
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+++ b/include/linux/reset.h
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@@ -1,9 +1,13 @@
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#ifndef _LINUX_RESET_H_
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#define _LINUX_RESET_H_
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+#include <linux/err.h>
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+
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struct device;
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struct reset_control;
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+#if defined(CONFIG_RESET_CONTROLLER)
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+
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int reset_control_reset(struct reset_control *rstc);
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int reset_control_assert(struct reset_control *rstc);
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int reset_control_deassert(struct reset_control *rstc);
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@@ -14,4 +18,43 @@ struct reset_control *devm_reset_control
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int device_reset(struct device *dev);
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+#else /* CONFIG_RESET_CONTROLLER */
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+
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+static inline int reset_control_reset(struct reset_control *rstc)
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+{
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+ return -ENOSYS;
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+}
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+
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+static inline int reset_control_assert(struct reset_control *rstc)
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+{
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+ return -ENOSYS;
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+}
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+
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+static inline int reset_control_deassert(struct reset_control *rstc)
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+{
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+ return -ENOSYS;
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+}
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+
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+static inline struct reset_control *reset_control_get(struct device *dev, const char *id)
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+{
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+ return ERR_PTR(-ENOSYS);
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+}
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+
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+static inline void reset_control_put(struct reset_control *rstc)
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+{
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+
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+}
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+
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+static inline struct reset_control *devm_reset_control_get(struct device *dev, const char *id)
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+{
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+ return ERR_PTR(-ENOSYS);
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+}
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+
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+static inline int device_reset(struct device *dev)
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+{
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+ return -ENOSYS;
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+}
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+
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+#endif
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+
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#endif
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@ -0,0 +1,39 @@
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From 8b87087423057f8a06423702f3035634d6e8cd73 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Sun, 28 Jul 2013 19:57:20 +0200
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Subject: [PATCH 03/25] DT: Add documentation for rt2880-wdt
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This document describes the binding of the watchdog core found ralink wireless
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SoC.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Cc: linux-watchdog@vger.kernel.org
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Cc: linux-mips@linux-mips.org
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Cc: devicetree-discuss@lists.ozlabs.org
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---
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.../devicetree/bindings/watchdog/rt2880-wdt.txt | 19 +++++++++++++++++++
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1 file changed, 19 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/watchdog/rt2880-wdt.txt
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/watchdog/rt2880-wdt.txt
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@@ -0,0 +1,19 @@
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+Ralink Watchdog Timers
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+
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+Required properties :
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+- compatible: must be "ralink,rt2880-wdt"
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+- reg: physical base address of the controller and length of the register range
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+
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+Optional properties :
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+- interrupt-parent: phandle to the INTC device node
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+- interrupts: Specify the INTC interrupt number
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+
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+Example:
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+
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+ watchdog@120 {
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+ compatible = "ralink,rt2880-wdt";
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+ reg = <0x120 0x10>;
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <1>;
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+ };
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@ -0,0 +1,59 @@
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From ad68c2865b360f1b637432b4cbcaaf101d2687b9 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Sun, 28 Jul 2013 19:45:30 +0200
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Subject: [PATCH 05/25] DT: Add documentation for gpio-ralink
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Describe gpio-ralink binding.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Cc: linux-mips@linux-mips.org
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Cc: devicetree@vger.kernel.org
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Cc: linux-gpio@vger.kernel.org
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---
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.../devicetree/bindings/gpio/gpio-ralink.txt | 40 ++++++++++++++++++++
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1 file changed, 40 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/gpio/gpio-ralink.txt
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/gpio/gpio-ralink.txt
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@@ -0,0 +1,40 @@
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+Ralink SoC GPIO controller bindings
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+
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+Required properties:
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+- compatible:
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+ - "ralink,rt2880-gpio" for Ralink controllers
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+- #gpio-cells : Should be two.
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+ - first cell is the pin number
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+ - second cell is used to specify optional parameters (unused)
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+- gpio-controller : Marks the device node as a GPIO controller
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+- reg : Physical base address and length of the controller's registers
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+- interrupt-parent: phandle to the INTC device node
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+- interrupts : Specify the INTC interrupt number
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+- ralink,num-gpios : Specify the number of GPIOs
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+- ralink,register-map : The register layout depends on the GPIO bank and actual
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+ SoC type. Register offsets need to be in this order.
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+ [ INT, EDGE, RENA, FENA, DATA, DIR, POL, SET, RESET, TOGGLE ]
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+
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+Optional properties:
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+- ralink,gpio-base : Specify the GPIO chips base number
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+
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+Example:
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+
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+ gpio0: gpio@600 {
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+ compatible = "ralink,rt5350-gpio", "ralink,rt2880-gpio";
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+
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+ #gpio-cells = <2>;
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+ gpio-controller;
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+
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+ reg = <0x600 0x34>;
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <6>;
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+
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+ ralink,gpio-base = <0>;
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+ ralink,num-gpios = <24>;
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+ ralink,register-map = [ 00 04 08 0c
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+ 20 24 28 2c
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+ 30 34 ];
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+
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+ };
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@ -0,0 +1,25 @@
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From 0b78522f6e136fa5901e72cdbf4a44693d100826 Mon Sep 17 00:00:00 2001
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From: Thomas Langer <thomas.langer@lantiq.com>
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Date: Sun, 28 Jul 2013 14:44:44 +0200
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||||
Subject: [PATCH 07/25] serial: MIPS: lantiq: add clk_enable() call to driver
|
||||
|
||||
Enable the clock if one is present when setting up the console.
|
||||
|
||||
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
|
||||
Acked-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
drivers/tty/serial/lantiq.c | 3 +++
|
||||
1 file changed, 3 insertions(+)
|
||||
|
||||
--- a/drivers/tty/serial/lantiq.c
|
||||
+++ b/drivers/tty/serial/lantiq.c
|
||||
@@ -636,6 +636,9 @@ lqasc_console_setup(struct console *co,
|
||||
|
||||
port = <q_port->port;
|
||||
|
||||
+ if (!IS_ERR(ltq_port->clk))
|
||||
+ clk_enable(ltq_port->clk);
|
||||
+
|
||||
port->uartclk = clk_get_rate(ltq_port->fpiclk);
|
||||
|
||||
if (options)
|
||||
@ -0,0 +1,32 @@
|
||||
From d94da02421c14fa9295feb218cd45fc01d0f470b Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 8 Aug 2013 17:19:42 +0200
|
||||
Subject: [PATCH 08/25] serial: MIPS: lantiq: fix clock error check
|
||||
|
||||
The clk should be checked with the proper IS_ERR() api before accessing it.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
drivers/tty/serial/lantiq.c | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/tty/serial/lantiq.c
|
||||
+++ b/drivers/tty/serial/lantiq.c
|
||||
@@ -318,7 +318,7 @@ lqasc_startup(struct uart_port *port)
|
||||
struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
|
||||
int retval;
|
||||
|
||||
- if (ltq_port->clk)
|
||||
+ if (!IS_ERR(ltq_port->clk))
|
||||
clk_enable(ltq_port->clk);
|
||||
port->uartclk = clk_get_rate(ltq_port->fpiclk);
|
||||
|
||||
@@ -386,7 +386,7 @@ lqasc_shutdown(struct uart_port *port)
|
||||
port->membase + LTQ_ASC_RXFCON);
|
||||
ltq_w32_mask(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU,
|
||||
port->membase + LTQ_ASC_TXFCON);
|
||||
- if (ltq_port->clk)
|
||||
+ if (!IS_ERR(ltq_port->clk))
|
||||
clk_disable(ltq_port->clk);
|
||||
}
|
||||
|
||||
@ -0,0 +1,126 @@
|
||||
From 4e694014a11a407e309f62c7daade545ba71dcf1 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sun, 28 Jul 2013 13:54:22 +0200
|
||||
Subject: [PATCH 09/25] MIPS: ralink: add support for reset-controller API
|
||||
|
||||
Add a helper for reseting different devices on the SoC.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/Kconfig | 1 +
|
||||
arch/mips/ralink/common.h | 2 ++
|
||||
arch/mips/ralink/of.c | 3 +++
|
||||
arch/mips/ralink/reset.c | 62 +++++++++++++++++++++++++++++++++++++++++++++
|
||||
4 files changed, 68 insertions(+)
|
||||
|
||||
--- a/arch/mips/Kconfig
|
||||
+++ b/arch/mips/Kconfig
|
||||
@@ -373,6 +373,7 @@ config MACH_VR41XX
|
||||
select CSRC_R4K
|
||||
select SYS_HAS_CPU_VR41XX
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
+ select ARCH_HAS_RESET_CONTROLLER
|
||||
|
||||
config NXP_STB220
|
||||
bool "NXP STB220 board"
|
||||
--- a/arch/mips/ralink/common.h
|
||||
+++ b/arch/mips/ralink/common.h
|
||||
@@ -46,6 +46,8 @@ extern void ralink_of_remap(void);
|
||||
extern void ralink_clk_init(void);
|
||||
extern void ralink_clk_add(const char *dev, unsigned long rate);
|
||||
|
||||
+extern void ralink_rst_init(void);
|
||||
+
|
||||
extern void prom_soc_init(struct ralink_soc_info *soc_info);
|
||||
|
||||
__iomem void *plat_of_remap_node(const char *node);
|
||||
--- a/arch/mips/ralink/of.c
|
||||
+++ b/arch/mips/ralink/of.c
|
||||
@@ -110,6 +110,9 @@ static int __init plat_of_setup(void)
|
||||
if (of_platform_populate(NULL, of_ids, NULL, NULL))
|
||||
panic("failed to populate DT\n");
|
||||
|
||||
+ /* make sure ithat the reset controller is setup early */
|
||||
+ ralink_rst_init();
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
--- a/arch/mips/ralink/reset.c
|
||||
+++ b/arch/mips/ralink/reset.c
|
||||
@@ -10,6 +10,8 @@
|
||||
|
||||
#include <linux/pm.h>
|
||||
#include <linux/io.h>
|
||||
+#include <linux/of.h>
|
||||
+#include <linux/reset-controller.h>
|
||||
|
||||
#include <asm/reboot.h>
|
||||
|
||||
@@ -19,6 +21,66 @@
|
||||
#define SYSC_REG_RESET_CTRL 0x034
|
||||
#define RSTCTL_RESET_SYSTEM BIT(0)
|
||||
|
||||
+static int ralink_assert_device(struct reset_controller_dev *rcdev,
|
||||
+ unsigned long id)
|
||||
+{
|
||||
+ u32 val;
|
||||
+
|
||||
+ if (id < 8)
|
||||
+ return -1;
|
||||
+
|
||||
+ val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
|
||||
+ val |= BIT(id);
|
||||
+ rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int ralink_deassert_device(struct reset_controller_dev *rcdev,
|
||||
+ unsigned long id)
|
||||
+{
|
||||
+ u32 val;
|
||||
+
|
||||
+ if (id < 8)
|
||||
+ return -1;
|
||||
+
|
||||
+ val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
|
||||
+ val &= ~BIT(id);
|
||||
+ rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int ralink_reset_device(struct reset_controller_dev *rcdev,
|
||||
+ unsigned long id)
|
||||
+{
|
||||
+ ralink_assert_device(rcdev, id);
|
||||
+ return ralink_deassert_device(rcdev, id);
|
||||
+}
|
||||
+
|
||||
+static struct reset_control_ops reset_ops = {
|
||||
+ .reset = ralink_reset_device,
|
||||
+ .assert = ralink_assert_device,
|
||||
+ .deassert = ralink_deassert_device,
|
||||
+};
|
||||
+
|
||||
+static struct reset_controller_dev reset_dev = {
|
||||
+ .ops = &reset_ops,
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .nr_resets = 32,
|
||||
+ .of_reset_n_cells = 1,
|
||||
+};
|
||||
+
|
||||
+void ralink_rst_init(void)
|
||||
+{
|
||||
+ reset_dev.of_node = of_find_compatible_node(NULL, NULL,
|
||||
+ "ralink,rt2880-reset");
|
||||
+ if (!reset_dev.of_node)
|
||||
+ pr_err("Failed to find reset controller node");
|
||||
+ else
|
||||
+ reset_controller_register(&reset_dev);
|
||||
+}
|
||||
+
|
||||
static void ralink_restart(char *command)
|
||||
{
|
||||
local_irq_disable();
|
||||
@ -0,0 +1,21 @@
|
||||
From c4d6a957efb0c8d919302598ae547bde05137461 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sun, 28 Jul 2013 13:48:39 +0200
|
||||
Subject: [PATCH 12/25] MIPS: ralink: probe clocksources from OF
|
||||
|
||||
Make plat_time_init() call clocksource_of_init() allowing the systick cevt
|
||||
to load.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/ralink/clk.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/arch/mips/ralink/clk.c
|
||||
+++ b/arch/mips/ralink/clk.c
|
||||
@@ -69,4 +69,5 @@ void __init plat_time_init(void)
|
||||
pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
|
||||
mips_hpt_frequency = clk_get_rate(clk) / 2;
|
||||
clk_put(clk);
|
||||
+ clocksource_of_init();
|
||||
}
|
||||
@ -1,7 +1,7 @@
|
||||
From 3f6b346e1dd83c4f43d94aefa0520ffdfafd5f0b Mon Sep 17 00:00:00 2001
|
||||
From 2d17c793a9cd3f67351d1a15c099ef2464e81f47 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Mon, 20 May 2013 20:30:11 +0200
|
||||
Subject: [PATCH 05/33] MIPS: ralink: make mt7620 ram detect verbose
|
||||
Subject: [PATCH 13/25] MIPS: ralink: mt7620: add verbose ram info
|
||||
|
||||
Make the code print which of SDRAM, DDR1 or DDR2 was detected.
|
||||
|
||||
@ -0,0 +1,22 @@
|
||||
From 51db62f58431d9a89c55f59f98879829dcfddcaf Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sun, 28 Jul 2013 13:50:11 +0200
|
||||
Subject: [PATCH 15/25] MIPS: ralink: mt7620: add wdt clock definition
|
||||
|
||||
The definition of the wdt clock is missing.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/ralink/mt7620.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/arch/mips/ralink/mt7620.c
|
||||
+++ b/arch/mips/ralink/mt7620.c
|
||||
@@ -166,6 +166,7 @@ void __init ralink_clk_init(void)
|
||||
|
||||
ralink_clk_add("cpu", cpu_rate);
|
||||
ralink_clk_add("10000100.timer", 40000000);
|
||||
+ ralink_clk_add("10000120.watchdog", 40000000);
|
||||
ralink_clk_add("10000500.uart", 40000000);
|
||||
ralink_clk_add("10000b00.spi", 40000000);
|
||||
ralink_clk_add("10000c00.uartlite", 40000000);
|
||||
@ -0,0 +1,63 @@
|
||||
From 011f4bdba0dd4d1dff6d33b1a65541fc4f09c78e Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Fri, 24 May 2013 21:28:08 +0200
|
||||
Subject: [PATCH 16/25] MIPS: ralink: mt7620: fix usb issue during frequency
|
||||
scaling
|
||||
|
||||
If the USB HCD is running and the cpu is scaled too low, then the USB stops
|
||||
working. Increase the idle speed of the core to fix this if the kernel is
|
||||
built with USB support.
|
||||
|
||||
The values are taken from the Ralink SDK Kernel.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/include/asm/mach-ralink/mt7620.h | 1 +
|
||||
arch/mips/ralink/mt7620.c | 19 +++++++++++++++++++
|
||||
2 files changed, 20 insertions(+)
|
||||
|
||||
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
|
||||
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
|
||||
@@ -20,6 +20,7 @@
|
||||
#define SYSC_REG_CHIP_REV 0x0c
|
||||
#define SYSC_REG_SYSTEM_CONFIG0 0x10
|
||||
#define SYSC_REG_SYSTEM_CONFIG1 0x14
|
||||
+#define SYSC_REG_CPU_SYS_CLKCFG 0x3c
|
||||
#define SYSC_REG_CPLL_CONFIG0 0x54
|
||||
#define SYSC_REG_CPLL_CONFIG1 0x58
|
||||
|
||||
--- a/arch/mips/ralink/mt7620.c
|
||||
+++ b/arch/mips/ralink/mt7620.c
|
||||
@@ -20,6 +20,12 @@
|
||||
|
||||
#include "common.h"
|
||||
|
||||
+/* clock scaling */
|
||||
+#define CLKCFG_FDIV_MASK 0x1f00
|
||||
+#define CLKCFG_FDIV_USB_VAL 0x0300
|
||||
+#define CLKCFG_FFRAC_MASK 0x001f
|
||||
+#define CLKCFG_FFRAC_USB_VAL 0x0003
|
||||
+
|
||||
/* does the board have sdram or ddram */
|
||||
static int dram_type;
|
||||
|
||||
@@ -170,6 +176,19 @@ void __init ralink_clk_init(void)
|
||||
ralink_clk_add("10000500.uart", 40000000);
|
||||
ralink_clk_add("10000b00.spi", 40000000);
|
||||
ralink_clk_add("10000c00.uartlite", 40000000);
|
||||
+
|
||||
+ if (IS_ENABLED(CONFIG_USB)) {
|
||||
+ /*
|
||||
+ * When the CPU goes into sleep mode, the BUS clock will be too low for
|
||||
+ * USB to function properly
|
||||
+ */
|
||||
+ u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
|
||||
+
|
||||
+ val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
|
||||
+ val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
|
||||
+
|
||||
+ rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);
|
||||
+ }
|
||||
}
|
||||
|
||||
void __init ralink_of_remap(void)
|
||||
@ -0,0 +1,23 @@
|
||||
From c16c0b66594cb0be44e150dbe3fda747817b873d Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sun, 28 Jul 2013 17:50:53 +0200
|
||||
Subject: [PATCH 17/25] MIPS: ralink: mt7620: this SoC has ehci and ohci hosts
|
||||
|
||||
Select the the EHCI and OHCI symbols.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/ralink/Kconfig | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/arch/mips/ralink/Kconfig
|
||||
+++ b/arch/mips/ralink/Kconfig
|
||||
@@ -29,6 +29,8 @@ choice
|
||||
|
||||
config SOC_MT7620
|
||||
bool "MT7620"
|
||||
+ select USB_ARCH_HAS_OHCI
|
||||
+ select USB_ARCH_HAS_EHCI
|
||||
|
||||
endchoice
|
||||
|
||||
@ -1,41 +0,0 @@
|
||||
From 3f40514a51b44171d274ef6a7d66dce9ae7c349d Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Fri, 24 May 2013 21:28:08 +0200
|
||||
Subject: [PATCH 17/33] USB: MIPS: ralink: fix usb issue on mt7620
|
||||
|
||||
USB fails when frequency scaling is enabled. Increase the idle cpu speed when
|
||||
scaled.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/include/asm/mach-ralink/mt7620.h | 1 +
|
||||
arch/mips/ralink/mt7620.c | 8 ++++++++
|
||||
2 files changed, 9 insertions(+)
|
||||
|
||||
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
|
||||
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
|
||||
@@ -20,6 +20,7 @@
|
||||
#define SYSC_REG_CHIP_REV 0x0c
|
||||
#define SYSC_REG_SYSTEM_CONFIG0 0x10
|
||||
#define SYSC_REG_SYSTEM_CONFIG1 0x14
|
||||
+#define SYSC_REG_CPU_SYS_CLKCFG 0x3c
|
||||
#define SYSC_REG_CPLL_CONFIG0 0x54
|
||||
#define SYSC_REG_CPLL_CONFIG1 0x58
|
||||
|
||||
--- a/arch/mips/ralink/mt7620.c
|
||||
+++ b/arch/mips/ralink/mt7620.c
|
||||
@@ -185,6 +185,14 @@ void __init ralink_clk_init(void)
|
||||
ralink_clk_add("10000500.uart", 40000000);
|
||||
ralink_clk_add("10000b00.spi", 40000000);
|
||||
ralink_clk_add("10000c00.uartlite", 40000000);
|
||||
+
|
||||
+#ifdef CONFIG_USB
|
||||
+ /*
|
||||
+ * When the CPU goes into sleep mode, the BUS clock will be too low for
|
||||
+ * USB to function properly
|
||||
+ */
|
||||
+ rt_sysc_m32(0x1f1f, 0x303, SYSC_REG_CPU_SYS_CLKCFG);
|
||||
+#endif
|
||||
}
|
||||
|
||||
void __init ralink_of_remap(void)
|
||||
@ -0,0 +1,44 @@
|
||||
From c464a54f9a4a959d09206583b11ae99740e0f267 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Fri, 9 Aug 2013 20:12:59 +0200
|
||||
Subject: [PATCH 18/25] DT: Add documentation for spi-rt2880
|
||||
|
||||
Describe the SPI master found on the MIPS based Ralink RT2880 SoC.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
.../devicetree/bindings/spi/spi-rt2880.txt | 28 ++++++++++++++++++++
|
||||
1 file changed, 28 insertions(+)
|
||||
create mode 100644 Documentation/devicetree/bindings/spi/spi-rt2880.txt
|
||||
|
||||
--- /dev/null
|
||||
+++ b/Documentation/devicetree/bindings/spi/spi-rt2880.txt
|
||||
@@ -0,0 +1,28 @@
|
||||
+Ralink SoC RT2880 SPI master controller.
|
||||
+
|
||||
+This SPI controller is found on most wireless SoCs made by ralink.
|
||||
+
|
||||
+Required properties:
|
||||
+- compatible : "ralink,rt2880-spi"
|
||||
+- reg : The register base for the controller.
|
||||
+- #address-cells : <1>, as required by generic SPI binding.
|
||||
+- #size-cells : <0>, also as required by generic SPI binding.
|
||||
+
|
||||
+Child nodes as per the generic SPI binding.
|
||||
+
|
||||
+Example:
|
||||
+
|
||||
+ spi@b00 {
|
||||
+ compatible = "ralink,rt2880-spi";
|
||||
+ reg = <0xb00 0x100>;
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ m25p80@0 {
|
||||
+ compatible = "m25p80";
|
||||
+ reg = <0>;
|
||||
+ spi-max-frequency = <10000000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
@ -0,0 +1,629 @@
|
||||
From 5845a3aa53cf42893db05662aa9bb91387949ff6 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Mon, 12 Aug 2013 18:11:33 +0200
|
||||
Subject: [PATCH 22/25] MIPS: ralink: update dts files
|
||||
|
||||
Add the devicetree nodes needed to make the newly merged drivers work.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/ralink/dts/mt7620a.dtsi | 135 +++++++++++++++++++++++
|
||||
arch/mips/ralink/dts/rt3050.dtsi | 156 ++++++++++++++++++++++++++
|
||||
arch/mips/ralink/dts/rt3883.dtsi | 219 +++++++++++++++++++++++++++++++++++++
|
||||
3 files changed, 510 insertions(+)
|
||||
|
||||
--- a/arch/mips/ralink/dts/mt7620a.dtsi
|
||||
+++ b/arch/mips/ralink/dts/mt7620a.dtsi
|
||||
@@ -29,10 +29,32 @@
|
||||
reg = <0x0 0x100>;
|
||||
};
|
||||
|
||||
+ timer@100 {
|
||||
+ compatible = "ralink,mt7620a-timer", "ralink,rt2880-timer";
|
||||
+ reg = <0x100 0x20>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <1>;
|
||||
+ };
|
||||
+
|
||||
+ watchdog@120 {
|
||||
+ compatible = "ralink,mt7620a-wdt", "ralink,rt2880-wdt";
|
||||
+ reg = <0x120 0x10>;
|
||||
+
|
||||
+ resets = <&rstctrl 8>;
|
||||
+ reset-names = "wdt";
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <1>;
|
||||
+ };
|
||||
+
|
||||
intc: intc@200 {
|
||||
compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
|
||||
reg = <0x200 0x100>;
|
||||
|
||||
+ resets = <&rstctrl 19>;
|
||||
+ reset-names = "intc";
|
||||
+
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
@@ -43,16 +65,129 @@
|
||||
memc@300 {
|
||||
compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
|
||||
reg = <0x300 0x100>;
|
||||
+
|
||||
+ resets = <&rstctrl 20>;
|
||||
+ reset-names = "mc";
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <3>;
|
||||
+ };
|
||||
+
|
||||
+ uart@500 {
|
||||
+ compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
|
||||
+ reg = <0x500 0x100>;
|
||||
+
|
||||
+ resets = <&rstctrl 12>;
|
||||
+ reset-names = "uart";
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <5>;
|
||||
+
|
||||
+ reg-shift = <2>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ gpio0: gpio@600 {
|
||||
+ compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
|
||||
+ reg = <0x600 0x34>;
|
||||
+
|
||||
+ resets = <&rstctrl 13>;
|
||||
+ reset-names = "pio";
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <6>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ ralink,gpio-base = <0>;
|
||||
+ ralink,num-gpios = <24>;
|
||||
+ ralink,register-map = [ 00 04 08 0c
|
||||
+ 20 24 28 2c
|
||||
+ 30 34 ];
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ gpio1: gpio@638 {
|
||||
+ compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
|
||||
+ reg = <0x638 0x24>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <6>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ ralink,gpio-base = <24>;
|
||||
+ ralink,num-gpios = <16>;
|
||||
+ ralink,register-map = [ 00 04 08 0c
|
||||
+ 10 14 18 1c
|
||||
+ 20 24 ];
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ gpio2: gpio@660 {
|
||||
+ compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
|
||||
+ reg = <0x660 0x24>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <6>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ ralink,gpio-base = <40>;
|
||||
+ ralink,num-gpios = <32>;
|
||||
+ ralink,register-map = [ 00 04 08 0c
|
||||
+ 10 14 18 1c
|
||||
+ 20 24 ];
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ spi@b00 {
|
||||
+ compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi";
|
||||
+ reg = <0xb00 0x100>;
|
||||
+
|
||||
+ resets = <&rstctrl 18>;
|
||||
+ reset-names = "spi";
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
};
|
||||
|
||||
uartlite@c00 {
|
||||
compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
|
||||
reg = <0xc00 0x100>;
|
||||
|
||||
+ resets = <&rstctrl 19>;
|
||||
+ reset-names = "uartl";
|
||||
+
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <12>;
|
||||
|
||||
reg-shift = <2>;
|
||||
};
|
||||
+
|
||||
+ systick@d00 {
|
||||
+ compatible = "ralink,mt7620a-systick", "ralink,cevt-systick";
|
||||
+ reg = <0xd00 0x10>;
|
||||
+
|
||||
+ resets = <&rstctrl 28>;
|
||||
+ reset-names = "intc";
|
||||
+
|
||||
+ interrupt-parent = <&cpuintc>;
|
||||
+ interrupts = <7>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rstctrl: rstctrl {
|
||||
+ compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
|
||||
+ #reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
--- a/arch/mips/ralink/dts/rt3050.dtsi
|
||||
+++ b/arch/mips/ralink/dts/rt3050.dtsi
|
||||
@@ -9,6 +9,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ chosen {
|
||||
+ bootargs = "console=ttyS0,57600";
|
||||
+ };
|
||||
+
|
||||
cpuintc: cpuintc@0 {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
@@ -29,10 +33,32 @@
|
||||
reg = <0x0 0x100>;
|
||||
};
|
||||
|
||||
+ timer@100 {
|
||||
+ compatible = "ralink,rt3052-timer", "ralink,rt2880-timer";
|
||||
+ reg = <0x100 0x20>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <1>;
|
||||
+ };
|
||||
+
|
||||
+ watchdog@120 {
|
||||
+ compatible = "ralink,rt3052-wdt", "ralink,rt2880-wdt";
|
||||
+ reg = <0x120 0x10>;
|
||||
+
|
||||
+ resets = <&rstctrl 8>;
|
||||
+ reset-names = "wdt";
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <1>;
|
||||
+ };
|
||||
+
|
||||
intc: intc@200 {
|
||||
compatible = "ralink,rt3052-intc", "ralink,rt2880-intc";
|
||||
reg = <0x200 0x100>;
|
||||
|
||||
+ resets = <&rstctrl 19>;
|
||||
+ reset-names = "intc";
|
||||
+
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
@@ -43,17 +69,144 @@
|
||||
memc@300 {
|
||||
compatible = "ralink,rt3052-memc", "ralink,rt3050-memc";
|
||||
reg = <0x300 0x100>;
|
||||
+
|
||||
+ resets = <&rstctrl 20>;
|
||||
+ reset-names = "mc";
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <3>;
|
||||
+ };
|
||||
+
|
||||
+ uart@500 {
|
||||
+ compatible = "ralink,rt5350-uart", "ralink,rt2880-uart", "ns16550a";
|
||||
+ reg = <0x500 0x100>;
|
||||
+
|
||||
+ resets = <&rstctrl 12>;
|
||||
+ reset-names = "uart";
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <5>;
|
||||
+
|
||||
+ reg-shift = <2>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ gpio0: gpio@600 {
|
||||
+ compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
|
||||
+ reg = <0x600 0x34>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ ralink,gpio-base = <0>;
|
||||
+ ralink,num-gpios = <24>;
|
||||
+ ralink,register-map = [ 00 04 08 0c
|
||||
+ 20 24 28 2c
|
||||
+ 30 34 ];
|
||||
+
|
||||
+ resets = <&rstctrl 13>;
|
||||
+ reset-names = "pio";
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <6>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ gpio1: gpio@638 {
|
||||
+ compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
|
||||
+ reg = <0x638 0x24>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ ralink,gpio-base = <24>;
|
||||
+ ralink,num-gpios = <16>;
|
||||
+ ralink,register-map = [ 00 04 08 0c
|
||||
+ 10 14 18 1c
|
||||
+ 20 24 ];
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ gpio2: gpio@660 {
|
||||
+ compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
|
||||
+ reg = <0x660 0x24>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ ralink,gpio-base = <40>;
|
||||
+ ralink,num-gpios = <12>;
|
||||
+ ralink,register-map = [ 00 04 08 0c
|
||||
+ 10 14 18 1c
|
||||
+ 20 24 ];
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ spi@b00 {
|
||||
+ compatible = "ralink,rt3050-spi", "ralink,rt2880-spi";
|
||||
+ reg = <0xb00 0x100>;
|
||||
+
|
||||
+ resets = <&rstctrl 18>;
|
||||
+ reset-names = "spi";
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
};
|
||||
|
||||
uartlite@c00 {
|
||||
compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
|
||||
reg = <0xc00 0x100>;
|
||||
|
||||
+ resets = <&rstctrl 19>;
|
||||
+ reset-names = "uartl";
|
||||
+
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <12>;
|
||||
|
||||
reg-shift = <2>;
|
||||
};
|
||||
+
|
||||
+ };
|
||||
+
|
||||
+ rstctrl: rstctrl {
|
||||
+ compatible = "ralink,rt3050-reset", "ralink,rt2880-reset";
|
||||
+ #reset-cells = <1>;
|
||||
+ };
|
||||
+
|
||||
+ ethernet@10100000 {
|
||||
+ compatible = "ralink,rt3050-eth";
|
||||
+ reg = <0x10100000 10000>;
|
||||
+
|
||||
+ interrupt-parent = <&cpuintc>;
|
||||
+ interrupts = <5>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ esw@10110000 {
|
||||
+ compatible = "ralink,rt3050-esw";
|
||||
+ reg = <0x10110000 8000>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <17>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ wmac@10180000 {
|
||||
+ compatible = "ralink,rt3050-wmac", "ralink,rt2880-wmac";
|
||||
+ reg = <0x10180000 40000>;
|
||||
+
|
||||
+ interrupt-parent = <&cpuintc>;
|
||||
+ interrupts = <6>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
};
|
||||
|
||||
usb@101c0000 {
|
||||
@@ -63,6 +216,9 @@
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <18>;
|
||||
|
||||
+ resets = <&rstctrl 22>;
|
||||
+ reset-names = "otg";
|
||||
+
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
--- a/arch/mips/ralink/dts/rt3883.dtsi
|
||||
+++ b/arch/mips/ralink/dts/rt3883.dtsi
|
||||
@@ -29,10 +29,32 @@
|
||||
reg = <0x0 0x100>;
|
||||
};
|
||||
|
||||
+ timer@100 {
|
||||
+ compatible = "ralink,rt3883-timer", "ralink,rt2880-timer";
|
||||
+ reg = <0x100 0x20>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <1>;
|
||||
+ };
|
||||
+
|
||||
+ watchdog@120 {
|
||||
+ compatible = "ralink,rt3883-wdt", "ralink,rt2880-wdt";
|
||||
+ reg = <0x120 0x10>;
|
||||
+
|
||||
+ resets = <&rstctrl 8>;
|
||||
+ reset-names = "wdt";
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <1>;
|
||||
+ };
|
||||
+
|
||||
intc: intc@200 {
|
||||
compatible = "ralink,rt3883-intc", "ralink,rt2880-intc";
|
||||
reg = <0x200 0x100>;
|
||||
|
||||
+ resets = <&rstctrl 19>;
|
||||
+ reset-names = "intc";
|
||||
+
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
@@ -43,16 +65,213 @@
|
||||
memc@300 {
|
||||
compatible = "ralink,rt3883-memc", "ralink,rt3050-memc";
|
||||
reg = <0x300 0x100>;
|
||||
+
|
||||
+ resets = <&rstctrl 20>;
|
||||
+ reset-names = "mc";
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <3>;
|
||||
+ };
|
||||
+
|
||||
+ uart@500 {
|
||||
+ compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
|
||||
+ reg = <0x500 0x100>;
|
||||
+
|
||||
+ resets = <&rstctrl 12>;
|
||||
+ reset-names = "uart";
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <5>;
|
||||
+
|
||||
+ reg-shift = <2>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ gpio0: gpio@600 {
|
||||
+ compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
|
||||
+ reg = <0x600 0x34>;
|
||||
+
|
||||
+ resets = <&rstctrl 13>;
|
||||
+ reset-names = "pio";
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <6>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ ralink,gpio-base = <0>;
|
||||
+ ralink,num-gpios = <24>;
|
||||
+ ralink,register-map = [ 00 04 08 0c
|
||||
+ 20 24 28 2c
|
||||
+ 30 34 ];
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ gpio1: gpio@638 {
|
||||
+ compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
|
||||
+ reg = <0x638 0x24>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ ralink,gpio-base = <24>;
|
||||
+ ralink,num-gpios = <16>;
|
||||
+ ralink,register-map = [ 00 04 08 0c
|
||||
+ 10 14 18 1c
|
||||
+ 20 24 ];
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ gpio2: gpio@660 {
|
||||
+ compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
|
||||
+ reg = <0x660 0x24>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ ralink,gpio-base = <40>;
|
||||
+ ralink,num-gpios = <32>;
|
||||
+ ralink,register-map = [ 00 04 08 0c
|
||||
+ 10 14 18 1c
|
||||
+ 20 24 ];
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ gpio3: gpio@688 {
|
||||
+ compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
|
||||
+ reg = <0x688 0x24>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ ralink,gpio-base = <72>;
|
||||
+ ralink,num-gpios = <24>;
|
||||
+ ralink,register-map = [ 00 04 08 0c
|
||||
+ 10 14 18 1c
|
||||
+ 20 24 ];
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ spi0: spi@b00 {
|
||||
+ compatible = "ralink,rt3883-spi", "ralink,rt2880-spi";
|
||||
+ reg = <0xb00 0x100>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ resets = <&rstctrl 18>;
|
||||
+ reset-names = "spi";
|
||||
+
|
||||
+ status = "disabled";
|
||||
};
|
||||
|
||||
uartlite@c00 {
|
||||
compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
|
||||
reg = <0xc00 0x100>;
|
||||
|
||||
+ resets = <&rstctrl 19>;
|
||||
+ reset-names = "uartl";
|
||||
+
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <12>;
|
||||
|
||||
reg-shift = <2>;
|
||||
};
|
||||
};
|
||||
+
|
||||
+ rstctrl: rstctrl {
|
||||
+ compatible = "ralink,rt3883-reset", "ralink,rt2880-reset";
|
||||
+ #reset-cells = <1>;
|
||||
+ };
|
||||
+
|
||||
+ pci@10140000 {
|
||||
+ compatible = "ralink,rt3883-pci";
|
||||
+ reg = <0x10140000 0x20000>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges; /* direct mapping */
|
||||
+
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ pciintc: interrupt-controller {
|
||||
+ interrupt-controller;
|
||||
+ #address-cells = <0>;
|
||||
+ #interrupt-cells = <1>;
|
||||
+
|
||||
+ interrupt-parent = <&cpuintc>;
|
||||
+ interrupts = <4>;
|
||||
+ };
|
||||
+
|
||||
+ host-bridge {
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
+ #interrupt-cells = <1>;
|
||||
+
|
||||
+ device_type = "pci";
|
||||
+
|
||||
+ bus-range = <0 255>;
|
||||
+ ranges = <
|
||||
+ 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
|
||||
+ 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
|
||||
+ >;
|
||||
+
|
||||
+ interrupt-map-mask = <0xf800 0 0 7>;
|
||||
+ interrupt-map = <
|
||||
+ /* IDSEL 17 */
|
||||
+ 0x8800 0 0 1 &pciintc 18
|
||||
+ 0x8800 0 0 2 &pciintc 18
|
||||
+ 0x8800 0 0 3 &pciintc 18
|
||||
+ 0x8800 0 0 4 &pciintc 18
|
||||
+ /* IDSEL 18 */
|
||||
+ 0x9000 0 0 1 &pciintc 19
|
||||
+ 0x9000 0 0 2 &pciintc 19
|
||||
+ 0x9000 0 0 3 &pciintc 19
|
||||
+ 0x9000 0 0 4 &pciintc 19
|
||||
+ >;
|
||||
+
|
||||
+ pci-bridge@1 {
|
||||
+ reg = <0x0800 0 0 0 0>;
|
||||
+ device_type = "pci";
|
||||
+ #interrupt-cells = <1>;
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ ralink,pci-slot = <1>;
|
||||
+
|
||||
+ interrupt-map-mask = <0x0 0 0 0>;
|
||||
+ interrupt-map = <0x0 0 0 0 &pciintc 20>;
|
||||
+ };
|
||||
+
|
||||
+ pci-slot@17 {
|
||||
+ reg = <0x8800 0 0 0 0>;
|
||||
+ device_type = "pci";
|
||||
+ #interrupt-cells = <1>;
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
+
|
||||
+ ralink,pci-slot = <17>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pci-slot@18 {
|
||||
+ reg = <0x9000 0 0 0 0>;
|
||||
+ device_type = "pci";
|
||||
+ #interrupt-cells = <1>;
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
+
|
||||
+ ralink,pci-slot = <18>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
@ -0,0 +1,95 @@
|
||||
From f6dc5d40c766e5ff9b18b93a1b6f7a576655f9c4 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sun, 28 Jul 2013 16:26:41 +0200
|
||||
Subject: [PATCH 21/25] MIPS: ralink: add cpu frequency scaling
|
||||
|
||||
This feature will break udelay() and cause the delay loop to have longer delays
|
||||
when the frequency is scaled causing a performance hit.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/ralink/cevt-rt3352.c | 36 ++++++++++++++++++++++++++++++++++++
|
||||
1 file changed, 36 insertions(+)
|
||||
|
||||
--- a/arch/mips/ralink/cevt-rt3352.c
|
||||
+++ b/arch/mips/ralink/cevt-rt3352.c
|
||||
@@ -29,6 +29,10 @@
|
||||
/* enable the counter */
|
||||
#define CFG_CNT_EN 0x1
|
||||
|
||||
+/* mt7620 frequency scaling defines */
|
||||
+#define CLK_LUT_CFG 0x40
|
||||
+#define SLEEP_EN BIT(31)
|
||||
+
|
||||
struct systick_device {
|
||||
void __iomem *membase;
|
||||
struct clock_event_device dev;
|
||||
@@ -36,6 +40,8 @@ struct systick_device {
|
||||
int freq_scale;
|
||||
};
|
||||
|
||||
+static void (*systick_freq_scaling)(struct systick_device *sdev, int status);
|
||||
+
|
||||
static void systick_set_clock_mode(enum clock_event_mode mode,
|
||||
struct clock_event_device *evt);
|
||||
|
||||
@@ -87,6 +93,21 @@ static struct irqaction systick_irqactio
|
||||
.dev_id = &systick.dev,
|
||||
};
|
||||
|
||||
+static inline void mt7620_freq_scaling(struct systick_device *sdev, int status)
|
||||
+{
|
||||
+ if (sdev->freq_scale == status)
|
||||
+ return;
|
||||
+
|
||||
+ sdev->freq_scale = status;
|
||||
+
|
||||
+ pr_info("%s: %s autosleep mode\n", systick.dev.name,
|
||||
+ (status) ? ("enable") : ("disable"));
|
||||
+ if (status)
|
||||
+ rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) | SLEEP_EN, CLK_LUT_CFG);
|
||||
+ else
|
||||
+ rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) & ~SLEEP_EN, CLK_LUT_CFG);
|
||||
+}
|
||||
+
|
||||
static void systick_set_clock_mode(enum clock_event_mode mode,
|
||||
struct clock_event_device *evt)
|
||||
{
|
||||
@@ -101,9 +122,13 @@ static void systick_set_clock_mode(enum
|
||||
sdev->irq_requested = 1;
|
||||
iowrite32(CFG_EXT_STK_EN | CFG_CNT_EN,
|
||||
systick.membase + SYSTICK_CONFIG);
|
||||
+ if (systick_freq_scaling)
|
||||
+ systick_freq_scaling(sdev, 1);
|
||||
break;
|
||||
|
||||
case CLOCK_EVT_MODE_SHUTDOWN:
|
||||
+ if (systick_freq_scaling)
|
||||
+ systick_freq_scaling(sdev, 0);
|
||||
if (sdev->irq_requested)
|
||||
free_irq(systick.dev.irq, &systick_irqaction);
|
||||
sdev->irq_requested = 0;
|
||||
@@ -116,12 +141,23 @@ static void systick_set_clock_mode(enum
|
||||
}
|
||||
}
|
||||
|
||||
+static const struct of_device_id systick_match[] = {
|
||||
+ { .compatible = "ralink,mt7620-systick", .data = mt7620_freq_scaling},
|
||||
+ {},
|
||||
+};
|
||||
+
|
||||
static void __init ralink_systick_init(struct device_node *np)
|
||||
{
|
||||
+ const struct of_device_id *match;
|
||||
+
|
||||
systick.membase = of_iomap(np, 0);
|
||||
if (!systick.membase)
|
||||
return;
|
||||
|
||||
+ match = of_match_node(systick_match, np);
|
||||
+ if (match)
|
||||
+ systick_freq_scaling = match->data;
|
||||
+
|
||||
systick_irqaction.name = np->name;
|
||||
systick.dev.name = np->name;
|
||||
clockevents_calc_mult_shift(&systick.dev, SYSTICK_FREQ, 60);
|
||||
@ -1,126 +0,0 @@
|
||||
From 0cc20912b376305452cdc5c8e7b97e156ba90e93 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Wed, 8 May 2013 22:08:39 +0200
|
||||
Subject: [PATCH 28/33] reset: MIPS: ralink: add core/device reset wrapper
|
||||
|
||||
Add a helper for reseting different devices ont he SoC.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/Kconfig | 1 +
|
||||
arch/mips/ralink/of.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++
|
||||
arch/mips/ralink/reset.c | 1 +
|
||||
3 files changed, 61 insertions(+)
|
||||
|
||||
--- a/arch/mips/Kconfig
|
||||
+++ b/arch/mips/Kconfig
|
||||
@@ -444,6 +444,7 @@ config RALINK
|
||||
select HAVE_MACH_CLKDEV
|
||||
select CLKDEV_LOOKUP
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
+ select ARCH_HAS_RESET_CONTROLLER
|
||||
|
||||
config SGI_IP22
|
||||
bool "SGI IP22 (Indy/Indigo2)"
|
||||
--- a/arch/mips/ralink/of.c
|
||||
+++ b/arch/mips/ralink/of.c
|
||||
@@ -14,16 +14,22 @@
|
||||
#include <linux/sizes.h>
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/kernel.h>
|
||||
+#include <linux/module.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/of_address.h>
|
||||
+#include <linux/reset-controller.h>
|
||||
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/addrspace.h>
|
||||
|
||||
+#include <asm/mach-ralink/ralink_regs.h>
|
||||
+
|
||||
#include "common.h"
|
||||
|
||||
+#define SYSC_REG_RESET_CTRL 0x034
|
||||
+
|
||||
__iomem void *rt_sysc_membase;
|
||||
__iomem void *rt_memc_membase;
|
||||
|
||||
@@ -96,6 +102,53 @@ void __init plat_mem_setup(void)
|
||||
soc_info.mem_size_max * SZ_1M);
|
||||
}
|
||||
|
||||
+static int ralink_assert_device(struct reset_controller_dev *rcdev, unsigned long id)
|
||||
+{
|
||||
+ u32 val;
|
||||
+
|
||||
+ if (id < 8)
|
||||
+ return -1;
|
||||
+
|
||||
+ val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
|
||||
+ val |= BIT(id);
|
||||
+ rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int ralink_deassert_device(struct reset_controller_dev *rcdev, unsigned long id)
|
||||
+{
|
||||
+ u32 val;
|
||||
+
|
||||
+ if (id < 8)
|
||||
+ return -1;
|
||||
+
|
||||
+ val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
|
||||
+ val &= ~BIT(id);
|
||||
+ rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int ralink_reset_device(struct reset_controller_dev *rcdev, unsigned long id)
|
||||
+{
|
||||
+ ralink_assert_device(rcdev, id);
|
||||
+ return ralink_deassert_device(rcdev, id);
|
||||
+}
|
||||
+
|
||||
+static struct reset_control_ops reset_ops = {
|
||||
+ .reset = ralink_reset_device,
|
||||
+ .assert = ralink_assert_device,
|
||||
+ .deassert = ralink_deassert_device,
|
||||
+};
|
||||
+
|
||||
+static struct reset_controller_dev reset_dev = {
|
||||
+ .ops = &reset_ops,
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .nr_resets = 32,
|
||||
+ .of_reset_n_cells = 1,
|
||||
+};
|
||||
+
|
||||
static int __init plat_of_setup(void)
|
||||
{
|
||||
static struct of_device_id of_ids[3];
|
||||
@@ -110,6 +163,12 @@ static int __init plat_of_setup(void)
|
||||
if (of_platform_populate(NULL, of_ids, NULL, NULL))
|
||||
panic("failed to populate DT\n");
|
||||
|
||||
+ reset_dev.of_node = of_find_compatible_node(NULL, NULL, "ralink,rt2880-reset");
|
||||
+ if (!reset_dev.of_node)
|
||||
+ panic("Failed to find reset controller node");
|
||||
+
|
||||
+ reset_controller_register(&reset_dev);
|
||||
+
|
||||
ralink_pinmux();
|
||||
|
||||
return 0;
|
||||
--- a/arch/mips/ralink/reset.c
|
||||
+++ b/arch/mips/ralink/reset.c
|
||||
@@ -10,6 +10,7 @@
|
||||
|
||||
#include <linux/pm.h>
|
||||
#include <linux/io.h>
|
||||
+#include <linux/module.h>
|
||||
|
||||
#include <asm/reboot.h>
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
From a1f29e15505226c6bc3a714daf91edccfc3a9e13 Mon Sep 17 00:00:00 2001
|
||||
From cdc1b12b3debaf5b3894fd146e73221a8acd0152 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sun, 14 Jul 2013 23:08:11 +0200
|
||||
Subject: [PATCH 01/33] MIPS: use set_mode() to enable/disable the cevt-r4k
|
||||
Subject: [PATCH 20/25] MIPS: use set_mode() to enable/disable the cevt-r4k
|
||||
irq
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/kernel/cevt-r4k.c | 39 ++++++++++++++++++++++++++-------------
|
||||
1 file changed, 26 insertions(+), 13 deletions(-)
|
||||
@ -0,0 +1,29 @@
|
||||
From 2922a8de996956893bb98e4aa91be9774c958336 Mon Sep 17 00:00:00 2001
|
||||
From: Stephen Warren <swarren@wwwdotorg.org>
|
||||
Date: Tue, 21 May 2013 20:36:34 -0600
|
||||
Subject: [PATCH] spi: introduce macros to set bits_per_word_mask
|
||||
|
||||
Introduce two macros to make setting up spi_master.bits_per_word_mask
|
||||
easier, and avoid mistakes like writing BIT(n) instead of BIT(n - 1).
|
||||
|
||||
SPI_BPW_MASK is for a single supported value of bits_per_word_mask.
|
||||
|
||||
SPI_BPW_RANGE_MASK represents a contiguous set of bit lengths.
|
||||
|
||||
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
|
||||
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
||||
---
|
||||
include/linux/spi/spi.h | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/include/linux/spi/spi.h
|
||||
+++ b/include/linux/spi/spi.h
|
||||
@@ -308,6 +308,8 @@ struct spi_master {
|
||||
|
||||
/* bitmask of supported bits_per_word for transfers */
|
||||
u32 bits_per_word_mask;
|
||||
+#define SPI_BPW_MASK(bits) BIT((bits) - 1)
|
||||
+#define SPI_BPW_RANGE_MASK(min, max) ((BIT(max) - 1) - (BIT(min) - 1))
|
||||
|
||||
/* other constraints relevant to this driver */
|
||||
u16 flags;
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,158 +0,0 @@
|
||||
CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
|
||||
CONFIG_ARCH_DISCARD_MEMBLOCK=y
|
||||
CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
|
||||
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
|
||||
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
|
||||
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
|
||||
CONFIG_ARCH_REQUIRE_GPIOLIB=y
|
||||
CONFIG_ARCH_SUSPEND_POSSIBLE=y
|
||||
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
CONFIG_CEVT_R4K=y
|
||||
CONFIG_CLKDEV_LOOKUP=y
|
||||
CONFIG_CLONE_BACKWARDS=y
|
||||
CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
|
||||
CONFIG_CMDLINE_BOOL=y
|
||||
# CONFIG_CMDLINE_OVERRIDE is not set
|
||||
CONFIG_CPU_GENERIC_DUMP_TLB=y
|
||||
CONFIG_CPU_HAS_PREFETCH=y
|
||||
CONFIG_CPU_HAS_SYNC=y
|
||||
CONFIG_CPU_LITTLE_ENDIAN=y
|
||||
CONFIG_CPU_MIPS32=y
|
||||
# CONFIG_CPU_MIPS32_R1 is not set
|
||||
CONFIG_CPU_MIPS32_R2=y
|
||||
CONFIG_CPU_MIPSR2=y
|
||||
CONFIG_CPU_R4K_CACHE_TLB=y
|
||||
CONFIG_CPU_R4K_FPU=y
|
||||
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
|
||||
CONFIG_CPU_SUPPORTS_HIGHMEM=y
|
||||
CONFIG_CSRC_R4K=y
|
||||
CONFIG_DECOMPRESS_LZMA=y
|
||||
CONFIG_DMA_NONCOHERENT=y
|
||||
# CONFIG_DTB_RT2880_EVAL is not set
|
||||
CONFIG_DTB_RT_NONE=y
|
||||
CONFIG_DTC=y
|
||||
CONFIG_EARLY_PRINTK=y
|
||||
CONFIG_GENERIC_ATOMIC64=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
|
||||
CONFIG_GENERIC_CMOS_UPDATE=y
|
||||
CONFIG_GENERIC_GPIO=y
|
||||
CONFIG_GENERIC_IO=y
|
||||
CONFIG_GENERIC_IRQ_SHOW=y
|
||||
CONFIG_GENERIC_SMP_IDLE_THREAD=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIO_DEVRES=y
|
||||
CONFIG_GPIO_RALINK=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_HARDWARE_WATCHPOINTS=y
|
||||
CONFIG_HAS_DMA=y
|
||||
CONFIG_HAS_IOMEM=y
|
||||
CONFIG_HAS_IOPORT=y
|
||||
# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
|
||||
CONFIG_HAVE_ARCH_JUMP_LABEL=y
|
||||
CONFIG_HAVE_ARCH_KGDB=y
|
||||
# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
|
||||
CONFIG_HAVE_CLK=y
|
||||
CONFIG_HAVE_C_RECORDMCOUNT=y
|
||||
CONFIG_HAVE_DEBUG_KMEMLEAK=y
|
||||
CONFIG_HAVE_DMA_API_DEBUG=y
|
||||
CONFIG_HAVE_DMA_ATTRS=y
|
||||
CONFIG_HAVE_DYNAMIC_FTRACE=y
|
||||
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
|
||||
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
|
||||
CONFIG_HAVE_FUNCTION_TRACER=y
|
||||
CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
|
||||
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
|
||||
CONFIG_HAVE_GENERIC_HARDIRQS=y
|
||||
CONFIG_HAVE_IDE=y
|
||||
CONFIG_HAVE_MACH_CLKDEV=y
|
||||
CONFIG_HAVE_MEMBLOCK=y
|
||||
CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
|
||||
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
|
||||
CONFIG_HAVE_NET_DSA=y
|
||||
CONFIG_HAVE_OPROFILE=y
|
||||
CONFIG_HAVE_PERF_EVENTS=y
|
||||
CONFIG_HW_HAS_PCI=y
|
||||
CONFIG_HW_RANDOM=m
|
||||
CONFIG_IMAGE_CMDLINE_HACK=y
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
CONFIG_IRQCHIP=y
|
||||
CONFIG_IRQ_CPU=y
|
||||
CONFIG_IRQ_DOMAIN=y
|
||||
CONFIG_IRQ_FORCED_THREADING=y
|
||||
CONFIG_IRQ_WORK=y
|
||||
CONFIG_M25PXX_USE_FAST_READ=y
|
||||
CONFIG_MDIO_BOARDINFO=y
|
||||
# CONFIG_MII is not set
|
||||
CONFIG_MIPS=y
|
||||
# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
|
||||
CONFIG_MIPS_L1_CACHE_SHIFT=4
|
||||
# CONFIG_MIPS_MACHINE is not set
|
||||
CONFIG_MIPS_MT_DISABLED=y
|
||||
CONFIG_MODULES_USE_ELF_REL=y
|
||||
# CONFIG_MTD_CFI_INTELEXT is not set
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_M25P80=y
|
||||
CONFIG_MTD_OF_PARTS=y
|
||||
CONFIG_MTD_PHYSMAP=y
|
||||
CONFIG_MTD_PHYSMAP_OF=y
|
||||
CONFIG_MTD_UIMAGE_SPLIT=y
|
||||
CONFIG_NEED_DMA_MAP_STATE=y
|
||||
CONFIG_NEED_PER_CPU_KM=y
|
||||
CONFIG_NET_RALINK=y
|
||||
CONFIG_NET_RALINK_MDIO=y
|
||||
CONFIG_NET_RALINK_MDIO_RT2880=y
|
||||
CONFIG_OF=y
|
||||
CONFIG_OF_ADDRESS=y
|
||||
CONFIG_OF_DEVICE=y
|
||||
# CONFIG_OF_DISPLAY_TIMING is not set
|
||||
CONFIG_OF_EARLY_FLATTREE=y
|
||||
CONFIG_OF_FLATTREE=y
|
||||
CONFIG_OF_GPIO=y
|
||||
CONFIG_OF_IRQ=y
|
||||
CONFIG_OF_MDIO=y
|
||||
CONFIG_OF_MTD=y
|
||||
CONFIG_OF_NET=y
|
||||
# CONFIG_OF_VIDEOMODE is not set
|
||||
CONFIG_PAGEFLAGS_EXTENDED=y
|
||||
# CONFIG_PCI is not set
|
||||
CONFIG_PERF_USE_VMALLOC=y
|
||||
CONFIG_PHYLIB=y
|
||||
# CONFIG_PREEMPT_RCU is not set
|
||||
CONFIG_RALINK=y
|
||||
# CONFIG_RALINK_ILL_ACC is not set
|
||||
# CONFIG_RALINK_USBPHY is not set
|
||||
CONFIG_RALINK_WDT=y
|
||||
# CONFIG_RCU_STALL_COMMON is not set
|
||||
CONFIG_RESET_CONTROLLER=y
|
||||
# CONFIG_SCSI_DMA is not set
|
||||
CONFIG_SERIAL_8250_NR_UARTS=4
|
||||
CONFIG_SERIAL_8250_RT288X=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
# CONFIG_SLAB is not set
|
||||
CONFIG_SLUB=y
|
||||
# CONFIG_SOC_MT7620 is not set
|
||||
CONFIG_SOC_RT288X=y
|
||||
# CONFIG_SOC_RT305X is not set
|
||||
# CONFIG_SOC_RT3883 is not set
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_MASTER=y
|
||||
CONFIG_SPI_RALINK=y
|
||||
CONFIG_SWCONFIG=y
|
||||
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
|
||||
CONFIG_SYS_HAS_CPU_MIPS32_R2=y
|
||||
CONFIG_SYS_HAS_EARLY_PRINTK=y
|
||||
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
|
||||
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
|
||||
CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
|
||||
CONFIG_TICK_CPU_ACCOUNTING=y
|
||||
CONFIG_UIDGID_CONVERTED=y
|
||||
# CONFIG_USB_ARCH_HAS_EHCI is not set
|
||||
# CONFIG_USB_ARCH_HAS_HCD is not set
|
||||
# CONFIG_USB_ARCH_HAS_OHCI is not set
|
||||
# CONFIG_USB_ARCH_HAS_XHCI is not set
|
||||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_USE_OF=y
|
||||
CONFIG_WATCHDOG_CORE=y
|
||||
CONFIG_ZONE_DMA_FLAG=0
|
||||
@ -1,158 +0,0 @@
|
||||
CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
|
||||
CONFIG_ARCH_DISCARD_MEMBLOCK=y
|
||||
CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
|
||||
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
|
||||
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
|
||||
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
|
||||
CONFIG_ARCH_REQUIRE_GPIOLIB=y
|
||||
CONFIG_ARCH_SUSPEND_POSSIBLE=y
|
||||
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
CONFIG_CEVT_R4K=y
|
||||
CONFIG_CLKDEV_LOOKUP=y
|
||||
CONFIG_CLKEVT_RT3352=y
|
||||
CONFIG_CLKSRC_MMIO=y
|
||||
CONFIG_CLKSRC_OF=y
|
||||
CONFIG_CLONE_BACKWARDS=y
|
||||
CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
|
||||
CONFIG_CMDLINE_BOOL=y
|
||||
# CONFIG_CMDLINE_OVERRIDE is not set
|
||||
CONFIG_CPU_GENERIC_DUMP_TLB=y
|
||||
CONFIG_CPU_HAS_PREFETCH=y
|
||||
CONFIG_CPU_HAS_SYNC=y
|
||||
CONFIG_CPU_LITTLE_ENDIAN=y
|
||||
CONFIG_CPU_MIPS32=y
|
||||
# CONFIG_CPU_MIPS32_R1 is not set
|
||||
CONFIG_CPU_MIPS32_R2=y
|
||||
CONFIG_CPU_MIPSR2=y
|
||||
CONFIG_CPU_R4K_CACHE_TLB=y
|
||||
CONFIG_CPU_R4K_FPU=y
|
||||
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
|
||||
CONFIG_CPU_SUPPORTS_HIGHMEM=y
|
||||
CONFIG_CSRC_R4K=y
|
||||
CONFIG_DECOMPRESS_LZMA=y
|
||||
CONFIG_DMA_NONCOHERENT=y
|
||||
# CONFIG_DTB_RT305X_EVAL is not set
|
||||
# CONFIG_DTB_RT5350_EVAL is not set
|
||||
CONFIG_DTB_RT_NONE=y
|
||||
CONFIG_DTC=y
|
||||
# CONFIG_DWC_OTG is not set
|
||||
CONFIG_EARLY_PRINTK=y
|
||||
CONFIG_GENERIC_ATOMIC64=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
|
||||
CONFIG_GENERIC_CMOS_UPDATE=y
|
||||
CONFIG_GENERIC_GPIO=y
|
||||
CONFIG_GENERIC_IO=y
|
||||
CONFIG_GENERIC_IRQ_SHOW=y
|
||||
CONFIG_GENERIC_SMP_IDLE_THREAD=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIO_DEVRES=y
|
||||
CONFIG_GPIO_RALINK=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_HARDWARE_WATCHPOINTS=y
|
||||
CONFIG_HAS_DMA=y
|
||||
CONFIG_HAS_IOMEM=y
|
||||
CONFIG_HAS_IOPORT=y
|
||||
# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
|
||||
CONFIG_HAVE_ARCH_JUMP_LABEL=y
|
||||
CONFIG_HAVE_ARCH_KGDB=y
|
||||
# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
|
||||
CONFIG_HAVE_CLK=y
|
||||
CONFIG_HAVE_C_RECORDMCOUNT=y
|
||||
CONFIG_HAVE_DEBUG_KMEMLEAK=y
|
||||
CONFIG_HAVE_DMA_API_DEBUG=y
|
||||
CONFIG_HAVE_DMA_ATTRS=y
|
||||
CONFIG_HAVE_DYNAMIC_FTRACE=y
|
||||
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
|
||||
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
|
||||
CONFIG_HAVE_FUNCTION_TRACER=y
|
||||
CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
|
||||
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
|
||||
CONFIG_HAVE_GENERIC_HARDIRQS=y
|
||||
CONFIG_HAVE_IDE=y
|
||||
CONFIG_HAVE_MACH_CLKDEV=y
|
||||
CONFIG_HAVE_MEMBLOCK=y
|
||||
CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
|
||||
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
|
||||
CONFIG_HAVE_NET_DSA=y
|
||||
CONFIG_HAVE_OPROFILE=y
|
||||
CONFIG_HAVE_PERF_EVENTS=y
|
||||
CONFIG_HW_RANDOM=m
|
||||
CONFIG_IMAGE_CMDLINE_HACK=y
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
CONFIG_IRQCHIP=y
|
||||
CONFIG_IRQ_CPU=y
|
||||
CONFIG_IRQ_DOMAIN=y
|
||||
CONFIG_IRQ_FORCED_THREADING=y
|
||||
CONFIG_IRQ_WORK=y
|
||||
CONFIG_M25PXX_USE_FAST_READ=y
|
||||
CONFIG_MDIO_BOARDINFO=y
|
||||
# CONFIG_MII is not set
|
||||
CONFIG_MIPS=y
|
||||
# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
|
||||
CONFIG_MIPS_L1_CACHE_SHIFT=5
|
||||
# CONFIG_MIPS_MACHINE is not set
|
||||
CONFIG_MIPS_MT_DISABLED=y
|
||||
CONFIG_MODULES_USE_ELF_REL=y
|
||||
# CONFIG_MTD_CFI_INTELEXT is not set
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_M25P80=y
|
||||
CONFIG_MTD_OF_PARTS=y
|
||||
CONFIG_MTD_PHYSMAP=y
|
||||
CONFIG_MTD_PHYSMAP_OF=y
|
||||
CONFIG_MTD_UIMAGE_SPLIT=y
|
||||
CONFIG_NEED_DMA_MAP_STATE=y
|
||||
CONFIG_NEED_PER_CPU_KM=y
|
||||
CONFIG_NET_RALINK=y
|
||||
CONFIG_NET_RALINK_ESW_RT3052=y
|
||||
CONFIG_OF=y
|
||||
CONFIG_OF_ADDRESS=y
|
||||
CONFIG_OF_DEVICE=y
|
||||
# CONFIG_OF_DISPLAY_TIMING is not set
|
||||
CONFIG_OF_EARLY_FLATTREE=y
|
||||
CONFIG_OF_FLATTREE=y
|
||||
CONFIG_OF_GPIO=y
|
||||
CONFIG_OF_IRQ=y
|
||||
CONFIG_OF_MDIO=y
|
||||
CONFIG_OF_MTD=y
|
||||
CONFIG_OF_NET=y
|
||||
# CONFIG_OF_VIDEOMODE is not set
|
||||
CONFIG_PAGEFLAGS_EXTENDED=y
|
||||
CONFIG_PERF_USE_VMALLOC=y
|
||||
CONFIG_PHYLIB=y
|
||||
# CONFIG_PREEMPT_RCU is not set
|
||||
CONFIG_RALINK=y
|
||||
# CONFIG_RALINK_ILL_ACC is not set
|
||||
CONFIG_RALINK_USBPHY=y
|
||||
CONFIG_RALINK_WDT=y
|
||||
# CONFIG_RCU_STALL_COMMON is not set
|
||||
CONFIG_RESET_CONTROLLER=y
|
||||
# CONFIG_SCSI_DMA is not set
|
||||
CONFIG_SERIAL_8250_NR_UARTS=4
|
||||
CONFIG_SERIAL_8250_RT288X=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
# CONFIG_SLAB is not set
|
||||
CONFIG_SLUB=y
|
||||
# CONFIG_SOC_MT7620 is not set
|
||||
# CONFIG_SOC_RT288X is not set
|
||||
CONFIG_SOC_RT305X=y
|
||||
# CONFIG_SOC_RT3883 is not set
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_MASTER=y
|
||||
CONFIG_SPI_RALINK=y
|
||||
CONFIG_SWCONFIG=y
|
||||
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
|
||||
CONFIG_SYS_HAS_CPU_MIPS32_R2=y
|
||||
CONFIG_SYS_HAS_EARLY_PRINTK=y
|
||||
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
|
||||
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
|
||||
CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
|
||||
CONFIG_TICK_CPU_ACCOUNTING=y
|
||||
CONFIG_UIDGID_CONVERTED=y
|
||||
# CONFIG_USB_ARCH_HAS_XHCI is not set
|
||||
CONFIG_USB_OTG_UTILS=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_USE_OF=y
|
||||
CONFIG_WATCHDOG_CORE=y
|
||||
CONFIG_ZONE_DMA_FLAG=0
|
||||
@ -1,166 +0,0 @@
|
||||
CONFIG_AR8216_PHY=y
|
||||
CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
|
||||
CONFIG_ARCH_DISCARD_MEMBLOCK=y
|
||||
CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
|
||||
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
|
||||
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
|
||||
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
|
||||
CONFIG_ARCH_REQUIRE_GPIOLIB=y
|
||||
CONFIG_ARCH_SUSPEND_POSSIBLE=y
|
||||
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
CONFIG_CEVT_R4K=y
|
||||
CONFIG_CLKDEV_LOOKUP=y
|
||||
CONFIG_CLONE_BACKWARDS=y
|
||||
CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
|
||||
CONFIG_CMDLINE_BOOL=y
|
||||
# CONFIG_CMDLINE_OVERRIDE is not set
|
||||
CONFIG_CPU_GENERIC_DUMP_TLB=y
|
||||
CONFIG_CPU_HAS_PREFETCH=y
|
||||
CONFIG_CPU_HAS_SYNC=y
|
||||
CONFIG_CPU_LITTLE_ENDIAN=y
|
||||
CONFIG_CPU_MIPS32=y
|
||||
# CONFIG_CPU_MIPS32_R1 is not set
|
||||
CONFIG_CPU_MIPS32_R2=y
|
||||
CONFIG_CPU_MIPSR2=y
|
||||
CONFIG_CPU_R4K_CACHE_TLB=y
|
||||
CONFIG_CPU_R4K_FPU=y
|
||||
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
|
||||
CONFIG_CPU_SUPPORTS_HIGHMEM=y
|
||||
CONFIG_CSRC_R4K=y
|
||||
CONFIG_DECOMPRESS_LZMA=y
|
||||
CONFIG_DMA_NONCOHERENT=y
|
||||
# CONFIG_DTB_RT3883_EVAL is not set
|
||||
CONFIG_DTB_RT_NONE=y
|
||||
CONFIG_DTC=y
|
||||
CONFIG_EARLY_PRINTK=y
|
||||
CONFIG_ETHERNET_PACKET_MANGLE=y
|
||||
CONFIG_GENERIC_ATOMIC64=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
|
||||
CONFIG_GENERIC_CMOS_UPDATE=y
|
||||
CONFIG_GENERIC_GPIO=y
|
||||
CONFIG_GENERIC_IO=y
|
||||
CONFIG_GENERIC_IRQ_SHOW=y
|
||||
CONFIG_GENERIC_PCI_IOMAP=y
|
||||
CONFIG_GENERIC_SMP_IDLE_THREAD=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIO_DEVRES=y
|
||||
CONFIG_GPIO_RALINK=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_HARDWARE_WATCHPOINTS=y
|
||||
CONFIG_HAS_DMA=y
|
||||
CONFIG_HAS_IOMEM=y
|
||||
CONFIG_HAS_IOPORT=y
|
||||
# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
|
||||
CONFIG_HAVE_ARCH_JUMP_LABEL=y
|
||||
CONFIG_HAVE_ARCH_KGDB=y
|
||||
# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
|
||||
CONFIG_HAVE_CLK=y
|
||||
CONFIG_HAVE_C_RECORDMCOUNT=y
|
||||
CONFIG_HAVE_DEBUG_KMEMLEAK=y
|
||||
CONFIG_HAVE_DMA_API_DEBUG=y
|
||||
CONFIG_HAVE_DMA_ATTRS=y
|
||||
CONFIG_HAVE_DYNAMIC_FTRACE=y
|
||||
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
|
||||
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
|
||||
CONFIG_HAVE_FUNCTION_TRACER=y
|
||||
CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
|
||||
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
|
||||
CONFIG_HAVE_GENERIC_HARDIRQS=y
|
||||
CONFIG_HAVE_IDE=y
|
||||
CONFIG_HAVE_MACH_CLKDEV=y
|
||||
CONFIG_HAVE_MEMBLOCK=y
|
||||
CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
|
||||
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
|
||||
CONFIG_HAVE_NET_DSA=y
|
||||
CONFIG_HAVE_OPROFILE=y
|
||||
CONFIG_HAVE_PERF_EVENTS=y
|
||||
CONFIG_HW_HAS_PCI=y
|
||||
CONFIG_HW_RANDOM=m
|
||||
CONFIG_IMAGE_CMDLINE_HACK=y
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
CONFIG_IRQCHIP=y
|
||||
CONFIG_IRQ_CPU=y
|
||||
CONFIG_IRQ_DOMAIN=y
|
||||
CONFIG_IRQ_FORCED_THREADING=y
|
||||
CONFIG_IRQ_WORK=y
|
||||
CONFIG_M25PXX_USE_FAST_READ=y
|
||||
CONFIG_MDIO_BOARDINFO=y
|
||||
# CONFIG_MII is not set
|
||||
CONFIG_MIPS=y
|
||||
# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
|
||||
CONFIG_MIPS_L1_CACHE_SHIFT=5
|
||||
# CONFIG_MIPS_MACHINE is not set
|
||||
CONFIG_MIPS_MT_DISABLED=y
|
||||
CONFIG_MODULES_USE_ELF_REL=y
|
||||
# CONFIG_MTD_CFI_INTELEXT is not set
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_M25P80=y
|
||||
CONFIG_MTD_OF_PARTS=y
|
||||
CONFIG_MTD_PHYSMAP=y
|
||||
CONFIG_MTD_PHYSMAP_OF=y
|
||||
CONFIG_MTD_UIMAGE_SPLIT=y
|
||||
CONFIG_NEED_DMA_MAP_STATE=y
|
||||
CONFIG_NEED_PER_CPU_KM=y
|
||||
CONFIG_NET_RALINK=y
|
||||
CONFIG_NET_RALINK_MDIO=y
|
||||
CONFIG_NET_RALINK_MDIO_RT2880=y
|
||||
CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
|
||||
CONFIG_OF=y
|
||||
CONFIG_OF_ADDRESS=y
|
||||
CONFIG_OF_DEVICE=y
|
||||
# CONFIG_OF_DISPLAY_TIMING is not set
|
||||
CONFIG_OF_EARLY_FLATTREE=y
|
||||
CONFIG_OF_FLATTREE=y
|
||||
CONFIG_OF_GPIO=y
|
||||
CONFIG_OF_IRQ=y
|
||||
CONFIG_OF_MDIO=y
|
||||
CONFIG_OF_MTD=y
|
||||
CONFIG_OF_NET=y
|
||||
CONFIG_OF_PCI=y
|
||||
CONFIG_OF_PCI_IRQ=y
|
||||
# CONFIG_OF_VIDEOMODE is not set
|
||||
CONFIG_PAGEFLAGS_EXTENDED=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCI_DOMAINS=y
|
||||
CONFIG_PERF_USE_VMALLOC=y
|
||||
CONFIG_PHYLIB=y
|
||||
# CONFIG_PREEMPT_RCU is not set
|
||||
CONFIG_RALINK=y
|
||||
# CONFIG_RALINK_ILL_ACC is not set
|
||||
CONFIG_RALINK_USBPHY=y
|
||||
CONFIG_RALINK_WDT=y
|
||||
# CONFIG_RCU_STALL_COMMON is not set
|
||||
CONFIG_RESET_CONTROLLER=y
|
||||
CONFIG_RTL8366_SMI=y
|
||||
CONFIG_RTL8367B_PHY=y
|
||||
CONFIG_RTL8367_PHY=y
|
||||
# CONFIG_SCSI_DMA is not set
|
||||
CONFIG_SERIAL_8250_NR_UARTS=4
|
||||
CONFIG_SERIAL_8250_RT288X=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
# CONFIG_SLAB is not set
|
||||
CONFIG_SLUB=y
|
||||
# CONFIG_SOC_MT7620 is not set
|
||||
# CONFIG_SOC_RT288X is not set
|
||||
# CONFIG_SOC_RT305X is not set
|
||||
CONFIG_SOC_RT3883=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_MASTER=y
|
||||
CONFIG_SPI_RALINK=y
|
||||
CONFIG_SWCONFIG=y
|
||||
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
|
||||
CONFIG_SYS_HAS_CPU_MIPS32_R2=y
|
||||
CONFIG_SYS_HAS_EARLY_PRINTK=y
|
||||
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
|
||||
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
|
||||
CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
|
||||
CONFIG_TICK_CPU_ACCOUNTING=y
|
||||
CONFIG_UIDGID_CONVERTED=y
|
||||
CONFIG_USB_ARCH_HAS_XHCI=y
|
||||
CONFIG_USB_OTG_UTILS=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_USE_OF=y
|
||||
CONFIG_WATCHDOG_CORE=y
|
||||
CONFIG_ZONE_DMA_FLAG=0
|
||||
Loading…
Reference in New Issue