bcm63xx: update patches to latest upstream versions
SVN-Revision: 32591v19.07.3_mercusys_ac12_duma
Jonas Gorski
12 years ago
parent
1e2262df76
commit
988147111c
@ -1,12 +1,17 @@
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From 69b21096e25889d7db7cfc159202ef0a16530e6b Mon Sep 17 00:00:00 2001
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From 0fec0136456ce214ea4df6b8ff3b3728befc816a Mon Sep 17 00:00:00 2001
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From: Florian Fainelli <florian@openwrt.org>
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Date: Wed, 25 Jan 2012 17:39:54 +0100
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Subject: [PATCH 15/63] MIPS: BCM63XX: add support for "ipsec" clock
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Date: Tue, 31 Jan 2012 15:12:22 +0100
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Subject: [PATCH 3/6] MIPS: BCM63XX: add support for "ipsec" clock
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This module is only available on BCM6368 so far and does not require
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resetting the block.
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Signed-off-by: Florian Fainelli <florian@openwrt.org>
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Cc: linux-mips@linux-mips.org
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Cc: mpm@selenic.com
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Cc: herbert@gondor.apana.org.au
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Patchwork: https://patchwork.linux-mips.org/patch/3324/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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arch/mips/bcm63xx/clk.c | 14 ++++++++++++++
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1 files changed, 14 insertions(+), 0 deletions(-)
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@ -0,0 +1,71 @@
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From 79fed26f65c22e0d67c9523f7a374f0585bd2803 Mon Sep 17 00:00:00 2001
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From: Florian Fainelli <florian@openwrt.org>
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Date: Tue, 31 Jan 2012 15:12:24 +0100
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Subject: [PATCH 5/6] MIPS: BCM63XX: add RNG driver platform_device stub
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Signed-off-by: Florian Fainelli <florian@openwrt.org>
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Cc: linux-mips@linux-mips.org
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Cc: mpm@selenic.com
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Cc: herbert@gondor.apana.org.au
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Patchwork: https://patchwork.linux-mips.org/patch/3325/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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arch/mips/bcm63xx/Makefile | 4 ++--
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arch/mips/bcm63xx/dev-rng.c | 40 ++++++++++++++++++++++++++++++++++++++++
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2 files changed, 42 insertions(+), 2 deletions(-)
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create mode 100644 arch/mips/bcm63xx/dev-rng.c
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--- a/arch/mips/bcm63xx/Makefile
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+++ b/arch/mips/bcm63xx/Makefile
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@@ -1,6 +1,6 @@
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obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
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- dev-dsp.o dev-enet.o dev-pcmcia.o dev-spi.o dev-uart.o \
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- dev-wdt.o
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+ dev-dsp.o dev-enet.o dev-pcmcia.o dev-rng.o dev-spi.o \
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+ dev-uart.o dev-wdt.o
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obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
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obj-y += boards/
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--- /dev/null
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+++ b/arch/mips/bcm63xx/dev-rng.c
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@@ -0,0 +1,40 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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+ * for more details.
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+ *
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+ * Copyright (C) 2011 Florian Fainelli <florian@openwrt.org>
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+ */
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+
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+#include <linux/init.h>
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+#include <linux/kernel.h>
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+#include <linux/platform_device.h>
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+#include <bcm63xx_cpu.h>
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+
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+static struct resource rng_resources[] = {
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+ {
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+ .start = -1, /* filled at runtime */
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+ .end = -1, /* filled at runtime */
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+ .flags = IORESOURCE_MEM,
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+ },
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+};
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+
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+static struct platform_device bcm63xx_rng_device = {
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+ .name = "bcm63xx-rng",
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+ .id = -1,
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+ .num_resources = ARRAY_SIZE(rng_resources),
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+ .resource = rng_resources,
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+};
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+
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+int __init bcm63xx_rng_register(void)
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+{
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+ if (!BCMCPU_IS_6368())
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+ return -ENODEV;
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+
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+ rng_resources[0].start = bcm63xx_regset_address(RSET_RNG);
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+ rng_resources[0].end = rng_resources[0].start;
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+ rng_resources[0].end += RSET_RNG_SIZE - 1;
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+
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+ return platform_device_register(&bcm63xx_rng_device);
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+}
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+arch_initcall(bcm63xx_rng_register);
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@ -1,17 +1,23 @@
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From d831de57b1995eff51f43310b4bbfa85b1a3df42 Mon Sep 17 00:00:00 2001
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From a9168d99658bd050e49afc06880d140e2fc2c231 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jonas.gorski@gmail.com>
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Date: Fri, 30 Dec 2011 02:37:47 +0100
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Subject: [PATCH 38/79] MIPS: BCM63XX: use the Chip ID register for
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identifying the SoC
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Date: Tue, 12 Jun 2012 10:23:40 +0200
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Subject: [PATCH 3/8] MIPS: BCM63XX: Use the Chip ID register for identifying the SoC
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Newer BCM63XX SoCs use virtually the same cpu ID. But since they all have
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the Chip ID register at the same location, we can use that to identify
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the SoC we are running on.
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Newer BCM63XX SoCs use virtually the same CPU ID, differing only in the
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revision bits. But since they all have the Chip ID register at the same
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location, we can use that to identify the SoC we are running on.
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Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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Cc: linux-mips@linux-mips.org
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Cc: Maxime Bizon <mbizon@freebox.fr>
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Cc: Florian Fainelli <florian@openwrt.org>
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Cc: Kevin Cernekee <cernekee@gmail.com>
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Patchwork: https://patchwork.linux-mips.org/patch/3955/
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Reviewed-by: Florian Fainelli <florian@openwrt.org>
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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arch/mips/bcm63xx/cpu.c | 20 ++++++++++++--------
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1 file changed, 12 insertions(+), 8 deletions(-)
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1 files changed, 12 insertions(+), 8 deletions(-)
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--- a/arch/mips/bcm63xx/cpu.c
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+++ b/arch/mips/bcm63xx/cpu.c
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@ -0,0 +1,61 @@
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From b8420b9150fa03fcdfacd32e8c5ad286e208d5e9 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jonas.gorski@gmail.com>
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Date: Wed, 13 Jun 2012 16:48:02 +0100
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Subject: [PATCH 5/8] MIPS: BCM63XX: Move the PCI initialization into its own function
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Also make the cpu check a bit more explicit.
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Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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Cc: linux-mips@linux-mips.org
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Cc: Maxime Bizon <mbizon@freebox.fr>
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Cc: Florian Fainelli <florian@openwrt.org>
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Cc: Kevin Cernekee <cernekee@gmail.com>
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Patchwork: https://patchwork.linux-mips.org/patch/3953/
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Reviewed-by: Florian Fainelli <florian@openwrt.org>
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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arch/mips/pci/pci-bcm63xx.c | 25 +++++++++++++++++--------
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1 files changed, 17 insertions(+), 8 deletions(-)
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--- a/arch/mips/pci/pci-bcm63xx.c
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+++ b/arch/mips/pci/pci-bcm63xx.c
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@@ -94,17 +94,10 @@ static void bcm63xx_int_cfg_writel(u32 v
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void __iomem *pci_iospace_start;
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-static int __init bcm63xx_pci_init(void)
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+static int __init bcm63xx_register_pci(void)
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{
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unsigned int mem_size;
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u32 val;
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-
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- if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358() && !BCMCPU_IS_6368())
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- return -ENODEV;
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-
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- if (!bcm63xx_pci_enabled)
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- return -ENODEV;
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-
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/*
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* configuration access are done through IO space, remap 4
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* first bytes to access it from CPU.
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@@ -221,4 +214,20 @@ static int __init bcm63xx_pci_init(void)
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return 0;
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}
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+
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+static int __init bcm63xx_pci_init(void)
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+{
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+ if (!bcm63xx_pci_enabled)
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+ return -ENODEV;
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+
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+ switch (bcm63xx_get_cpu_id()) {
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+ case BCM6348_CPU_ID:
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+ case BCM6358_CPU_ID:
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+ case BCM6368_CPU_ID:
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+ return bcm63xx_register_pci();
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+ default:
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+ return -ENODEV;
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+ }
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+}
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+
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arch_initcall(bcm63xx_pci_init);
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@ -0,0 +1,427 @@
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From 45655e79f84e35c13b8964b961d804e64b3aca91 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jonas.gorski@gmail.com>
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Date: Wed, 13 Jun 2012 17:07:13 +0100
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Subject: [PATCH 6/8] MIPS: BCM63XX: Add PCIe Support for BCM6328
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Add support for the PCIe port found on BCM6328.
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Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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Cc: linux-mips@linux-mips.org
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Cc: Maxime Bizon <mbizon@freebox.fr>
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Cc: Florian Fainelli <florian@openwrt.org>
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Cc: Kevin Cernekee <cernekee@gmail.com>
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Patchwork: https://patchwork.linux-mips.org/patch/3956/
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Reviewed-by: Florian Fainelli <florian@openwrt.org>
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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arch/mips/bcm63xx/Kconfig | 1 +
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 9 ++
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 6 +
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 54 ++++++++++
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arch/mips/pci/ops-bcm63xx.c | 61 +++++++++++
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arch/mips/pci/pci-bcm63xx.c | 112 +++++++++++++++++++++
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arch/mips/pci/pci-bcm63xx.h | 5 +
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7 files changed, 248 insertions(+), 0 deletions(-)
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--- a/arch/mips/bcm63xx/Kconfig
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+++ b/arch/mips/bcm63xx/Kconfig
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@@ -3,6 +3,7 @@ menu "CPU support"
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config BCM63XX_CPU_6328
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bool "support 6328 CPU"
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+ select HW_HAS_PCI
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config BCM63XX_CPU_6338
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bool "support 6338 CPU"
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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@@ -122,6 +122,7 @@ enum bcm63xx_regs_set {
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RSET_USBH_PRIV,
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RSET_MPI,
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RSET_PCMCIA,
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+ RSET_PCIE,
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RSET_DSL,
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RSET_ENET0,
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RSET_ENET1,
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@@ -188,6 +189,7 @@ enum bcm63xx_regs_set {
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#define BCM_6328_USBH_PRIV_BASE (0xdeadbeef)
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#define BCM_6328_MPI_BASE (0xdeadbeef)
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#define BCM_6328_PCMCIA_BASE (0xdeadbeef)
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+#define BCM_6328_PCIE_BASE (0xb0e40000)
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#define BCM_6328_SDRAM_REGS_BASE (0xdeadbeef)
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#define BCM_6328_DSL_BASE (0xb0001900)
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#define BCM_6328_UBUS_BASE (0xdeadbeef)
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@@ -232,6 +234,7 @@ enum bcm63xx_regs_set {
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#define BCM_6338_USBH_PRIV_BASE (0xdeadbeef)
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#define BCM_6338_MPI_BASE (0xfffe3160)
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#define BCM_6338_PCMCIA_BASE (0xdeadbeef)
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+#define BCM_6338_PCIE_BASE (0xdeadbeef)
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#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)
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#define BCM_6338_DSL_BASE (0xfffe1000)
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#define BCM_6338_UBUS_BASE (0xdeadbeef)
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@@ -279,6 +282,7 @@ enum bcm63xx_regs_set {
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#define BCM_6345_ENETSW_BASE (0xdeadbeef)
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#define BCM_6345_PCMCIA_BASE (0xfffe2028)
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#define BCM_6345_MPI_BASE (0xfffe2000)
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+#define BCM_6345_PCIE_BASE (0xdeadbeef)
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#define BCM_6345_OHCI0_BASE (0xfffe2100)
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#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
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#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
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@@ -320,6 +324,7 @@ enum bcm63xx_regs_set {
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#define BCM_6348_USBH_PRIV_BASE (0xdeadbeef)
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#define BCM_6348_MPI_BASE (0xfffe2000)
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#define BCM_6348_PCMCIA_BASE (0xfffe2054)
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+#define BCM_6348_PCIE_BASE (0xdeadbeef)
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#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
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#define BCM_6348_M2M_BASE (0xfffe2800)
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#define BCM_6348_DSL_BASE (0xfffe3000)
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@@ -362,6 +367,7 @@ enum bcm63xx_regs_set {
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#define BCM_6358_USBH_PRIV_BASE (0xfffe1500)
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#define BCM_6358_MPI_BASE (0xfffe1000)
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#define BCM_6358_PCMCIA_BASE (0xfffe1054)
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+#define BCM_6358_PCIE_BASE (0xdeadbeef)
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#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
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#define BCM_6358_M2M_BASE (0xdeadbeef)
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#define BCM_6358_DSL_BASE (0xfffe3000)
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@@ -405,6 +411,7 @@ enum bcm63xx_regs_set {
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#define BCM_6368_USBH_PRIV_BASE (0xb0001700)
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#define BCM_6368_MPI_BASE (0xb0001000)
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#define BCM_6368_PCMCIA_BASE (0xb0001054)
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+#define BCM_6368_PCIE_BASE (0xdeadbeef)
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#define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef)
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#define BCM_6368_M2M_BASE (0xdeadbeef)
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#define BCM_6368_DSL_BASE (0xdeadbeef)
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@@ -453,6 +460,7 @@ extern const unsigned long *bcm63xx_regs
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__GEN_RSET_BASE(__cpu, USBH_PRIV) \
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__GEN_RSET_BASE(__cpu, MPI) \
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__GEN_RSET_BASE(__cpu, PCMCIA) \
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+ __GEN_RSET_BASE(__cpu, PCIE) \
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__GEN_RSET_BASE(__cpu, DSL) \
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__GEN_RSET_BASE(__cpu, ENET0) \
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__GEN_RSET_BASE(__cpu, ENET1) \
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@@ -493,6 +501,7 @@ extern const unsigned long *bcm63xx_regs
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[RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \
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[RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \
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[RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \
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+ [RSET_PCIE] = BCM_## __cpu ##_PCIE_BASE, \
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[RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \
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[RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \
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[RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
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@@ -40,6 +40,10 @@
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#define BCM_CB_MEM_END_PA (BCM_CB_MEM_BASE_PA + \
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BCM_CB_MEM_SIZE - 1)
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+#define BCM_PCIE_MEM_BASE_PA 0x10f00000
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+#define BCM_PCIE_MEM_SIZE (16 * 1024 * 1024)
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+#define BCM_PCIE_MEM_END_PA (BCM_PCIE_MEM_BASE_PA + \
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+ BCM_PCIE_MEM_SIZE - 1)
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/*
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* Internal registers are accessed through KSEG3
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@@ -85,6 +89,8 @@
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#define bcm_mpi_writel(v, o) bcm_rset_writel(RSET_MPI, (v), (o))
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#define bcm_pcmcia_readl(o) bcm_rset_readl(RSET_PCMCIA, (o))
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#define bcm_pcmcia_writel(v, o) bcm_rset_writel(RSET_PCMCIA, (v), (o))
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+#define bcm_pcie_readl(o) bcm_rset_readl(RSET_PCIE, (o))
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+#define bcm_pcie_writel(v, o) bcm_rset_writel(RSET_PCIE, (v), (o))
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#define bcm_sdram_readl(o) bcm_rset_readl(RSET_SDRAM, (o))
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#define bcm_sdram_writel(v, o) bcm_rset_writel(RSET_SDRAM, (v), (o))
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#define bcm_memc_readl(o) bcm_rset_readl(RSET_MEMC, (o))
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -1169,6 +1169,9 @@
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/*************************************************************************
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* _REG relative to RSET_MISC
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*************************************************************************/
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+#define MISC_SERDES_CTRL_REG 0x0
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+#define SERDES_PCIE_EN (1 << 0)
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+#define SERDES_PCIE_EXD_EN (1 << 15)
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#define MISC_STRAPBUS_6328_REG 0x240
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#define STRAPBUS_6328_FCVO_SHIFT 7
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@@ -1176,4 +1179,55 @@
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#define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28)
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#define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28)
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+/*************************************************************************
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+ * _REG relative to RSET_PCIE
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+ *************************************************************************/
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+
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+#define PCIE_CONFIG2_REG 0x408
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+#define CONFIG2_BAR1_SIZE_EN 1
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+#define CONFIG2_BAR1_SIZE_MASK 0xf
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+
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+#define PCIE_IDVAL3_REG 0x43c
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+#define IDVAL3_CLASS_CODE_MASK 0xffffff
|
||||
+#define IDVAL3_SUBCLASS_SHIFT 8
|
||||
+#define IDVAL3_CLASS_SHIFT 16
|
||||
+
|
||||
+#define PCIE_DLSTATUS_REG 0x1048
|
||||
+#define DLSTATUS_PHYLINKUP (1 << 13)
|
||||
+
|
||||
+#define PCIE_BRIDGE_OPT1_REG 0x2820
|
||||
+#define OPT1_RD_BE_OPT_EN (1 << 7)
|
||||
+#define OPT1_RD_REPLY_BE_FIX_EN (1 << 9)
|
||||
+#define OPT1_PCIE_BRIDGE_HOLE_DET_EN (1 << 11)
|
||||
+#define OPT1_L1_INT_STATUS_MASK_POL (1 << 12)
|
||||
+
|
||||
+#define PCIE_BRIDGE_OPT2_REG 0x2824
|
||||
+#define OPT2_UBUS_UR_DECODE_DIS (1 << 2)
|
||||
+#define OPT2_TX_CREDIT_CHK_EN (1 << 4)
|
||||
+#define OPT2_CFG_TYPE1_BD_SEL (1 << 7)
|
||||
+#define OPT2_CFG_TYPE1_BUS_NO_SHIFT 16
|
||||
+#define OPT2_CFG_TYPE1_BUS_NO_MASK (0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT)
|
||||
+
|
||||
+#define PCIE_BRIDGE_BAR0_BASEMASK_REG 0x2828
|
||||
+#define PCIE_BRIDGE_BAR1_BASEMASK_REG 0x2830
|
||||
+#define BASEMASK_REMAP_EN (1 << 0)
|
||||
+#define BASEMASK_SWAP_EN (1 << 1)
|
||||
+#define BASEMASK_MASK_SHIFT 4
|
||||
+#define BASEMASK_MASK_MASK (0xfff << BASEMASK_MASK_SHIFT)
|
||||
+#define BASEMASK_BASE_SHIFT 20
|
||||
+#define BASEMASK_BASE_MASK (0xfff << BASEMASK_BASE_SHIFT)
|
||||
+
|
||||
+#define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c
|
||||
+#define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG 0x2834
|
||||
+#define REBASE_ADDR_BASE_SHIFT 20
|
||||
+#define REBASE_ADDR_BASE_MASK (0xfff << REBASE_ADDR_BASE_SHIFT)
|
||||
+
|
||||
+#define PCIE_BRIDGE_RC_INT_MASK_REG 0x2854
|
||||
+#define PCIE_RC_INT_A (1 << 0)
|
||||
+#define PCIE_RC_INT_B (1 << 1)
|
||||
+#define PCIE_RC_INT_C (1 << 2)
|
||||
+#define PCIE_RC_INT_D (1 << 3)
|
||||
+
|
||||
+#define PCIE_DEVICE_OFFSET 0x8000
|
||||
+
|
||||
#endif /* BCM63XX_REGS_H_ */
|
||||
--- a/arch/mips/pci/ops-bcm63xx.c
|
||||
+++ b/arch/mips/pci/ops-bcm63xx.c
|
||||
@@ -465,3 +465,64 @@ static void bcm63xx_fixup(struct pci_dev
|
||||
|
||||
DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm63xx_fixup);
|
||||
#endif
|
||||
+
|
||||
+static int bcm63xx_pcie_can_access(struct pci_bus *bus, int devfn)
|
||||
+{
|
||||
+ switch (bus->number) {
|
||||
+ case PCIE_BUS_BRIDGE:
|
||||
+ return (PCI_SLOT(devfn) == 0);
|
||||
+ case PCIE_BUS_DEVICE:
|
||||
+ if (PCI_SLOT(devfn) == 0)
|
||||
+ return bcm_pcie_readl(PCIE_DLSTATUS_REG)
|
||||
+ & DLSTATUS_PHYLINKUP;
|
||||
+ default:
|
||||
+ return false;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static int bcm63xx_pcie_read(struct pci_bus *bus, unsigned int devfn,
|
||||
+ int where, int size, u32 *val)
|
||||
+{
|
||||
+ u32 data;
|
||||
+ u32 reg = where & ~3;
|
||||
+
|
||||
+ if (!bcm63xx_pcie_can_access(bus, devfn))
|
||||
+ return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
+
|
||||
+ if (bus->number == PCIE_BUS_DEVICE)
|
||||
+ reg += PCIE_DEVICE_OFFSET;
|
||||
+
|
||||
+ data = bcm_pcie_readl(reg);
|
||||
+
|
||||
+ *val = postprocess_read(data, where, size);
|
||||
+
|
||||
+ return PCIBIOS_SUCCESSFUL;
|
||||
+
|
||||
+}
|
||||
+
|
||||
+static int bcm63xx_pcie_write(struct pci_bus *bus, unsigned int devfn,
|
||||
+ int where, int size, u32 val)
|
||||
+{
|
||||
+ u32 data;
|
||||
+ u32 reg = where & ~3;
|
||||
+
|
||||
+ if (!bcm63xx_pcie_can_access(bus, devfn))
|
||||
+ return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
+
|
||||
+ if (bus->number == PCIE_BUS_DEVICE)
|
||||
+ reg += PCIE_DEVICE_OFFSET;
|
||||
+
|
||||
+
|
||||
+ data = bcm_pcie_readl(reg);
|
||||
+
|
||||
+ data = preprocess_write(data, val, where, size);
|
||||
+ bcm_pcie_writel(data, reg);
|
||||
+
|
||||
+ return PCIBIOS_SUCCESSFUL;
|
||||
+}
|
||||
+
|
||||
+
|
||||
+struct pci_ops bcm63xx_pcie_ops = {
|
||||
+ .read = bcm63xx_pcie_read,
|
||||
+ .write = bcm63xx_pcie_write
|
||||
+};
|
||||
--- a/arch/mips/pci/pci-bcm63xx.c
|
||||
+++ b/arch/mips/pci/pci-bcm63xx.c
|
||||
@@ -10,6 +10,7 @@
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
+#include <linux/delay.h>
|
||||
#include <asm/bootinfo.h>
|
||||
|
||||
#include "pci-bcm63xx.h"
|
||||
@@ -71,6 +72,26 @@ struct pci_controller bcm63xx_cb_control
|
||||
};
|
||||
#endif
|
||||
|
||||
+static struct resource bcm_pcie_mem_resource = {
|
||||
+ .name = "bcm63xx PCIe memory space",
|
||||
+ .start = BCM_PCIE_MEM_BASE_PA,
|
||||
+ .end = BCM_PCIE_MEM_END_PA,
|
||||
+ .flags = IORESOURCE_MEM,
|
||||
+};
|
||||
+
|
||||
+static struct resource bcm_pcie_io_resource = {
|
||||
+ .name = "bcm63xx PCIe IO space",
|
||||
+ .start = 0,
|
||||
+ .end = 0,
|
||||
+ .flags = 0,
|
||||
+};
|
||||
+
|
||||
+struct pci_controller bcm63xx_pcie_controller = {
|
||||
+ .pci_ops = &bcm63xx_pcie_ops,
|
||||
+ .io_resource = &bcm_pcie_io_resource,
|
||||
+ .mem_resource = &bcm_pcie_mem_resource,
|
||||
+};
|
||||
+
|
||||
static u32 bcm63xx_int_cfg_readl(u32 reg)
|
||||
{
|
||||
u32 tmp;
|
||||
@@ -94,6 +115,95 @@ static void bcm63xx_int_cfg_writel(u32 v
|
||||
|
||||
void __iomem *pci_iospace_start;
|
||||
|
||||
+static void __init bcm63xx_reset_pcie(void)
|
||||
+{
|
||||
+ u32 val;
|
||||
+
|
||||
+ /* enable clock */
|
||||
+ val = bcm_perf_readl(PERF_CKCTL_REG);
|
||||
+ val |= CKCTL_6328_PCIE_EN;
|
||||
+ bcm_perf_writel(val, PERF_CKCTL_REG);
|
||||
+
|
||||
+ /* enable SERDES */
|
||||
+ val = bcm_misc_readl(MISC_SERDES_CTRL_REG);
|
||||
+ val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN;
|
||||
+ bcm_misc_writel(val, MISC_SERDES_CTRL_REG);
|
||||
+
|
||||
+ /* reset the PCIe core */
|
||||
+ val = bcm_perf_readl(PERF_SOFTRESET_6328_REG);
|
||||
+
|
||||
+ val &= ~SOFTRESET_6328_PCIE_MASK;
|
||||
+ val &= ~SOFTRESET_6328_PCIE_CORE_MASK;
|
||||
+ val &= ~SOFTRESET_6328_PCIE_HARD_MASK;
|
||||
+ val &= ~SOFTRESET_6328_PCIE_EXT_MASK;
|
||||
+ bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
|
||||
+ mdelay(10);
|
||||
+
|
||||
+ val |= SOFTRESET_6328_PCIE_MASK;
|
||||
+ val |= SOFTRESET_6328_PCIE_CORE_MASK;
|
||||
+ val |= SOFTRESET_6328_PCIE_HARD_MASK;
|
||||
+ bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
|
||||
+ mdelay(10);
|
||||
+
|
||||
+ val |= SOFTRESET_6328_PCIE_EXT_MASK;
|
||||
+ bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
|
||||
+ mdelay(200);
|
||||
+}
|
||||
+
|
||||
+static int __init bcm63xx_register_pcie(void)
|
||||
+{
|
||||
+ u32 val;
|
||||
+
|
||||
+ bcm63xx_reset_pcie();
|
||||
+
|
||||
+ /* configure the PCIe bridge */
|
||||
+ val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG);
|
||||
+ val |= OPT1_RD_BE_OPT_EN;
|
||||
+ val |= OPT1_RD_REPLY_BE_FIX_EN;
|
||||
+ val |= OPT1_PCIE_BRIDGE_HOLE_DET_EN;
|
||||
+ val |= OPT1_L1_INT_STATUS_MASK_POL;
|
||||
+ bcm_pcie_writel(val, PCIE_BRIDGE_OPT1_REG);
|
||||
+
|
||||
+ /* setup the interrupts */
|
||||
+ val = bcm_pcie_readl(PCIE_BRIDGE_RC_INT_MASK_REG);
|
||||
+ val |= PCIE_RC_INT_A | PCIE_RC_INT_B | PCIE_RC_INT_C | PCIE_RC_INT_D;
|
||||
+ bcm_pcie_writel(val, PCIE_BRIDGE_RC_INT_MASK_REG);
|
||||
+
|
||||
+ val = bcm_pcie_readl(PCIE_BRIDGE_OPT2_REG);
|
||||
+ /* enable credit checking and error checking */
|
||||
+ val |= OPT2_TX_CREDIT_CHK_EN;
|
||||
+ val |= OPT2_UBUS_UR_DECODE_DIS;
|
||||
+
|
||||
+ /* set device bus/func for the pcie device */
|
||||
+ val |= (PCIE_BUS_DEVICE << OPT2_CFG_TYPE1_BUS_NO_SHIFT);
|
||||
+ val |= OPT2_CFG_TYPE1_BD_SEL;
|
||||
+ bcm_pcie_writel(val, PCIE_BRIDGE_OPT2_REG);
|
||||
+
|
||||
+ /* setup class code as bridge */
|
||||
+ val = bcm_pcie_readl(PCIE_IDVAL3_REG);
|
||||
+ val &= ~IDVAL3_CLASS_CODE_MASK;
|
||||
+ val |= (PCI_CLASS_BRIDGE_PCI << IDVAL3_SUBCLASS_SHIFT);
|
||||
+ bcm_pcie_writel(val, PCIE_IDVAL3_REG);
|
||||
+
|
||||
+ /* disable bar1 size */
|
||||
+ val = bcm_pcie_readl(PCIE_CONFIG2_REG);
|
||||
+ val &= ~CONFIG2_BAR1_SIZE_MASK;
|
||||
+ bcm_pcie_writel(val, PCIE_CONFIG2_REG);
|
||||
+
|
||||
+ /* set bar0 to little endian */
|
||||
+ val = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT;
|
||||
+ val |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT;
|
||||
+ val |= BASEMASK_REMAP_EN;
|
||||
+ bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG);
|
||||
+
|
||||
+ val = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT;
|
||||
+ bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);
|
||||
+
|
||||
+ register_pci_controller(&bcm63xx_pcie_controller);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static int __init bcm63xx_register_pci(void)
|
||||
{
|
||||
unsigned int mem_size;
|
||||
@@ -221,6 +331,8 @@ static int __init bcm63xx_pci_init(void)
|
||||
return -ENODEV;
|
||||
|
||||
switch (bcm63xx_get_cpu_id()) {
|
||||
+ case BCM6328_CPU_ID:
|
||||
+ return bcm63xx_register_pcie();
|
||||
case BCM6348_CPU_ID:
|
||||
case BCM6358_CPU_ID:
|
||||
case BCM6368_CPU_ID:
|
||||
--- a/arch/mips/pci/pci-bcm63xx.h
|
||||
+++ b/arch/mips/pci/pci-bcm63xx.h
|
||||
@@ -13,11 +13,16 @@
|
||||
*/
|
||||
#define CARDBUS_PCI_IDSEL 0x8
|
||||
|
||||
+
|
||||
+#define PCIE_BUS_BRIDGE 0
|
||||
+#define PCIE_BUS_DEVICE 1
|
||||
+
|
||||
/*
|
||||
* defined in ops-bcm63xx.c
|
||||
*/
|
||||
extern struct pci_ops bcm63xx_pci_ops;
|
||||
extern struct pci_ops bcm63xx_cb_ops;
|
||||
+extern struct pci_ops bcm63xx_pcie_ops;
|
||||
|
||||
/*
|
||||
* defined in pci-bcm63xx.c
|
||||
@ -0,0 +1,28 @@
|
||||
From 4831929b8c37aa866afca1498001c939377e5a67 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Gorski <jonas.gorski@gmail.com>
|
||||
Date: Wed, 13 Jun 2012 17:07:16 +0100
|
||||
Subject: [PATCH 7/8] MIPS: Expose PCIe drivers for MIPS
|
||||
|
||||
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
|
||||
Cc: linux-mips@linux-mips.org
|
||||
Cc: Maxime Bizon <mbizon@freebox.fr>
|
||||
Cc: Florian Fainelli <florian@openwrt.org>
|
||||
Cc: Kevin Cernekee <cernekee@gmail.com>
|
||||
Patchwork: https://patchwork.linux-mips.org/patch/3957/
|
||||
Reviewed-by: Florian Fainelli <florian@openwrt.org>
|
||||
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
||||
---
|
||||
arch/mips/Kconfig | 2 ++
|
||||
1 files changed, 2 insertions(+), 0 deletions(-)
|
||||
|
||||
--- a/arch/mips/Kconfig
|
||||
+++ b/arch/mips/Kconfig
|
||||
@@ -2392,6 +2392,8 @@ config PCI_DOMAINS
|
||||
|
||||
source "drivers/pci/Kconfig"
|
||||
|
||||
+source "drivers/pci/pcie/Kconfig"
|
||||
+
|
||||
#
|
||||
# ISA support is now enabled via select. Too many systems still have the one
|
||||
# or other ISA chip on the board that users don't know about so don't expect
|
||||
@ -1,66 +0,0 @@
|
||||
From cfcc8526e97bdcbfcbf945246b878262389b8842 Mon Sep 17 00:00:00 2001
|
||||
From: Florian Fainelli <florian@openwrt.org>
|
||||
Date: Wed, 25 Jan 2012 17:39:59 +0100
|
||||
Subject: [PATCH 17/63] MIPS: BCM63XX: add RNG driver platform_device stub
|
||||
|
||||
Signed-off-by: Florian Fainelli <florian@openwrt.org>
|
||||
---
|
||||
arch/mips/bcm63xx/Makefile | 4 ++--
|
||||
arch/mips/bcm63xx/dev-trng.c | 40 ++++++++++++++++++++++++++++++++++++++++
|
||||
2 files changed, 42 insertions(+), 2 deletions(-)
|
||||
create mode 100644 arch/mips/bcm63xx/dev-trng.c
|
||||
|
||||
--- a/arch/mips/bcm63xx/Makefile
|
||||
+++ b/arch/mips/bcm63xx/Makefile
|
||||
@@ -1,6 +1,6 @@
|
||||
obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
|
||||
- dev-dsp.o dev-enet.o dev-pcmcia.o dev-spi.o dev-uart.o \
|
||||
- dev-wdt.o
|
||||
+ dev-dsp.o dev-enet.o dev-pcmcia.o dev-spi.o dev-trng.o \
|
||||
+ dev-uart.o dev-wdt.o
|
||||
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
|
||||
|
||||
obj-y += boards/
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/bcm63xx/dev-trng.c
|
||||
@@ -0,0 +1,40 @@
|
||||
+/*
|
||||
+ * This file is subject to the terms and conditions of the GNU General Public
|
||||
+ * License. See the file "COPYING" in the main directory of this archive
|
||||
+ * for more details.
|
||||
+ *
|
||||
+ * Copyright (C) 2011 Florian Fainelli <florian@openwrt.org>
|
||||
+ */
|
||||
+
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <bcm63xx_cpu.h>
|
||||
+
|
||||
+static struct resource trng_resources[] = {
|
||||
+ {
|
||||
+ .start = -1, /* filled at runtime */
|
||||
+ .end = -1, /* filled at runtime */
|
||||
+ .flags = IORESOURCE_MEM,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static struct platform_device bcm63xx_trng_device = {
|
||||
+ .name = "bcm63xx-trng",
|
||||
+ .id = -1,
|
||||
+ .num_resources = ARRAY_SIZE(trng_resources),
|
||||
+ .resource = trng_resources,
|
||||
+};
|
||||
+
|
||||
+int __init bcm63xx_trng_register(void)
|
||||
+{
|
||||
+ if (!BCMCPU_IS_6368())
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ trng_resources[0].start = bcm63xx_regset_address(RSET_TRNG);
|
||||
+ trng_resources[0].end = trng_resources[0].start;
|
||||
+ trng_resources[0].end += RSET_TRNG_SIZE - 1;
|
||||
+
|
||||
+ return platform_device_register(&bcm63xx_trng_device);
|
||||
+}
|
||||
+arch_initcall(bcm63xx_trng_register);
|
||||
@ -1,21 +0,0 @@
|
||||
From a3f65b46e32acd29c613b35fab588e4d28e5d432 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Gorski <jonas.gorski@gmail.com>
|
||||
Date: Sun, 3 Jul 2011 13:11:19 +0200
|
||||
Subject: [PATCH 48/79] MIPS: expose PCIe drivers for MIPS
|
||||
|
||||
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
|
||||
---
|
||||
arch/mips/Kconfig | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/arch/mips/Kconfig
|
||||
+++ b/arch/mips/Kconfig
|
||||
@@ -2392,6 +2392,8 @@ config PCI_DOMAINS
|
||||
|
||||
source "drivers/pci/Kconfig"
|
||||
|
||||
+source "drivers/pci/pcie/Kconfig"
|
||||
+
|
||||
#
|
||||
# ISA support is now enabled via select. Too many systems still have the one
|
||||
# or other ISA chip on the board that users don't know about so don't expect
|
||||
@ -1,21 +0,0 @@
|
||||
From d42f3f75a5d1abe9f7c5275fb59f3e894e83043d Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Gorski <jonas.gorski@gmail.com>
|
||||
Date: Sun, 6 May 2012 15:05:48 +0200
|
||||
Subject: [PATCH 1/2] MIPS: BCM63XX: register devices earlier
|
||||
|
||||
Register devices as an arch initcall so that the fallback sprom gets
|
||||
installed in the same phase as the pci bus gets registered.
|
||||
|
||||
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
|
||||
---
|
||||
arch/mips/bcm63xx/setup.c | 2 +-
|
||||
1 files changed, 1 insertions(+), 1 deletions(-)
|
||||
|
||||
--- a/arch/mips/bcm63xx/setup.c
|
||||
+++ b/arch/mips/bcm63xx/setup.c
|
||||
@@ -150,4 +150,4 @@ int __init bcm63xx_register_devices(void
|
||||
return board_register_devices();
|
||||
}
|
||||
|
||||
-device_initcall(bcm63xx_register_devices);
|
||||
+arch_initcall(bcm63xx_register_devices);
|
||||
@ -0,0 +1,23 @@
|
||||
From a7d2622b6614fdca504c074a0cd307d5a1165c30 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Gorski <jonas.gorski@gmail.com>
|
||||
Date: Tue, 8 May 2012 09:39:01 +0200
|
||||
Subject: [PATCH 04/59] Revert "MIPS: BCM63XX: Call board_register_device from device_initcall()"
|
||||
|
||||
This commit causes a race between PCI scan and SSB fallback SPROM handler
|
||||
registration, causing the wifi to not work on slower systems. The only
|
||||
subsystem touched from board_register_device is platform device
|
||||
registration, which should be safe as an arch init call.
|
||||
|
||||
This reverts commit d64ed7ada2f689d2c62af1892ca55e47d3653e36.
|
||||
---
|
||||
arch/mips/bcm63xx/setup.c | 2 +-
|
||||
1 files changed, 1 insertions(+), 1 deletions(-)
|
||||
|
||||
--- a/arch/mips/bcm63xx/setup.c
|
||||
+++ b/arch/mips/bcm63xx/setup.c
|
||||
@@ -157,4 +157,4 @@ int __init bcm63xx_register_devices(void
|
||||
return board_register_devices();
|
||||
}
|
||||
|
||||
-device_initcall(bcm63xx_register_devices);
|
||||
+arch_initcall(bcm63xx_register_devices);
|
||||
@ -1,89 +0,0 @@
|
||||
From 45aebb9465e22b236a201deef1b234693d99e174 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Gorski <jonas.gorski@gmail.com>
|
||||
Date: Sun, 6 May 2012 15:13:48 +0200
|
||||
Subject: [PATCH 2/2] MIPS: BCM63XX: explicitly register the PCI bus
|
||||
|
||||
Instead of setting a global variable toggling the PCI registration,
|
||||
register it in the device_register phase after setting the fallback
|
||||
sprom to ensure there cannot be a race between them.
|
||||
|
||||
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
|
||||
---
|
||||
arch/mips/bcm63xx/boards/board_bcm963xx.c | 6 +++++-
|
||||
.../include/asm/mach-bcm63xx/bcm63xx_dev_pci.h | 4 +++-
|
||||
arch/mips/pci/pci-bcm63xx.c | 13 +------------
|
||||
3 files changed, 9 insertions(+), 14 deletions(-)
|
||||
|
||||
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
|
||||
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
|
||||
@@ -826,7 +826,6 @@ void __init board_prom_init(void)
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
if (board.has_pci) {
|
||||
- bcm63xx_pci_enabled = 1;
|
||||
if (BCMCPU_IS_6348())
|
||||
val |= GPIO_MODE_6348_G2_PCI;
|
||||
}
|
||||
@@ -998,5 +997,10 @@ int __init board_register_devices(void)
|
||||
platform_device_register(&bcm63xx_gpio_keys_device);
|
||||
}
|
||||
|
||||
+#ifdef CONFIG_PCI
|
||||
+ if (board.has_pci)
|
||||
+ bcm63xx_pci_register();
|
||||
+#endif
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_pci.h
|
||||
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_pci.h
|
||||
@@ -1,6 +1,8 @@
|
||||
#ifndef BCM63XX_DEV_PCI_H_
|
||||
#define BCM63XX_DEV_PCI_H_
|
||||
|
||||
-extern int bcm63xx_pci_enabled;
|
||||
+#include <linux/init.h>
|
||||
+
|
||||
+int __init bcm63xx_pci_register(void);
|
||||
|
||||
#endif /* BCM63XX_DEV_PCI_H_ */
|
||||
--- a/arch/mips/pci/pci-bcm63xx.c
|
||||
+++ b/arch/mips/pci/pci-bcm63xx.c
|
||||
@@ -14,12 +14,6 @@
|
||||
|
||||
#include "pci-bcm63xx.h"
|
||||
|
||||
-/*
|
||||
- * Allow PCI to be disabled at runtime depending on board nvram
|
||||
- * configuration
|
||||
- */
|
||||
-int bcm63xx_pci_enabled;
|
||||
-
|
||||
static struct resource bcm_pci_mem_resource = {
|
||||
.name = "bcm63xx PCI memory space",
|
||||
.start = BCM_PCI_MEM_BASE_PA,
|
||||
@@ -94,7 +88,7 @@ static void bcm63xx_int_cfg_writel(u32 v
|
||||
|
||||
void __iomem *pci_iospace_start;
|
||||
|
||||
-static int __init bcm63xx_pci_init(void)
|
||||
+int __init bcm63xx_pci_register(void)
|
||||
{
|
||||
unsigned int mem_size;
|
||||
u32 val;
|
||||
@@ -102,9 +96,6 @@ static int __init bcm63xx_pci_init(void)
|
||||
if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358() && !BCMCPU_IS_6368())
|
||||
return -ENODEV;
|
||||
|
||||
- if (!bcm63xx_pci_enabled)
|
||||
- return -ENODEV;
|
||||
-
|
||||
/*
|
||||
* configuration access are done through IO space, remap 4
|
||||
* first bytes to access it from CPU.
|
||||
@@ -220,5 +211,3 @@ static int __init bcm63xx_pci_init(void)
|
||||
"bcm63xx PCI IO space");
|
||||
return 0;
|
||||
}
|
||||
-
|
||||
-arch_initcall(bcm63xx_pci_init);
|
||||
@ -0,0 +1,211 @@
|
||||
From 70f970222bc1096689ae1bffeb9ed09a7c4bed07 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Gorski <jonas.gorski@gmail.com>
|
||||
Date: Sat, 12 Nov 2011 12:19:55 +0100
|
||||
Subject: [PATCH 28/60] MIPS: BCM63XX: add HSSPI register definitions
|
||||
|
||||
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
|
||||
---
|
||||
arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 18 ++++++++
|
||||
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 47 +++++++++++++++++++++
|
||||
2 files changed, 65 insertions(+), 0 deletions(-)
|
||||
|
||||
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
|
||||
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
|
||||
@@ -116,6 +116,7 @@ enum bcm63xx_regs_set {
|
||||
RSET_UART1,
|
||||
RSET_GPIO,
|
||||
RSET_SPI,
|
||||
+ RSET_HSSPI,
|
||||
RSET_UDC0,
|
||||
RSET_OHCI0,
|
||||
RSET_OHCI_PRIV,
|
||||
@@ -159,6 +160,7 @@ enum bcm63xx_regs_set {
|
||||
#define RSET_ENETDMA_SIZE 2048
|
||||
#define RSET_ENETSW_SIZE 65536
|
||||
#define RSET_UART_SIZE 24
|
||||
+#define RSET_HSSPI_SIZE 1536
|
||||
#define RSET_UDC_SIZE 256
|
||||
#define RSET_OHCI_SIZE 256
|
||||
#define RSET_EHCI_SIZE 256
|
||||
@@ -182,6 +184,7 @@ enum bcm63xx_regs_set {
|
||||
#define BCM_6328_UART1_BASE (0xb0000120)
|
||||
#define BCM_6328_GPIO_BASE (0xb0000080)
|
||||
#define BCM_6328_SPI_BASE (0xdeadbeef)
|
||||
+#define BCM_6328_HSSPI_BASE (0xb0001000)
|
||||
#define BCM_6328_UDC0_BASE (0xdeadbeef)
|
||||
#define BCM_6328_USBDMA_BASE (0xdeadbeef)
|
||||
#define BCM_6328_OHCI0_BASE (0xdeadbeef)
|
||||
@@ -227,6 +230,7 @@ enum bcm63xx_regs_set {
|
||||
#define BCM_6338_UART1_BASE (0xdeadbeef)
|
||||
#define BCM_6338_GPIO_BASE (0xfffe0400)
|
||||
#define BCM_6338_SPI_BASE (0xfffe0c00)
|
||||
+#define BCM_6338_HSSPI_BASE (0xdeadbeef)
|
||||
#define BCM_6338_UDC0_BASE (0xdeadbeef)
|
||||
#define BCM_6338_USBDMA_BASE (0xfffe2400)
|
||||
#define BCM_6338_OHCI0_BASE (0xdeadbeef)
|
||||
@@ -273,6 +277,7 @@ enum bcm63xx_regs_set {
|
||||
#define BCM_6345_UART1_BASE (0xdeadbeef)
|
||||
#define BCM_6345_GPIO_BASE (0xfffe0400)
|
||||
#define BCM_6345_SPI_BASE (0xdeadbeef)
|
||||
+#define BCM_6345_HSSPI_BASE (0xdeadbeef)
|
||||
#define BCM_6345_UDC0_BASE (0xdeadbeef)
|
||||
#define BCM_6345_USBDMA_BASE (0xfffe2800)
|
||||
#define BCM_6345_ENET0_BASE (0xfffe1800)
|
||||
@@ -318,6 +323,7 @@ enum bcm63xx_regs_set {
|
||||
#define BCM_6348_UART1_BASE (0xdeadbeef)
|
||||
#define BCM_6348_GPIO_BASE (0xfffe0400)
|
||||
#define BCM_6348_SPI_BASE (0xfffe0c00)
|
||||
+#define BCM_6348_HSSPI_BASE (0xdeadbeef)
|
||||
#define BCM_6348_UDC0_BASE (0xfffe1000)
|
||||
#define BCM_6348_OHCI0_BASE (0xfffe1b00)
|
||||
#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
|
||||
@@ -361,6 +367,7 @@ enum bcm63xx_regs_set {
|
||||
#define BCM_6358_UART1_BASE (0xfffe0120)
|
||||
#define BCM_6358_GPIO_BASE (0xfffe0080)
|
||||
#define BCM_6358_SPI_BASE (0xfffe0800)
|
||||
+#define BCM_6358_HSSPI_BASE (0xdeadbeef)
|
||||
#define BCM_6358_UDC0_BASE (0xfffe0800)
|
||||
#define BCM_6358_OHCI0_BASE (0xfffe1400)
|
||||
#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
|
||||
@@ -405,6 +412,7 @@ enum bcm63xx_regs_set {
|
||||
#define BCM_6368_UART1_BASE (0xb0000120)
|
||||
#define BCM_6368_GPIO_BASE (0xb0000080)
|
||||
#define BCM_6368_SPI_BASE (0xb0000800)
|
||||
+#define BCM_6368_HSSPI_BASE (0xdeadbeef)
|
||||
#define BCM_6368_UDC0_BASE (0xdeadbeef)
|
||||
#define BCM_6368_OHCI0_BASE (0xb0001600)
|
||||
#define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef)
|
||||
@@ -454,6 +462,7 @@ extern const unsigned long *bcm63xx_regs
|
||||
__GEN_RSET_BASE(__cpu, UART1) \
|
||||
__GEN_RSET_BASE(__cpu, GPIO) \
|
||||
__GEN_RSET_BASE(__cpu, SPI) \
|
||||
+ __GEN_RSET_BASE(__cpu, HSSPI) \
|
||||
__GEN_RSET_BASE(__cpu, UDC0) \
|
||||
__GEN_RSET_BASE(__cpu, OHCI0) \
|
||||
__GEN_RSET_BASE(__cpu, OHCI_PRIV) \
|
||||
@@ -495,6 +504,7 @@ extern const unsigned long *bcm63xx_regs
|
||||
[RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \
|
||||
[RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \
|
||||
[RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \
|
||||
+ [RSET_HSSPI] = BCM_## __cpu ##_HSSPI_BASE, \
|
||||
[RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \
|
||||
[RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \
|
||||
[RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \
|
||||
@@ -567,6 +577,7 @@ enum bcm63xx_irq {
|
||||
IRQ_ENET0,
|
||||
IRQ_ENET1,
|
||||
IRQ_ENET_PHY,
|
||||
+ IRQ_HSSPI,
|
||||
IRQ_OHCI0,
|
||||
IRQ_EHCI0,
|
||||
IRQ_ENET0_RXDMA,
|
||||
@@ -602,6 +613,7 @@ enum bcm63xx_irq {
|
||||
#define BCM_6328_ENET0_IRQ 0
|
||||
#define BCM_6328_ENET1_IRQ 0
|
||||
#define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
|
||||
+#define BCM_6328_HSSPI_IRQ (IRQ_INTERNAL_BASE + 29)
|
||||
#define BCM_6328_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9)
|
||||
#define BCM_6328_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
|
||||
#define BCM_6328_PCMCIA_IRQ 0
|
||||
@@ -640,6 +652,7 @@ enum bcm63xx_irq {
|
||||
#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
|
||||
#define BCM_6338_ENET1_IRQ 0
|
||||
#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
|
||||
+#define BCM_6338_HSSPI_IRQ 0
|
||||
#define BCM_6338_OHCI0_IRQ 0
|
||||
#define BCM_6338_EHCI0_IRQ 0
|
||||
#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
|
||||
@@ -671,6 +684,7 @@ enum bcm63xx_irq {
|
||||
#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
|
||||
#define BCM_6345_ENET1_IRQ 0
|
||||
#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
|
||||
+#define BCM_6345_HSSPI_IRQ 0
|
||||
#define BCM_6345_OHCI0_IRQ 0
|
||||
#define BCM_6345_EHCI0_IRQ 0
|
||||
#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1)
|
||||
@@ -702,6 +716,7 @@ enum bcm63xx_irq {
|
||||
#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
|
||||
#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
|
||||
#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
|
||||
+#define BCM_6348_HSSPI_IRQ 0
|
||||
#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
|
||||
#define BCM_6348_EHCI0_IRQ 0
|
||||
#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
|
||||
@@ -733,6 +748,7 @@ enum bcm63xx_irq {
|
||||
#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
|
||||
#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
|
||||
#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
|
||||
+#define BCM_6358_HSSPI_IRQ 0
|
||||
#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
|
||||
#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
|
||||
#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
|
||||
@@ -773,6 +789,7 @@ enum bcm63xx_irq {
|
||||
#define BCM_6368_ENET0_IRQ 0
|
||||
#define BCM_6368_ENET1_IRQ 0
|
||||
#define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15)
|
||||
+#define BCM_6368_HSSPI_IRQ 0
|
||||
#define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
|
||||
#define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7)
|
||||
#define BCM_6368_PCMCIA_IRQ 0
|
||||
@@ -813,6 +830,7 @@ extern const int *bcm63xx_irqs;
|
||||
[IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \
|
||||
[IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \
|
||||
[IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \
|
||||
+ [IRQ_HSSPI] = BCM_## __cpu ##_HSSPI_IRQ, \
|
||||
[IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \
|
||||
[IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \
|
||||
[IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \
|
||||
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||
@@ -1231,4 +1231,51 @@
|
||||
|
||||
#define PCIE_DEVICE_OFFSET 0x8000
|
||||
|
||||
+/*************************************************************************
|
||||
+ * _REG relative to RSET_HSSPI
|
||||
+ *************************************************************************/
|
||||
+
|
||||
+#define HSSPI_GLOBAL_CTRL_REG 0x0
|
||||
+#define GLOBAL_CTRL_CLK_POLARITY (1 << 17)
|
||||
+#define GLOBAL_CTRL_CLK_GATE_SSOFF (1 << 16)
|
||||
+
|
||||
+#define HSSPI_GLOBAL_EXT_TRIGGER_REG 0x4
|
||||
+
|
||||
+#define HSSPI_INT_STATUS_REG 0x8
|
||||
+#define HSSPI_INT_STATUS_MASKED_REG 0xc
|
||||
+#define HSSPI_INT_MASK_REG 0x10
|
||||
+
|
||||
+#define HSSPI_PING0_CMD_DONE (1 << 0)
|
||||
+
|
||||
+#define HSSPI_INT_CLEAR_ALL 0xff001f1f
|
||||
+
|
||||
+#define HSSPI_PINGPONG_COMMAND_REG(x) (0x80 + (x) * 0x40)
|
||||
+#define PINGPONG_CMD_COMMAND_MASK 0xf
|
||||
+#define PINGPONG_COMMAND_NOOP 0
|
||||
+#define PINGPONG_COMMAND_START_NOW 1
|
||||
+#define PINGPONG_COMMAND_START_TRIGGER 2
|
||||
+#define PINGPONG_COMMAND_HALT 3
|
||||
+#define PINGPONG_COMMAND_FLUSH 4
|
||||
+#define PINGPONG_CMD_PROFILE_SHIFT 8
|
||||
+#define PINGPONG_CMD_SS_SHIFT 12
|
||||
+
|
||||
+#define HSSPI_PINGPONG_STATUS_REG(x) (0x84 + (x) * 0x40)
|
||||
+
|
||||
+#define HSSPI_PROFILE_CLK_CTRL_REG(x) (0x100 + (x) * 0x20)
|
||||
+#define CLK_CTRL_ACCUM_RST_ON_LOOP (1 << 15)
|
||||
+
|
||||
+#define HSSPI_PROFILE_SIGNAL_CTRL_REG(x) (0x104 + (x) * 0x20)
|
||||
+#define SIGNAL_CTRL_LATCH_RISING (1 << 12)
|
||||
+#define SIGNAL_CTRL_LAUNCH_RISING (1 << 13)
|
||||
+#define SIGNAL_CTRL_ASYNC_INPUT_PATH (1 << 16)
|
||||
+
|
||||
+#define HSSPI_PROFILE_MODE_CTRL_REG(x) (0x108 + (x) * 0x20)
|
||||
+#define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT 8
|
||||
+#define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT 12
|
||||
+#define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT 16
|
||||
+#define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT 18
|
||||
+#define MODE_CTRL_PREPENDBYTE_CNT_SHIFT 24
|
||||
+
|
||||
+#define HSSPI_FIFO_REG(x) (0x200 + (x) * 0x200)
|
||||
+
|
||||
#endif /* BCM63XX_REGS_H_ */
|
||||
@ -1,107 +0,0 @@
|
||||
From 48d3ed67982d2d1cecb5b33bf396d21f6fd7b088 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Gorski <jonas.gorski@gmail.com>
|
||||
Date: Tue, 14 Jun 2011 21:14:39 +0200
|
||||
Subject: [PATCH 39/79] MIPS: BCM63XX: add MISC register set definition
|
||||
|
||||
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
|
||||
---
|
||||
arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 10 +++++++++-
|
||||
arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 2 ++
|
||||
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 10 ++++++++++
|
||||
3 files changed, 21 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
|
||||
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
|
||||
@@ -129,7 +129,8 @@ enum bcm63xx_regs_set {
|
||||
RSET_PCMDMA,
|
||||
RSET_PCMDMAC,
|
||||
RSET_PCMDMAS,
|
||||
- RSET_TRNG
|
||||
+ RSET_TRNG,
|
||||
+ RSET_MISC
|
||||
};
|
||||
|
||||
#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
|
||||
@@ -198,6 +199,7 @@ enum bcm63xx_regs_set {
|
||||
#define BCM_6338_PCMDMAC_BASE (0xdeadbeef)
|
||||
#define BCM_6338_PCMDMAS_BASE (0xdeadbeef)
|
||||
#define BCM_6338_TRNG_BASE (0xdeadbeef)
|
||||
+#define BCM_6338_MISC_BASE (0xdeadbeef)
|
||||
|
||||
/*
|
||||
* 6345 register sets base address
|
||||
@@ -242,6 +244,7 @@ enum bcm63xx_regs_set {
|
||||
#define BCM_6345_PCMDMAC_BASE (0xdeadbeef)
|
||||
#define BCM_6345_PCMDMAS_BASE (0xdeadbeef)
|
||||
#define BCM_6345_TRNG_BASE (0xdeadbeef)
|
||||
+#define BCM_6345_MISC_BASE (0xdeadbeef)
|
||||
|
||||
/*
|
||||
* 6348 register sets base address
|
||||
@@ -283,6 +286,7 @@ enum bcm63xx_regs_set {
|
||||
#define BCM_6348_PCMDMAC_BASE (0xdeadbeef)
|
||||
#define BCM_6348_PCMDMAS_BASE (0xdeadbeef)
|
||||
#define BCM_6348_TRNG_BASE (0xdeadbeef)
|
||||
+#define BCM_6348_MISC_BASE (0xdeadbeef)
|
||||
|
||||
/*
|
||||
* 6358 register sets base address
|
||||
@@ -324,6 +328,7 @@ enum bcm63xx_regs_set {
|
||||
#define BCM_6358_PCMDMAC_BASE (0xfffe1900)
|
||||
#define BCM_6358_PCMDMAS_BASE (0xfffe1a00)
|
||||
#define BCM_6358_TRNG_BASE (0xdeadbeef)
|
||||
+#define BCM_6358_MISC_BASE (0xdeadbeef)
|
||||
|
||||
|
||||
/*
|
||||
@@ -366,6 +371,7 @@ enum bcm63xx_regs_set {
|
||||
#define BCM_6368_PCMDMAC_BASE (0xb0005a00)
|
||||
#define BCM_6368_PCMDMAS_BASE (0xb0005c00)
|
||||
#define BCM_6368_TRNG_BASE (0xb0004180)
|
||||
+#define BCM_6368_MISC_BASE (0xdeadbeef)
|
||||
|
||||
|
||||
extern const unsigned long *bcm63xx_regs_base;
|
||||
@@ -412,6 +418,7 @@ extern const unsigned long *bcm63xx_regs
|
||||
__GEN_RSET_BASE(__cpu, PCMDMAC) \
|
||||
__GEN_RSET_BASE(__cpu, PCMDMAS) \
|
||||
__GEN_RSET_BASE(__cpu, TRNG) \
|
||||
+ __GEN_RSET_BASE(__cpu, MISC) \
|
||||
}
|
||||
|
||||
#define __GEN_CPU_REGS_TABLE(__cpu) \
|
||||
@@ -451,6 +458,7 @@ extern const unsigned long *bcm63xx_regs
|
||||
[RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \
|
||||
[RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \
|
||||
[RSET_TRNG] = BCM_## __cpu ##_TRNG_BASE, \
|
||||
+ [RSET_MISC] = BCM_## __cpu ##_MISC_BASE, \
|
||||
|
||||
|
||||
static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
|
||||
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
|
||||
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
|
||||
@@ -91,5 +91,7 @@
|
||||
#define bcm_memc_writel(v, o) bcm_rset_writel(RSET_MEMC, (v), (o))
|
||||
#define bcm_ddr_readl(o) bcm_rset_readl(RSET_DDR, (o))
|
||||
#define bcm_ddr_writel(v, o) bcm_rset_writel(RSET_DDR, (v), (o))
|
||||
+#define bcm_misc_readl(o) bcm_rset_readl(RSET_MISC, (o))
|
||||
+#define bcm_misc_writel(v, o) bcm_rset_writel(RSET_MISC, (v), (o))
|
||||
|
||||
#endif /* ! BCM63XX_IO_H_ */
|
||||
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||
@@ -1123,4 +1123,14 @@
|
||||
#define TRNG_THRES 0x0c
|
||||
#define TRNG_MASK 0x10
|
||||
|
||||
+/*************************************************************************
|
||||
+ * _REG relative to RSET_MISC
|
||||
+ *************************************************************************/
|
||||
+
|
||||
+#define MISC_STRAPBUS_6328_REG 0x240
|
||||
+#define STRAPBUS_6328_FCVO_SHIFT 7
|
||||
+#define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
|
||||
+#define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28)
|
||||
+#define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28)
|
||||
+
|
||||
#endif /* BCM63XX_REGS_H_ */
|
||||
@ -1,25 +0,0 @@
|
||||
From dc087ed1d9d4ae326a47e4a1eef3a079acf4a1f5 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Gorski <jonas.gorski@gmail.com>
|
||||
Date: Tue, 14 Jun 2011 21:14:39 +0200
|
||||
Subject: [PATCH 41/79] MIPS: BCM63XX: add flash type detection for BCM6328
|
||||
|
||||
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
|
||||
---
|
||||
arch/mips/bcm63xx/dev-flash.c | 6 ++++++
|
||||
1 file changed, 6 insertions(+)
|
||||
|
||||
--- a/arch/mips/bcm63xx/dev-flash.c
|
||||
+++ b/arch/mips/bcm63xx/dev-flash.c
|
||||
@@ -59,6 +59,12 @@ static int __init bcm63xx_detect_flash_t
|
||||
u32 val;
|
||||
|
||||
switch (bcm63xx_get_cpu_id()) {
|
||||
+ case BCM6328_CPU_ID:
|
||||
+ val = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
|
||||
+ if (val & STRAPBUS_6328_BOOT_SEL_SERIAL)
|
||||
+ return BCM63XX_FLASH_TYPE_SERIAL;
|
||||
+ else
|
||||
+ return BCM63XX_FLASH_TYPE_NAND;
|
||||
case BCM6338_CPU_ID:
|
||||
case BCM6345_CPU_ID:
|
||||
case BCM6348_CPU_ID:
|
||||
@ -1,48 +0,0 @@
|
||||
From f7d09679600b187fcfa1d70819e53f190fb1c231 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Gorski <jonas.gorski@gmail.com>
|
||||
Date: Sun, 3 Jul 2011 03:08:11 +0200
|
||||
Subject: [PATCH 45/79] MIPS: BCM63XX: Move the PCI initialization into its
|
||||
own function
|
||||
|
||||
Also make the cpu check a bit more explicit.
|
||||
|
||||
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
|
||||
---
|
||||
arch/mips/pci/pci-bcm63xx.c | 25 +++++++++++++++++--------
|
||||
1 file changed, 17 insertions(+), 8 deletions(-)
|
||||
|
||||
--- a/arch/mips/pci/pci-bcm63xx.c
|
||||
+++ b/arch/mips/pci/pci-bcm63xx.c
|
||||
@@ -88,14 +88,10 @@ static void bcm63xx_int_cfg_writel(u32 v
|
||||
|
||||
void __iomem *pci_iospace_start;
|
||||
|
||||
-int __init bcm63xx_pci_register(void)
|
||||
+static int __init bcm63xx_register_pci(void)
|
||||
{
|
||||
unsigned int mem_size;
|
||||
u32 val;
|
||||
-
|
||||
- if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358() && !BCMCPU_IS_6368())
|
||||
- return -ENODEV;
|
||||
-
|
||||
/*
|
||||
* configuration access are done through IO space, remap 4
|
||||
* first bytes to access it from CPU.
|
||||
@@ -211,3 +207,16 @@ int __init bcm63xx_pci_register(void)
|
||||
"bcm63xx PCI IO space");
|
||||
return 0;
|
||||
}
|
||||
+
|
||||
+int __init bcm63xx_pci_register(void)
|
||||
+{
|
||||
+ switch (bcm63xx_get_cpu_id()) {
|
||||
+ case BCM6348_CPU_ID:
|
||||
+ case BCM6358_CPU_ID:
|
||||
+ case BCM6368_CPU_ID:
|
||||
+ return bcm63xx_register_pci();
|
||||
+ default:
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
@ -1,176 +0,0 @@
|
||||
From 9a16718a325c1969422eb9d9b644eb89ce06692c Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Gorski <jonas.gorski@gmail.com>
|
||||
Date: Sun, 3 Jul 2011 03:41:02 +0200
|
||||
Subject: [PATCH 46/79] MIPS: BCM63XX: Add PCIe register set definitions
|
||||
|
||||
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
|
||||
---
|
||||
arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 9 ++++
|
||||
arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 6 +++
|
||||
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 54 +++++++++++++++++++++
|
||||
3 files changed, 69 insertions(+)
|
||||
|
||||
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
|
||||
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
|
||||
@@ -122,6 +122,7 @@ enum bcm63xx_regs_set {
|
||||
RSET_USBH_PRIV,
|
||||
RSET_MPI,
|
||||
RSET_PCMCIA,
|
||||
+ RSET_PCIE,
|
||||
RSET_DSL,
|
||||
RSET_ENET0,
|
||||
RSET_ENET1,
|
||||
@@ -188,6 +189,7 @@ enum bcm63xx_regs_set {
|
||||
#define BCM_6328_USBH_PRIV_BASE (0xdeadbeef)
|
||||
#define BCM_6328_MPI_BASE (0xdeadbeef)
|
||||
#define BCM_6328_PCMCIA_BASE (0xdeadbeef)
|
||||
+#define BCM_6328_PCIE_BASE (0xb0e40000)
|
||||
#define BCM_6328_SDRAM_REGS_BASE (0xdeadbeef)
|
||||
#define BCM_6328_DSL_BASE (0xb0001900)
|
||||
#define BCM_6328_UBUS_BASE (0xdeadbeef)
|
||||
@@ -232,6 +234,7 @@ enum bcm63xx_regs_set {
|
||||
#define BCM_6338_USBH_PRIV_BASE (0xdeadbeef)
|
||||
#define BCM_6338_MPI_BASE (0xfffe3160)
|
||||
#define BCM_6338_PCMCIA_BASE (0xdeadbeef)
|
||||
+#define BCM_6338_PCIE_BASE (0xdeadbeef)
|
||||
#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)
|
||||
#define BCM_6338_DSL_BASE (0xfffe1000)
|
||||
#define BCM_6338_UBUS_BASE (0xdeadbeef)
|
||||
@@ -279,6 +282,7 @@ enum bcm63xx_regs_set {
|
||||
#define BCM_6345_ENETSW_BASE (0xdeadbeef)
|
||||
#define BCM_6345_PCMCIA_BASE (0xfffe2028)
|
||||
#define BCM_6345_MPI_BASE (0xfffe2000)
|
||||
+#define BCM_6345_PCIE_BASE (0xdeadbeef)
|
||||
#define BCM_6345_OHCI0_BASE (0xfffe2100)
|
||||
#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
|
||||
#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
|
||||
@@ -320,6 +324,7 @@ enum bcm63xx_regs_set {
|
||||
#define BCM_6348_USBH_PRIV_BASE (0xdeadbeef)
|
||||
#define BCM_6348_MPI_BASE (0xfffe2000)
|
||||
#define BCM_6348_PCMCIA_BASE (0xfffe2054)
|
||||
+#define BCM_6348_PCIE_BASE (0xdeadbeef)
|
||||
#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
|
||||
#define BCM_6348_M2M_BASE (0xfffe2800)
|
||||
#define BCM_6348_DSL_BASE (0xfffe3000)
|
||||
@@ -362,6 +367,7 @@ enum bcm63xx_regs_set {
|
||||
#define BCM_6358_USBH_PRIV_BASE (0xfffe1500)
|
||||
#define BCM_6358_MPI_BASE (0xfffe1000)
|
||||
#define BCM_6358_PCMCIA_BASE (0xfffe1054)
|
||||
+#define BCM_6358_PCIE_BASE (0xdeadbeef)
|
||||
#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
|
||||
#define BCM_6358_M2M_BASE (0xdeadbeef)
|
||||
#define BCM_6358_DSL_BASE (0xfffe3000)
|
||||
@@ -405,6 +411,7 @@ enum bcm63xx_regs_set {
|
||||
#define BCM_6368_USBH_PRIV_BASE (0xb0001700)
|
||||
#define BCM_6368_MPI_BASE (0xb0001000)
|
||||
#define BCM_6368_PCMCIA_BASE (0xb0001054)
|
||||
+#define BCM_6368_PCIE_BASE (0xdeadbeef)
|
||||
#define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef)
|
||||
#define BCM_6368_M2M_BASE (0xdeadbeef)
|
||||
#define BCM_6368_DSL_BASE (0xdeadbeef)
|
||||
@@ -453,6 +460,7 @@ extern const unsigned long *bcm63xx_regs
|
||||
__GEN_RSET_BASE(__cpu, USBH_PRIV) \
|
||||
__GEN_RSET_BASE(__cpu, MPI) \
|
||||
__GEN_RSET_BASE(__cpu, PCMCIA) \
|
||||
+ __GEN_RSET_BASE(__cpu, PCIE) \
|
||||
__GEN_RSET_BASE(__cpu, DSL) \
|
||||
__GEN_RSET_BASE(__cpu, ENET0) \
|
||||
__GEN_RSET_BASE(__cpu, ENET1) \
|
||||
@@ -493,6 +501,7 @@ extern const unsigned long *bcm63xx_regs
|
||||
[RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \
|
||||
[RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \
|
||||
[RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \
|
||||
+ [RSET_PCIE] = BCM_## __cpu ##_PCIE_BASE, \
|
||||
[RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \
|
||||
[RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \
|
||||
[RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \
|
||||
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
|
||||
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
|
||||
@@ -40,6 +40,10 @@
|
||||
#define BCM_CB_MEM_END_PA (BCM_CB_MEM_BASE_PA + \
|
||||
BCM_CB_MEM_SIZE - 1)
|
||||
|
||||
+#define BCM_PCIE_MEM_BASE_PA 0x10f00000
|
||||
+#define BCM_PCIE_MEM_SIZE (16 * 1024 * 1024)
|
||||
+#define BCM_PCIE_MEM_END_PA (BCM_PCIE_MEM_BASE_PA + \
|
||||
+ BCM_PCIE_MEM_SIZE - 1)
|
||||
|
||||
/*
|
||||
* Internal registers are accessed through KSEG3
|
||||
@@ -85,6 +89,8 @@
|
||||
#define bcm_mpi_writel(v, o) bcm_rset_writel(RSET_MPI, (v), (o))
|
||||
#define bcm_pcmcia_readl(o) bcm_rset_readl(RSET_PCMCIA, (o))
|
||||
#define bcm_pcmcia_writel(v, o) bcm_rset_writel(RSET_PCMCIA, (v), (o))
|
||||
+#define bcm_pcie_readl(o) bcm_rset_readl(RSET_PCIE, (o))
|
||||
+#define bcm_pcie_writel(v, o) bcm_rset_writel(RSET_PCIE, (v), (o))
|
||||
#define bcm_sdram_readl(o) bcm_rset_readl(RSET_SDRAM, (o))
|
||||
#define bcm_sdram_writel(v, o) bcm_rset_writel(RSET_SDRAM, (v), (o))
|
||||
#define bcm_memc_readl(o) bcm_rset_readl(RSET_MEMC, (o))
|
||||
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||
@@ -1170,6 +1170,9 @@
|
||||
/*************************************************************************
|
||||
* _REG relative to RSET_MISC
|
||||
*************************************************************************/
|
||||
+#define MISC_SERDES_CTRL_REG 0x0
|
||||
+#define SERDES_PCIE_EN (1 << 0)
|
||||
+#define SERDES_PCIE_EXD_EN (1 << 15)
|
||||
|
||||
#define MISC_STRAPBUS_6328_REG 0x240
|
||||
#define STRAPBUS_6328_FCVO_SHIFT 7
|
||||
@@ -1177,4 +1180,55 @@
|
||||
#define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28)
|
||||
#define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28)
|
||||
|
||||
+/*************************************************************************
|
||||
+ * _REG relative to RSET_PCIE
|
||||
+ *************************************************************************/
|
||||
+
|
||||
+#define PCIE_CONFIG2_REG 0x408
|
||||
+#define CONFIG2_BAR1_SIZE_EN 1
|
||||
+#define CONFIG2_BAR1_SIZE_MASK 0xf
|
||||
+
|
||||
+#define PCIE_IDVAL3_REG 0x43c
|
||||
+#define IDVAL3_CLASS_CODE_MASK 0xffffff
|
||||
+#define IDVAL3_SUBCLASS_SHIFT 8
|
||||
+#define IDVAL3_CLASS_SHIFT 16
|
||||
+
|
||||
+#define PCIE_DLSTATUS_REG 0x1048
|
||||
+#define DLSTATUS_PHYLINKUP (1 << 13)
|
||||
+
|
||||
+#define PCIE_BRIDGE_OPT1_REG 0x2820
|
||||
+#define OPT1_RD_BE_OPT_EN (1 << 7)
|
||||
+#define OPT1_RD_REPLY_BE_FIX_EN (1 << 9)
|
||||
+#define OPT1_PCIE_BRIDGE_HOLE_DET_EN (1 << 11)
|
||||
+#define OPT1_L1_INT_STATUS_MASK_POL (1 << 12)
|
||||
+
|
||||
+#define PCIE_BRIDGE_OPT2_REG 0x2824
|
||||
+#define OPT2_UBUS_UR_DECODE_DIS (1 << 2)
|
||||
+#define OPT2_TX_CREDIT_CHK_EN (1 << 4)
|
||||
+#define OPT2_CFG_TYPE1_BD_SEL (1 << 7)
|
||||
+#define OPT2_CFG_TYPE1_BUS_NO_SHIFT 16
|
||||
+#define OPT2_CFG_TYPE1_BUS_NO_MASK (0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT)
|
||||
+
|
||||
+#define PCIE_BRIDGE_BAR0_BASEMASK_REG 0x2828
|
||||
+#define PCIE_BRIDGE_BAR1_BASEMASK_REG 0x2830
|
||||
+#define BASEMASK_REMAP_EN (1 << 0)
|
||||
+#define BASEMASK_SWAP_EN (1 << 1)
|
||||
+#define BASEMASK_MASK_SHIFT 4
|
||||
+#define BASEMASK_MASK_MASK (0xfff << BASEMASK_MASK_SHIFT)
|
||||
+#define BASEMASK_BASE_SHIFT 20
|
||||
+#define BASEMASK_BASE_MASK (0xfff << BASEMASK_BASE_SHIFT)
|
||||
+
|
||||
+#define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c
|
||||
+#define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG 0x2834
|
||||
+#define REBASE_ADDR_BASE_SHIFT 20
|
||||
+#define REBASE_ADDR_BASE_MASK (0xfff << REBASE_ADDR_BASE_SHIFT)
|
||||
+
|
||||
+#define PCIE_BRIDGE_RC_INT_MASK_REG 0x2854
|
||||
+#define PCIE_RC_INT_A (1 << 0)
|
||||
+#define PCIE_RC_INT_B (1 << 1)
|
||||
+#define PCIE_RC_INT_C (1 << 2)
|
||||
+#define PCIE_RC_INT_D (1 << 3)
|
||||
+
|
||||
+#define PCIE_DEVICE_OFFSET 0x8000
|
||||
+
|
||||
#endif /* BCM63XX_REGS_H_ */
|
||||
@ -1,240 +0,0 @@
|
||||
From e170282d7d12f4a26f10d4b666b158d24810d2f6 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Gorski <jonas.gorski@gmail.com>
|
||||
Date: Sun, 3 Jul 2011 03:41:02 +0200
|
||||
Subject: [PATCH 47/79] MIPS: BCM63XX: Add PCIe Support for BCM6328
|
||||
|
||||
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
|
||||
---
|
||||
arch/mips/pci/ops-bcm63xx.c | 61 +++++++++++++++++++++++
|
||||
arch/mips/pci/pci-bcm63xx.c | 112 +++++++++++++++++++++++++++++++++++++++++++
|
||||
arch/mips/pci/pci-bcm63xx.h | 5 ++
|
||||
3 files changed, 178 insertions(+)
|
||||
|
||||
--- a/arch/mips/pci/ops-bcm63xx.c
|
||||
+++ b/arch/mips/pci/ops-bcm63xx.c
|
||||
@@ -465,3 +465,64 @@ static void bcm63xx_fixup(struct pci_dev
|
||||
|
||||
DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm63xx_fixup);
|
||||
#endif
|
||||
+
|
||||
+static int bcm63xx_pcie_can_access(struct pci_bus *bus, int devfn)
|
||||
+{
|
||||
+ switch (bus->number) {
|
||||
+ case PCIE_BUS_BRIDGE:
|
||||
+ return (PCI_SLOT(devfn) == 0);
|
||||
+ case PCIE_BUS_DEVICE:
|
||||
+ if (PCI_SLOT(devfn) == 0)
|
||||
+ return bcm_pcie_readl(PCIE_DLSTATUS_REG)
|
||||
+ & DLSTATUS_PHYLINKUP;
|
||||
+ default:
|
||||
+ return false;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static int bcm63xx_pcie_read(struct pci_bus *bus, unsigned int devfn,
|
||||
+ int where, int size, u32 *val)
|
||||
+{
|
||||
+ u32 data;
|
||||
+ u32 reg = where & ~3;
|
||||
+
|
||||
+ if (!bcm63xx_pcie_can_access(bus, devfn))
|
||||
+ return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
+
|
||||
+ if (bus->number == PCIE_BUS_DEVICE)
|
||||
+ reg += PCIE_DEVICE_OFFSET;
|
||||
+
|
||||
+ data = bcm_pcie_readl(reg);
|
||||
+
|
||||
+ *val = postprocess_read(data, where, size);
|
||||
+
|
||||
+ return PCIBIOS_SUCCESSFUL;
|
||||
+
|
||||
+}
|
||||
+
|
||||
+static int bcm63xx_pcie_write(struct pci_bus *bus, unsigned int devfn,
|
||||
+ int where, int size, u32 val)
|
||||
+{
|
||||
+ u32 data;
|
||||
+ u32 reg = where & ~3;
|
||||
+
|
||||
+ if (!bcm63xx_pcie_can_access(bus, devfn))
|
||||
+ return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
+
|
||||
+ if (bus->number == PCIE_BUS_DEVICE)
|
||||
+ reg += PCIE_DEVICE_OFFSET;
|
||||
+
|
||||
+
|
||||
+ data = bcm_pcie_readl(reg);
|
||||
+
|
||||
+ data = preprocess_write(data, val, where, size);
|
||||
+ bcm_pcie_writel(data, reg);
|
||||
+
|
||||
+ return PCIBIOS_SUCCESSFUL;
|
||||
+}
|
||||
+
|
||||
+
|
||||
+struct pci_ops bcm63xx_pcie_ops = {
|
||||
+ .read = bcm63xx_pcie_read,
|
||||
+ .write = bcm63xx_pcie_write
|
||||
+};
|
||||
--- a/arch/mips/pci/pci-bcm63xx.c
|
||||
+++ b/arch/mips/pci/pci-bcm63xx.c
|
||||
@@ -10,6 +10,7 @@
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
+#include <linux/delay.h>
|
||||
#include <asm/bootinfo.h>
|
||||
|
||||
#include "pci-bcm63xx.h"
|
||||
@@ -65,6 +66,26 @@ struct pci_controller bcm63xx_cb_control
|
||||
};
|
||||
#endif
|
||||
|
||||
+static struct resource bcm_pcie_mem_resource = {
|
||||
+ .name = "bcm63xx PCIe memory space",
|
||||
+ .start = BCM_PCIE_MEM_BASE_PA,
|
||||
+ .end = BCM_PCIE_MEM_END_PA,
|
||||
+ .flags = IORESOURCE_MEM,
|
||||
+};
|
||||
+
|
||||
+static struct resource bcm_pcie_io_resource = {
|
||||
+ .name = "bcm63xx PCIe IO space",
|
||||
+ .start = 0,
|
||||
+ .end = 0,
|
||||
+ .flags = 0,
|
||||
+};
|
||||
+
|
||||
+struct pci_controller bcm63xx_pcie_controller = {
|
||||
+ .pci_ops = &bcm63xx_pcie_ops,
|
||||
+ .io_resource = &bcm_pcie_io_resource,
|
||||
+ .mem_resource = &bcm_pcie_mem_resource,
|
||||
+};
|
||||
+
|
||||
static u32 bcm63xx_int_cfg_readl(u32 reg)
|
||||
{
|
||||
u32 tmp;
|
||||
@@ -88,6 +109,95 @@ static void bcm63xx_int_cfg_writel(u32 v
|
||||
|
||||
void __iomem *pci_iospace_start;
|
||||
|
||||
+static void __init bcm63xx_reset_pcie(void)
|
||||
+{
|
||||
+ u32 val;
|
||||
+
|
||||
+ /* enable clock */
|
||||
+ val = bcm_perf_readl(PERF_CKCTL_REG);
|
||||
+ val |= CKCTL_6328_PCIE_EN;
|
||||
+ bcm_perf_writel(val, PERF_CKCTL_REG);
|
||||
+
|
||||
+ /* enable SERDES */
|
||||
+ val = bcm_misc_readl(MISC_SERDES_CTRL_REG);
|
||||
+ val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN;
|
||||
+ bcm_misc_writel(val, MISC_SERDES_CTRL_REG);
|
||||
+
|
||||
+ /* reset the PCIe core */
|
||||
+ val = bcm_perf_readl(PERF_SOFTRESET_6328_REG);
|
||||
+
|
||||
+ val &= ~SOFTRESET_6328_PCIE_MASK;
|
||||
+ val &= ~SOFTRESET_6328_PCIE_CORE_MASK;
|
||||
+ val &= ~SOFTRESET_6328_PCIE_HARD_MASK;
|
||||
+ val &= ~SOFTRESET_6328_PCIE_EXT_MASK;
|
||||
+ bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
|
||||
+ mdelay(10);
|
||||
+
|
||||
+ val |= SOFTRESET_6328_PCIE_MASK;
|
||||
+ val |= SOFTRESET_6328_PCIE_CORE_MASK;
|
||||
+ val |= SOFTRESET_6328_PCIE_HARD_MASK;
|
||||
+ bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
|
||||
+ mdelay(10);
|
||||
+
|
||||
+ val |= SOFTRESET_6328_PCIE_EXT_MASK;
|
||||
+ bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
|
||||
+ mdelay(200);
|
||||
+}
|
||||
+
|
||||
+static int __init bcm63xx_register_pcie(void)
|
||||
+{
|
||||
+ u32 val;
|
||||
+
|
||||
+ bcm63xx_reset_pcie();
|
||||
+
|
||||
+ /* configure the PCIe bridge */
|
||||
+ val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG);
|
||||
+ val |= OPT1_RD_BE_OPT_EN;
|
||||
+ val |= OPT1_RD_REPLY_BE_FIX_EN;
|
||||
+ val |= OPT1_PCIE_BRIDGE_HOLE_DET_EN;
|
||||
+ val |= OPT1_L1_INT_STATUS_MASK_POL;
|
||||
+ bcm_pcie_writel(val, PCIE_BRIDGE_OPT1_REG);
|
||||
+
|
||||
+ /* setup the interrupts */
|
||||
+ val = bcm_pcie_readl(PCIE_BRIDGE_RC_INT_MASK_REG);
|
||||
+ val |= PCIE_RC_INT_A | PCIE_RC_INT_B | PCIE_RC_INT_C | PCIE_RC_INT_D;
|
||||
+ bcm_pcie_writel(val, PCIE_BRIDGE_RC_INT_MASK_REG);
|
||||
+
|
||||
+ val = bcm_pcie_readl(PCIE_BRIDGE_OPT2_REG);
|
||||
+ /* enable credit checking and error checking */
|
||||
+ val |= OPT2_TX_CREDIT_CHK_EN;
|
||||
+ val |= OPT2_UBUS_UR_DECODE_DIS;
|
||||
+
|
||||
+ /* set device bus/func for the pcie device */
|
||||
+ val |= (PCIE_BUS_DEVICE << OPT2_CFG_TYPE1_BUS_NO_SHIFT);
|
||||
+ val |= OPT2_CFG_TYPE1_BD_SEL;
|
||||
+ bcm_pcie_writel(val, PCIE_BRIDGE_OPT2_REG);
|
||||
+
|
||||
+ /* setup class code as bridge */
|
||||
+ val = bcm_pcie_readl(PCIE_IDVAL3_REG);
|
||||
+ val &= ~IDVAL3_CLASS_CODE_MASK;
|
||||
+ val |= (PCI_CLASS_BRIDGE_PCI << IDVAL3_SUBCLASS_SHIFT);
|
||||
+ bcm_pcie_writel(val, PCIE_IDVAL3_REG);
|
||||
+
|
||||
+ /* disable bar1 size */
|
||||
+ val = bcm_pcie_readl(PCIE_CONFIG2_REG);
|
||||
+ val &= ~CONFIG2_BAR1_SIZE_MASK;
|
||||
+ bcm_pcie_writel(val, PCIE_CONFIG2_REG);
|
||||
+
|
||||
+ /* set bar0 to little endian */
|
||||
+ val = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT;
|
||||
+ val |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT;
|
||||
+ val |= BASEMASK_REMAP_EN;
|
||||
+ bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG);
|
||||
+
|
||||
+ val = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT;
|
||||
+ bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);
|
||||
+
|
||||
+ register_pci_controller(&bcm63xx_pcie_controller);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static int __init bcm63xx_register_pci(void)
|
||||
{
|
||||
unsigned int mem_size;
|
||||
@@ -211,6 +321,8 @@ static int __init bcm63xx_register_pci(v
|
||||
int __init bcm63xx_pci_register(void)
|
||||
{
|
||||
switch (bcm63xx_get_cpu_id()) {
|
||||
+ case BCM6328_CPU_ID:
|
||||
+ return bcm63xx_register_pcie();
|
||||
case BCM6348_CPU_ID:
|
||||
case BCM6358_CPU_ID:
|
||||
case BCM6368_CPU_ID:
|
||||
--- a/arch/mips/pci/pci-bcm63xx.h
|
||||
+++ b/arch/mips/pci/pci-bcm63xx.h
|
||||
@@ -13,11 +13,16 @@
|
||||
*/
|
||||
#define CARDBUS_PCI_IDSEL 0x8
|
||||
|
||||
+
|
||||
+#define PCIE_BUS_BRIDGE 0
|
||||
+#define PCIE_BUS_DEVICE 1
|
||||
+
|
||||
/*
|
||||
* defined in ops-bcm63xx.c
|
||||
*/
|
||||
extern struct pci_ops bcm63xx_pci_ops;
|
||||
extern struct pci_ops bcm63xx_cb_ops;
|
||||
+extern struct pci_ops bcm63xx_pcie_ops;
|
||||
|
||||
/*
|
||||
* defined in pci-bcm63xx.c
|
||||
Loading…
Reference in New Issue