kernel: bump 4.14 to 4.14.136
Refreshed all patches. Altered patches: - 306-v4.16-netfilter-remove-saveroute-indirection-in-struct-nf_.patch Remove upstreamed: - 100-powerpc-4xx-uic-clear-pending-interrupt-after-irq-ty.patch - 088-0002-i2c-qup-fixed-releasing-dma-without-flush-operation.patch - 500-arm64-dts-marvell-Fix-A37xx-UART0-register-size.patch Fixes: - CVE-2019-13648 - CVE-2019-10207 Compile-tested on: cns3xxx Runtime-tested on: cns3xxx Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>master
Koen Vandeputte
5 years ago
parent
a4d366005d
commit
96f1d4b02b
@ -1,30 +0,0 @@
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From 9b84ad676e248a3e3c81db7f5d39e1739b3780aa Mon Sep 17 00:00:00 2001
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From: Christian Lamparter <chunkeey@gmail.com>
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Date: Sat, 15 Jun 2019 16:35:26 +0200
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Subject: [PATCH] powerpc/4xx/uic: clear pending interrupt after irq type/pol
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change
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When testing out gpio-keys with a button, a spurious
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interrupt (and therefore a key press or release event)
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gets triggered as soon as the driver enables the irq
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line for the first time.
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This patch clears any potential bogus generated interrupt
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that was caused by the switching of the associated irq's
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type and polarity.
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Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
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---
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arch/powerpc/platforms/4xx/uic.c | 1 +
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1 file changed, 1 insertion(+)
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--- a/arch/powerpc/platforms/4xx/uic.c
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+++ b/arch/powerpc/platforms/4xx/uic.c
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@@ -158,6 +158,7 @@ static int uic_set_irq_type(struct irq_d
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mtdcr(uic->dcrbase + UIC_PR, pr);
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mtdcr(uic->dcrbase + UIC_TR, tr);
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+ mtdcr(uic->dcrbase + UIC_SR, ~mask);
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raw_spin_unlock_irqrestore(&uic->lock, flags);
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@ -1,44 +0,0 @@
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From 7239872fb3400b21a8f5547257f9f86455867bd6 Mon Sep 17 00:00:00 2001
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From: Abhishek Sahu <absahu@codeaurora.org>
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Date: Mon, 12 Mar 2018 18:44:51 +0530
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Subject: [PATCH 02/13] i2c: qup: fixed releasing dma without flush operation
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completion
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The QUP BSLP BAM generates the following error sometimes if the
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current I2C DMA transfer fails and the flush operation has been
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scheduled
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“bam-dma-engine 7884000.dma: Cannot free busy channel”
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If any I2C error comes during BAM DMA transfer, then the QUP I2C
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interrupt will be generated and the flush operation will be
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carried out to make I2C consume all scheduled DMA transfer.
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Currently, the same completion structure is being used for BAM
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transfer which has already completed without reinit. It will make
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flush operation wait_for_completion_timeout completed immediately
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and will proceed for freeing the DMA resources where the
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descriptors are still in process.
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Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
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Acked-by: Sricharan R <sricharan@codeaurora.org>
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Reviewed-by: Austin Christ <austinwc@codeaurora.org>
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Reviewed-by: Andy Gross <andy.gross@linaro.org>
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Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
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---
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drivers/i2c/busses/i2c-qup.c | 2 ++
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1 file changed, 2 insertions(+)
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--- a/drivers/i2c/busses/i2c-qup.c
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+++ b/drivers/i2c/busses/i2c-qup.c
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@@ -835,6 +835,8 @@ static int qup_i2c_bam_do_xfer(struct qu
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}
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if (ret || qup->bus_err || qup->qup_err) {
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+ reinit_completion(&qup->xfer);
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+
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if (qup_i2c_change_state(qup, QUP_RUN_STATE)) {
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dev_err(qup->dev, "change to run state timed out");
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goto desc_err;
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@ -1,39 +0,0 @@
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From c737abc193d16e62e23e2fb585b8b7398ab380d8 Mon Sep 17 00:00:00 2001
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From: allen yan <yanwei@marvell.com>
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Date: Thu, 7 Sep 2017 15:04:53 +0200
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Subject: arm64: dts: marvell: Fix A37xx UART0 register size
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Armada-37xx UART0 registers are 0x200 bytes wide. Right next to them are
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the UART1 registers that should not be declared in this node.
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Update the example in DT bindings document accordingly.
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Signed-off-by: allen yan <yanwei@marvell.com>
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Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
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Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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---
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Documentation/devicetree/bindings/serial/mvebu-uart.txt | 2 +-
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arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 +-
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2 files changed, 2 insertions(+), 2 deletions(-)
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--- a/Documentation/devicetree/bindings/serial/mvebu-uart.txt
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+++ b/Documentation/devicetree/bindings/serial/mvebu-uart.txt
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@@ -8,6 +8,6 @@ Required properties:
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Example:
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serial@12000 {
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compatible = "marvell,armada-3700-uart";
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- reg = <0x12000 0x400>;
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+ reg = <0x12000 0x200>;
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interrupts = <43>;
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};
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--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
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+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
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@@ -134,7 +134,7 @@
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uart0: serial@12000 {
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compatible = "marvell,armada-3700-uart";
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- reg = <0x12000 0x400>;
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+ reg = <0x12000 0x200>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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