ipq40xx: use patches that were sent upstream
Signed-off-by: John Crispin <john@phrozen.org>v19.07.3_mercusys_ac12_duma
John Crispin
6 years ago
parent
e8c58e7ddd
commit
95672e0433
@ -0,0 +1,38 @@
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From d60e006ec0e425877aacc61c7ece3da0434a8fce Mon Sep 17 00:00:00 2001
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From: Christian Lamparter <chunkeey@gmail.com>
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Date: Mon, 23 Jul 2018 16:34:54 +0200
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Subject: [PATCH 7/8] qcom: ipq4019: fix cpu0's qcom,saw2 reg value
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while compiling an ipq4019 target, dtc will complain:
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regulator@b089000 unit address format error, expected "2089000"
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The saw0 regulator reg value seems to be
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copied and pasted from qcom-ipq8064.dtsi.
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This patch fixes the reg value to match that of the
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unit address which in turn silences the warning.
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(There is no driver for qcom,saw2 right now.
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So this went unnoticed)
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Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
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Signed-off-by: John Crispin <john@phrozen.org>
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---
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arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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index 98b9850ed2a0..3289b3a6c10e 100644
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--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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@@ -316,7 +316,7 @@
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saw0: regulator@b089000 {
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compatible = "qcom,saw2";
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- reg = <0x02089000 0x1000>, <0x0b009000 0x1000>;
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+ reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
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regulator;
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};
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--
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2.11.0
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@ -1,28 +1,33 @@
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From e7748d641ae37081e2034869491f1629461ae13c Mon Sep 17 00:00:00 2001
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From 89b43d59ec8c9cda588555eb1f2754dd19ef5144 Mon Sep 17 00:00:00 2001
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From: Christian Lamparter <chunkeey@gmail.com>
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Date: Sat, 19 Nov 2016 00:58:18 +0100
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Subject: [PATCH] ARM: qcom: Add IPQ4019 SoC support
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Date: Sun, 22 Jul 2018 12:07:57 +0200
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Subject: [PATCH 8/8] ARM: qcom: Add IPQ4019 SoC support
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Add support for the Qualcomm Atheros IPQ4019 SoC.
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Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
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Signed-off-by: John Crispin <john@phrozen.org>
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---
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arch/arm/Makefile | 1 +
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arch/arm/mach-qcom/Kconfig | 5 +++++
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2 files changed, 6 insertions(+)
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--- a/arch/arm/Makefile
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+++ b/arch/arm/Makefile
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@@ -149,6 +149,7 @@ textofs-$(CONFIG_SA1111) := 0x00208000
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endif
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Index: linux-4.14.54/arch/arm/Makefile
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===================================================================
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--- linux-4.14.54.orig/arch/arm/Makefile
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+++ linux-4.14.54/arch/arm/Makefile
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@@ -150,6 +150,7 @@ endif
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textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
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textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
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+textofs-$(CONFIG_ARCH_IPQ40XX) := 0x00208000
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textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
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+textofs-$(CONFIG_ARCH_IPQ40XX) := 0x00208000
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# Machine directory name. This list is sorted alphanumerically
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--- a/arch/arm/mach-qcom/Kconfig
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+++ b/arch/arm/mach-qcom/Kconfig
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# by CONFIG_* macro name.
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Index: linux-4.14.54/arch/arm/mach-qcom/Kconfig
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===================================================================
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--- linux-4.14.54.orig/arch/arm/mach-qcom/Kconfig
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+++ linux-4.14.54/arch/arm/mach-qcom/Kconfig
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@@ -27,4 +27,9 @@ config ARCH_MDM9615
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bool "Enable support for MDM9615"
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select CLKSRC_QCOM
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@ -0,0 +1,44 @@
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From 5f01733dc755dfadfa51b7b3c6c160e632fc6002 Mon Sep 17 00:00:00 2001
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From: John Crispin <john@phrozen.org>
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Date: Tue, 24 Jul 2018 15:09:36 +0200
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Subject: [PATCH 1/3] dt-bindings: phy-qcom-ipq4019-usb: add binding document
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This patch adds the binding documentation for the HS/SS USB PHY found
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inside Qualcom Dakota SoCs.
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Signed-off-by: John Crispin <john@phrozen.org>
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---
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.../bindings/phy/phy-qcom-ipq4019-usb.txt | 21 +++++++++++++++++++++
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1 file changed, 21 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt
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diff --git a/Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt b/Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt
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new file mode 100644
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index 000000000000..362877fcafed
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt
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@@ -0,0 +1,21 @@
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+Qualcom Dakota HS/SS USB PHY
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+
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+Required properties:
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+ - compatible: "qcom,usb-ss-ipq4019-phy",
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+ "qcom,usb-hs-ipq4019-phy"
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+ - reg: offset and length of the registers
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+ - #phy-cells: should be 0
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+ - resets: the reset controllers as listed below
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+ - reset-names: the names of the reset controllers
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+ "por_rst" - the POR reset line for SS and HS phys
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+ "srif_rst" - the SRIF reset line for HS phys
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+Example:
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+
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+hsphy@a8000 {
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+ compatible = "qcom,usb-hs-ipq4019-phy";
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+ phy-cells = <0>;
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+ reg = <0xa8000 0x40>;
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+ resets = <&gcc USB2_HSPHY_POR_ARES>,
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+ <&gcc USB2_HSPHY_S_ARES>;
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+ reset-names = "por_rst", "srif_rst";
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+};
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--
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2.11.0
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@ -0,0 +1,130 @@
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From 1fc7d5523e21ed140fed43c4dde011a3b6d9ba08 Mon Sep 17 00:00:00 2001
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From: John Crispin <john@phrozen.org>
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Date: Tue, 24 Jul 2018 14:47:55 +0200
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Subject: [PATCH 3/3] qcom: ipq4019: add USB devicetree nodes
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This patch makes USB work on the Dakota EVB.
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Signed-off-by: John Crispin <john@phrozen.org>
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---
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arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 ++++++++
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arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++++++++++
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2 files changed, 94 insertions(+)
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diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
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index 418f9a022336..2ee5f05d5a43 100644
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--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
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@@ -109,5 +109,25 @@
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wifi@a800000 {
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status = "ok";
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};
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+
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+ usb3_ss_phy: ssphy@9a000 {
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+ status = "ok";
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+ };
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+
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+ usb3_hs_phy: hsphy@a6000 {
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+ status = "ok";
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+ };
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+
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+ usb3: usb3@8af8800 {
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+ status = "ok";
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+ };
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+
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+ usb2_hs_phy: hsphy@a8000 {
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+ status = "ok";
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+ };
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+
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+ usb2: usb2@60f8800 {
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+ status = "ok";
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+ };
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};
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};
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diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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index e5e52adbd5a3..e6b12129f0e4 100644
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--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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@@ -553,5 +553,79 @@
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"legacy";
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status = "disabled";
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};
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+
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+ usb3_ss_phy: ssphy@9a000 {
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+ compatible = "qcom,usb-ss-ipq4019-phy";
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+ #phy-cells = <0>;
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+ reg = <0x9a000 0x800>;
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+ reg-names = "phy_base";
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+ resets = <&gcc USB3_UNIPHY_PHY_ARES>;
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+ reset-names = "por_rst";
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+ status = "disabled";
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+ };
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+
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+ usb3_hs_phy: hsphy@a6000 {
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+ compatible = "qcom,usb-hs-ipq4019-phy";
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+ #phy-cells = <0>;
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+ reg = <0xa6000 0x40>;
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+ reg-names = "phy_base";
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+ resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
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+ reset-names = "por_rst", "srif_rst";
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+ status = "disabled";
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+ };
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+
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+ usb3@8af8800 {
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+ compatible = "qcom,dwc3";
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+ reg = <0x8af8800 0x100>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ clocks = <&gcc GCC_USB3_MASTER_CLK>,
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+ <&gcc GCC_USB3_SLEEP_CLK>,
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+ <&gcc GCC_USB3_MOCK_UTMI_CLK>;
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+ clock-names = "master", "sleep", "mock_utmi";
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+ ranges;
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+ status = "disabled";
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+
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+ dwc3@8a00000 {
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+ compatible = "snps,dwc3";
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+ reg = <0x8a00000 0xf8000>;
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+ interrupts = <0 132 0>;
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+ phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
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+ phy-names = "usb2-phy", "usb3-phy";
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+ dr_mode = "host";
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+ };
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+ };
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+
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+ usb2_hs_phy: hsphy@a8000 {
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+ compatible = "qcom,usb-hs-ipq4019-phy";
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+ #phy-cells = <0>;
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+ reg = <0xa8000 0x40>;
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+ reg-names = "phy_base";
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+ resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
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+ reset-names = "por_rst", "srif_rst";
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+ status = "disabled";
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+ };
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+
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+ usb2@60f8800 {
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+ compatible = "qcom,dwc3";
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+ reg = <0x60f8800 0x100>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ clocks = <&gcc GCC_USB2_MASTER_CLK>,
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+ <&gcc GCC_USB2_SLEEP_CLK>,
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+ <&gcc GCC_USB2_MOCK_UTMI_CLK>;
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+ clock-names = "master", "sleep", "mock_utmi";
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+ ranges;
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+ status = "disabled";
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+
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+ dwc3@6000000 {
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+ compatible = "snps,dwc3";
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+ reg = <0x6000000 0xf8000>;
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+ interrupts = <0 136 0>;
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+ phys = <&usb2_hs_phy>;
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+ phy-names = "usb2-phy";
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+ dr_mode = "host";
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+ };
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+ };
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};
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};
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--
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2.11.0
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