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@ -80,7 +80,7 @@ ifx_ssc_get_kernel_clk (struct ifx_ssc_port *info)
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{
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unsigned int rmc;
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rmc = (readl(IFXMIPS_SSC_CLC) & IFX_CLC_RUN_DIVIDER_MASK) >> IFX_CLC_RUN_DIVIDER_OFFSET;
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rmc = (ifxmips_r32(IFXMIPS_SSC_CLC) & IFX_CLC_RUN_DIVIDER_MASK) >> IFX_CLC_RUN_DIVIDER_OFFSET;
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if (rmc == 0)
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{
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printk ("ifx_ssc_get_kernel_clk rmc==0 \n");
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@ -97,12 +97,12 @@ rx_int (struct ifx_ssc_port *info)
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unsigned long *tmp_ptr;
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unsigned int rx_valid_cnt;
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/* number of words waiting in the RX FIFO */
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fifo_fill_lev = (readl(IFXMIPS_SSC_FSTAT) & IFX_SSC_FSTAT_RECEIVED_WORDS_MASK) >> IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET;
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fifo_fill_lev = (ifxmips_r32(IFXMIPS_SSC_FSTAT) & IFX_SSC_FSTAT_RECEIVED_WORDS_MASK) >> IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET;
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bytes_in_buf = info->rxbuf_end - info->rxbuf_ptr;
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// transfer with 32 bits per entry
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while ((bytes_in_buf >= 4) && (fifo_fill_lev > 0)) {
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tmp_ptr = (unsigned long *) info->rxbuf_ptr;
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*tmp_ptr = readl(IFXMIPS_SSC_RB);
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*tmp_ptr = ifxmips_r32(IFXMIPS_SSC_RB);
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info->rxbuf_ptr += 4;
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info->stats.rxBytes += 4;
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fifo_fill_lev--;
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@ -111,14 +111,14 @@ rx_int (struct ifx_ssc_port *info)
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// now do the rest as mentioned in STATE.RXBV
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while ((bytes_in_buf > 0) && (fifo_fill_lev > 0)) {
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rx_valid_cnt = (readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET;
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rx_valid_cnt = (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET;
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if (rx_valid_cnt == 0)
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break;
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if (rx_valid_cnt > bytes_in_buf)
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rx_valid_cnt = bytes_in_buf;
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tmp_val = readl(IFXMIPS_SSC_RB);
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tmp_val = ifxmips_r32(IFXMIPS_SSC_RB);
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for (i = 0; i < rx_valid_cnt; i++)
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{
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@ -134,12 +134,12 @@ rx_int (struct ifx_ssc_port *info)
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{
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disable_irq(IFXMIPS_SSC_RIR);
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wake_up_interruptible (&info->rwait);
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} else if ((info->opts.modeRxTx == IFX_SSC_MODE_RX) && (readl(IFXMIPS_SSC_RXCNT) == 0))
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} else if ((info->opts.modeRxTx == IFX_SSC_MODE_RX) && (ifxmips_r32(IFXMIPS_SSC_RXCNT) == 0))
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{
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if (info->rxbuf_end - info->rxbuf_ptr < IFX_SSC_RXREQ_BLOCK_SIZE)
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writel((info->rxbuf_end - info->rxbuf_ptr) << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
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ifxmips_w32((info->rxbuf_end - info->rxbuf_ptr) << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
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else
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writel(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
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ifxmips_w32(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
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}
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}
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@ -148,8 +148,8 @@ tx_int (struct ifx_ssc_port *info)
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{
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int fifo_space, fill, i;
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fifo_space = ((readl(IFXMIPS_SSC_ID) & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET)
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- ((readl(IFXMIPS_SSC_FSTAT) & IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK) >> IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET);
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fifo_space = ((ifxmips_r32(IFXMIPS_SSC_ID) & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET)
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- ((ifxmips_r32(IFXMIPS_SSC_FSTAT) & IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK) >> IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET);
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if (fifo_space == 0)
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return;
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@ -162,7 +162,7 @@ tx_int (struct ifx_ssc_port *info)
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for (i = 0; i < fill / 4; i++)
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{
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// at first 32 bit access
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writel(*(UINT32 *) info->txbuf_ptr, IFXMIPS_SSC_TB);
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ifxmips_w32(*(UINT32 *) info->txbuf_ptr, IFXMIPS_SSC_TB);
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info->txbuf_ptr += 4;
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}
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@ -224,7 +224,7 @@ ifx_ssc_err_int (int irq, void *dev_id)
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unsigned long flags;
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local_irq_save (flags);
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state = readl(IFXMIPS_SSC_STATE);
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state = ifxmips_r32(IFXMIPS_SSC_STATE);
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if ((state & IFX_SSC_STATE_RX_UFL) != 0) {
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info->stats.rxUnErr++;
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@ -252,7 +252,7 @@ ifx_ssc_err_int (int irq, void *dev_id)
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}
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if (write_back)
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writel(write_back, IFXMIPS_SSC_WHBSTATE);
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ifxmips_w32(write_back, IFXMIPS_SSC_WHBSTATE);
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local_irq_restore (flags);
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@ -278,12 +278,12 @@ ifx_ssc_abort (struct ifx_ssc_port *info)
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// complete word. The disable cuts the transmission immediatly and
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// releases the chip selects. This could result in unpredictable
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// behavior of connected external devices!
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enabled = (readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED) != 0;
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writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
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enabled = (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED) != 0;
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ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
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// flush fifos
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writel(IFX_SSC_XFCON_FIFO_FLUSH, IFXMIPS_SSC_TXFCON);
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writel(IFX_SSC_XFCON_FIFO_FLUSH, IFXMIPS_SSC_RXFCON);
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ifxmips_w32(IFX_SSC_XFCON_FIFO_FLUSH, IFXMIPS_SSC_TXFCON);
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ifxmips_w32(IFX_SSC_XFCON_FIFO_FLUSH, IFXMIPS_SSC_RXFCON);
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// free txbuf
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if (info->txbuf != NULL)
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@ -302,10 +302,10 @@ ifx_ssc_abort (struct ifx_ssc_port *info)
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mask_and_ack_ifxmips_irq(IFXMIPS_SSC_EIR);
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// clear error flags
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writel(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, IFXMIPS_SSC_WHBSTATE);
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ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, IFXMIPS_SSC_WHBSTATE);
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if (enabled)
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writel(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
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ifxmips_w32(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
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}
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@ -343,22 +343,22 @@ ifx_ssc_open (struct inode *inode, struct file *filp)
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disable_irq(IFXMIPS_SSC_EIR);
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/* Flush and enable TX/RX FIFO */
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writel((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_TXFCON);
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writel((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_RXFCON);
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ifxmips_w32((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_TXFCON);
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ifxmips_w32((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_RXFCON);
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/* logically flush the software FIFOs */
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info->rxbuf_ptr = 0;
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info->txbuf_ptr = 0;
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/* clear all error bits */
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writel(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, IFXMIPS_SSC_WHBSTATE);
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ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, IFXMIPS_SSC_WHBSTATE);
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// clear pending interrupts
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mask_and_ack_ifxmips_irq(IFXMIPS_SSC_RIR);
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mask_and_ack_ifxmips_irq(IFXMIPS_SSC_TIR);
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mask_and_ack_ifxmips_irq(IFXMIPS_SSC_EIR);
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writel(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
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ifxmips_w32(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
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return 0;
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}
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@ -382,7 +382,7 @@ ifx_ssc_close (struct inode *inode, struct file *filp)
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if (!info)
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return -ENXIO;
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writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
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ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
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ifx_ssc_abort(info);
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@ -451,13 +451,13 @@ ifx_ssc_read_helper (struct ifx_ssc_port *info, char *buf, size_t len, int from_
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enable_irq(IFXMIPS_SSC_RIR);
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} else {
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local_irq_restore(flags);
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if (readl(IFXMIPS_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK)
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if (ifxmips_r32(IFXMIPS_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK)
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return -EBUSY;
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enable_irq(IFXMIPS_SSC_RIR);
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if (len < IFX_SSC_RXREQ_BLOCK_SIZE)
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writel(len << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
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ifxmips_w32(len << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
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else
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writel(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
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ifxmips_w32(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
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}
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__add_wait_queue (&info->rwait, &wait);
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@ -643,12 +643,12 @@ ifx_ssc_frm_status_get (struct ifx_ssc_port *info)
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{
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unsigned long tmp;
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tmp = readl(IFXMIPS_SSC_SFSTAT);
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tmp = ifxmips_r32(IFXMIPS_SSC_SFSTAT);
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info->frm_status.DataBusy = (tmp & IFX_SSC_SFSTAT_IN_DATA) > 0;
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info->frm_status.PauseBusy = (tmp & IFX_SSC_SFSTAT_IN_PAUSE) > 0;
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info->frm_status.DataCount = (tmp & IFX_SSC_SFSTAT_DATA_COUNT_MASK) >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET;
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info->frm_status.PauseCount = (tmp & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK) >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET;
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tmp = readl(IFXMIPS_SSC_SFCON);
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tmp = ifxmips_r32(IFXMIPS_SSC_SFCON);
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info->frm_status.EnIntAfterData = (tmp & IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE) > 0;
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info->frm_status.EnIntAfterPause = (tmp & IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE) > 0;
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@ -661,7 +661,7 @@ ifx_ssc_frm_control_get (struct ifx_ssc_port *info)
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{
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unsigned long tmp;
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tmp = readl(IFXMIPS_SSC_SFCON);
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tmp = ifxmips_r32(IFXMIPS_SSC_SFCON);
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info->frm_opts.FrameEnable = (tmp & IFX_SSC_SFCON_SF_ENABLE) > 0;
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info->frm_opts.DataLength = (tmp & IFX_SSC_SFCON_DATA_LENGTH_MASK) >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET;
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info->frm_opts.PauseLength = (tmp & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET;
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@ -686,7 +686,7 @@ ifx_ssc_frm_control_set (struct ifx_ssc_port *info)
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return -EINVAL;
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// read interrupt bits (they're not changed here)
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tmp = readl(IFXMIPS_SSC_SFCON) &
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tmp = ifxmips_r32(IFXMIPS_SSC_SFCON) &
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(IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE | IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE);
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// set all values with respect to it's bit position (for data and pause
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@ -698,7 +698,7 @@ ifx_ssc_frm_control_set (struct ifx_ssc_port *info)
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tmp |= info->frm_opts.FrameEnable * IFX_SSC_SFCON_SF_ENABLE;
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tmp |= info->frm_opts.StopAfterPause * IFX_SSC_SFCON_STOP_AFTER_PAUSE;
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writel(tmp, IFXMIPS_SSC_SFCON);
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ifxmips_w32(tmp, IFXMIPS_SSC_SFCON);
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return 0;
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}
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@ -711,12 +711,12 @@ ifx_ssc_rxtx_mode_set (struct ifx_ssc_port *info, unsigned int val)
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if (!(info) || (val & ~(IFX_SSC_MODE_MASK)))
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return -EINVAL;
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if ((readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_BUSY)
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|| (readl(IFXMIPS_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK))
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if ((ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_BUSY)
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|| (ifxmips_r32(IFXMIPS_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK))
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return -EBUSY;
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tmp = (readl(IFXMIPS_SSC_CON) & ~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF)) | (val);
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writel(tmp, IFXMIPS_SSC_SFCON);
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tmp = (ifxmips_r32(IFXMIPS_SSC_CON) & ~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF)) | (val);
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ifxmips_w32(tmp, IFXMIPS_SSC_SFCON);
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info->opts.modeRxTx = val;
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return 0;
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@ -766,20 +766,20 @@ ifx_ssc_sethwopts (struct ifx_ssc_port *info)
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local_irq_save (flags);
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writel(bits, IFXMIPS_SSC_CON);
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writel((info->opts.gpoCs << IFX_SSC_GPOCON_ISCSB0_POS) |
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ifxmips_w32(bits, IFXMIPS_SSC_CON);
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ifxmips_w32((info->opts.gpoCs << IFX_SSC_GPOCON_ISCSB0_POS) |
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(info->opts.gpoInv << IFX_SSC_GPOCON_INVOUT0_POS), IFXMIPS_SSC_GPOCON);
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writel(info->opts.gpoCs << IFX_SSC_WHBGPOSTAT_SETOUT0_POS, IFXMIPS_SSC_WHBGPOSTAT);
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ifxmips_w32(info->opts.gpoCs << IFX_SSC_WHBGPOSTAT_SETOUT0_POS, IFXMIPS_SSC_WHBGPOSTAT);
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//master mode
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if (opts->masterSelect)
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writel(IFX_SSC_WHBSTATE_SET_MASTER_SELECT, IFXMIPS_SSC_WHBSTATE);
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ifxmips_w32(IFX_SSC_WHBSTATE_SET_MASTER_SELECT, IFXMIPS_SSC_WHBSTATE);
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else
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writel(IFX_SSC_WHBSTATE_CLR_MASTER_SELECT, IFXMIPS_SSC_WHBSTATE);
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ifxmips_w32(IFX_SSC_WHBSTATE_CLR_MASTER_SELECT, IFXMIPS_SSC_WHBSTATE);
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// init serial framing
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writel(0, IFXMIPS_SSC_SFCON);
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ifxmips_w32(0, IFXMIPS_SSC_SFCON);
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/* set up the port pins */
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//check for general requirements to switch (external) pad/pin characteristics
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/* TODO: P0.9 SPI_CS4, P0.10 SPI_CS5, P 0.11 SPI_CS6, because of ASC0 */
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@ -823,23 +823,23 @@ ifx_ssc_set_baud (struct ifx_ssc_port *info, unsigned int baud)
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local_irq_save (flags);
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enabled = (readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
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writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
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enabled = (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
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ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
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br = (((ifx_ssc_clock >> 1) + baud / 2) / baud) - 1;
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wmb();
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if (br > 0xffff || ((br == 0) &&
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((readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_MASTER) == 0))) {
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((ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_MASTER) == 0))) {
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local_irq_restore (flags);
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printk ("%s: invalid baudrate %u\n", __func__, baud);
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return -EINVAL;
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}
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writel(br, IFXMIPS_SSC_BR);
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ifxmips_w32(br, IFXMIPS_SSC_BR);
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if (enabled)
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writel(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
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ifxmips_w32(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
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local_irq_restore(flags);
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@ -853,8 +853,8 @@ ifx_ssc_hwinit (struct ifx_ssc_port *info)
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|
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unsigned long flags;
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|
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bool enabled;
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|
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enabled = (readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
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|
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writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
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enabled = (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
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ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
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|
|
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|
|
if (ifx_ssc_sethwopts (info) < 0)
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|
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{
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|
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@ -871,14 +871,14 @@ ifx_ssc_hwinit (struct ifx_ssc_port *info)
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|
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local_irq_save (flags);
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/* TX FIFO */
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writel((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_TXFCON);
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|
|
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ifxmips_w32((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_TXFCON);
|
|
|
|
|
/* RX FIFO */
|
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|
|
writel((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_RXFCON);
|
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|
|
ifxmips_w32((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_RXFCON);
|
|
|
|
|
|
|
|
|
|
local_irq_restore (flags);
|
|
|
|
|
|
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|
|
if (enabled)
|
|
|
|
|
writel(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
|
|
|
|
|
ifxmips_w32(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
@ -926,7 +926,7 @@ ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigne
|
|
|
|
|
/* if the buffers are not empty then the port is */
|
|
|
|
|
/* busy and we shouldn't change things on-the-fly! */
|
|
|
|
|
if (!info->txbuf || !info->rxbuf ||
|
|
|
|
|
(readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_BUSY)) {
|
|
|
|
|
(ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_BUSY)) {
|
|
|
|
|
ret_val = -EBUSY;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
@ -967,7 +967,7 @@ ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigne
|
|
|
|
|
ret_val = ifx_ssc_rxtx_mode_set (info, tmp);
|
|
|
|
|
break;
|
|
|
|
|
case IFX_SSC_RXTX_MODE_GET:
|
|
|
|
|
tmp = readl(IFXMIPS_SSC_CON) &
|
|
|
|
|
tmp = ifxmips_r32(IFXMIPS_SSC_CON) &
|
|
|
|
|
(~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF));
|
|
|
|
|
if (from_kernel)
|
|
|
|
|
*((unsigned int *) data) = tmp;
|
|
|
|
@ -991,7 +991,7 @@ ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigne
|
|
|
|
|
if (tmp > IFX_SSC_MAX_GPO_OUT)
|
|
|
|
|
ret_val = -EINVAL;
|
|
|
|
|
else
|
|
|
|
|
writel(1 << (tmp + IFX_SSC_WHBGPOSTAT_SETOUT0_POS),
|
|
|
|
|
ifxmips_w32(1 << (tmp + IFX_SSC_WHBGPOSTAT_SETOUT0_POS),
|
|
|
|
|
IFXMIPS_SSC_WHBGPOSTAT);
|
|
|
|
|
break;
|
|
|
|
|
case IFX_SSC_GPO_OUT_CLR:
|
|
|
|
@ -1004,12 +1004,12 @@ ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigne
|
|
|
|
|
if (tmp > IFX_SSC_MAX_GPO_OUT)
|
|
|
|
|
ret_val = -EINVAL;
|
|
|
|
|
else {
|
|
|
|
|
writel(1 << (tmp + IFX_SSC_WHBGPOSTAT_CLROUT0_POS),
|
|
|
|
|
ifxmips_w32(1 << (tmp + IFX_SSC_WHBGPOSTAT_CLROUT0_POS),
|
|
|
|
|
IFXMIPS_SSC_WHBGPOSTAT);
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case IFX_SSC_GPO_OUT_GET:
|
|
|
|
|
tmp = readl(IFXMIPS_SSC_GPOSTAT);
|
|
|
|
|
tmp = ifxmips_r32(IFXMIPS_SSC_GPOSTAT);
|
|
|
|
|
if (from_kernel)
|
|
|
|
|
*((unsigned int *) data) = tmp;
|
|
|
|
|
else if (copy_to_user ((void *) data,
|
|
|
|
@ -1053,7 +1053,7 @@ ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigne
|
|
|
|
|
/* if the buffers are not empty then the port is */
|
|
|
|
|
/* busy and we shouldn't change things on-the-fly! */
|
|
|
|
|
if (!info->txbuf || !info->rxbuf ||
|
|
|
|
|
(readl(IFXMIPS_SSC_STATE)
|
|
|
|
|
(ifxmips_r32(IFXMIPS_SSC_STATE)
|
|
|
|
|
& IFX_SSC_STATE_BUSY)) {
|
|
|
|
|
ret_val = -EBUSY;
|
|
|
|
|
break;
|
|
|
|
@ -1165,14 +1165,14 @@ ifx_ssc_init (void)
|
|
|
|
|
info->mapbase = IFXMIPS_SSC_BASE_ADDR;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
writel(IFX_SSC_DEF_RMC << IFX_CLC_RUN_DIVIDER_OFFSET, IFXMIPS_SSC_CLC);
|
|
|
|
|
ifxmips_w32(IFX_SSC_DEF_RMC << IFX_CLC_RUN_DIVIDER_OFFSET, IFXMIPS_SSC_CLC);
|
|
|
|
|
|
|
|
|
|
init_waitqueue_head (&info->rwait);
|
|
|
|
|
|
|
|
|
|
local_irq_save (flags);
|
|
|
|
|
|
|
|
|
|
// init serial framing register
|
|
|
|
|
writel(IFX_SSC_DEF_SFCON, IFXMIPS_SSC_SFCON);
|
|
|
|
|
ifxmips_w32(IFX_SSC_DEF_SFCON, IFXMIPS_SSC_SFCON);
|
|
|
|
|
|
|
|
|
|
ret_val = request_irq(IFXMIPS_SSC_TIR, ifx_ssc_tx_int, IRQF_DISABLED, "ifx_ssc_tx", info);
|
|
|
|
|
if (ret_val)
|
|
|
|
@ -1197,7 +1197,7 @@ ifx_ssc_init (void)
|
|
|
|
|
local_irq_restore (flags);
|
|
|
|
|
goto irqerr;
|
|
|
|
|
}
|
|
|
|
|
writel(IFX_SSC_DEF_IRNEN, IFXMIPS_SSC_IRN);
|
|
|
|
|
ifxmips_w32(IFX_SSC_DEF_IRNEN, IFXMIPS_SSC_IRN);
|
|
|
|
|
|
|
|
|
|
//enable_irq(IFXMIPS_SSC_TIR);
|
|
|
|
|
//enable_irq(IFXMIPS_SSC_RIR);
|
|
|
|
@ -1233,7 +1233,7 @@ ifx_ssc_cleanup_module (void)
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < PORT_CNT; i++) {
|
|
|
|
|
writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
|
|
|
|
|
ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
|
|
|
|
|
free_irq(IFXMIPS_SSC_TIR, &isp[i]);
|
|
|
|
|
free_irq(IFXMIPS_SSC_RIR, &isp[i]);
|
|
|
|
|
free_irq(IFXMIPS_SSC_EIR, &isp[i]);
|
|
|
|
|