kernel: refresh patches against 3.9-rc6
Signed-off-by: Florian Fainelli <florian@openwrt.org> SVN-Revision: 36297v19.07.3_mercusys_ac12_duma
Florian Fainelli
11 years ago
parent
c3366cd164
commit
915969ff2c
@ -1,368 +0,0 @@
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From f9b4e05597e636a550af8392e80b15f79d9f9e11 Mon Sep 17 00:00:00 2001
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From: Florian Fainelli <florian@openwrt.org>
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Date: Thu, 14 Mar 2013 14:07:20 +0100
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Subject: [PATCH] MIPS: fix code generation for non-DSP capable CPUs
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Commit 32a7ede (MIPS: dsp: Add assembler support for DSP ASEs) has
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enabled the use of DSP ASE specific instructions such as rddsp and wrdsp
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under the idea that all code path that will make use of these two
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instructions are properly checking for cpu_has_dsp to ensure that the
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particular CPU we are running on *actually* supports DSP ASE.
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This commit actually causes the following oops on QEMU Malta emulating a
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MIPS 24Kc without the DSP ASE implemented:
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[ 7.960000] Reserved instruction in kernel
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[ 7.960000] Cpu 0
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[ 7.960000] $ 0 : 00000000 00000000 00000014 00000005
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[ 7.960000] $ 4 : 8fc2de48 00000001 00000000 8f59ddb0
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[ 7.960000] $ 8 : 8f5ceec4 00000018 00000c00 00800000
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[ 7.960000] $12 : 00000100 00000200 00000000 00457b84
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[ 7.960000] $16 : 00000000 8fc2ba78 8f4ec980 00000001
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[ 7.960000] $20 : 80418f90 00000000 00000000 000002dd
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[ 7.960000] $24 : 0000009c 7730d7b8
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[ 7.960000] $28 : 8f59c000 8f59dd38 00000001 80104248
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[ 7.960000] Hi : 0000001d
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[ 7.960000] Lo : 0000000b
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[ 7.960000] epc : 801041ec thread_saved_pc+0x2c/0x38
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[ 7.960000] Not tainted
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[ 7.960000] ra : 80104248 get_wchan+0x48/0xac
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[ 7.960000] Status: 1000b703 KERNEL EXL IE
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[ 7.960000] Cause : 10800028
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[ 7.960000] PrId : 00019300 (MIPS 24Kc)
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[ 7.960000] Modules linked in:
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[ 7.960000] Process killall (pid: 1574, threadinfo=8f59c000,
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task=8fd14558, tls=773aa440)
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[ 7.960000] Stack : 8fc2ba78 8012b008 0000000c 0000001d 00000000
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00000000 8f58a380
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8f58a380 8fc2ba78 80202668 8f59de78 8f468600 8f59de28
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801b2a3c 8f59df00 8f98ba20 74696e69
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8f468600 8f59de28 801b7308 0081c007 00000000 00000000
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00000000 00000000 00000000 00000000
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00000000 8fc2bbb4 00000001 0000001d 0000000b 77f038cc
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7fe80648 ffffffff ffffffff 00000000
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00000001 0016e000 00000000 ...
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[ 7.960000] Call Trace:
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[ 7.960000] [<801041ec>] thread_saved_pc+0x2c/0x38
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[ 7.960000] [<80104248>] get_wchan+0x48/0xac
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The disassembly of thread_saved_pc points to the following:
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000006d0 <thread_saved_pc>:
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6d0: 8c820208 lw v0,520(a0)
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6d4: 3c030000 lui v1,0x0
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6d8: 24630000 addiu v1,v1,0
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6dc: 10430008 beq v0,v1,700 <thread_saved_pc+0x30>
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6e0: 00000000 nop
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6e4: 3c020000 lui v0,0x0
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6e8: 8c43000c lw v1,12(v0)
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6ec: 04620004 bltzl v1,700 <thread_saved_pc+0x30>
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6f0: 00001021 move v0,zero
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6f4: 8c840200 lw a0,512(a0)
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6f8: 00031080 sll v0,v1,0x2
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6fc: 7c44100a lwx v0,a0(v0) <------------
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700: 03e00008 jr ra
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704: 00000000 nop
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If we specifically disable -mdsp/-mdspr2 for arch/mips/kernel/process.o,
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we get the following (non-crashing) assembly:
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00000708 <thread_saved_pc>:
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708: 8c820208 lw v0,520(a0)
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70c: 3c030000 lui v1,0x0
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710: 24630000 addiu v1,v1,0
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714: 10430009 beq v0,v1,73c <thread_saved_pc+0x34>
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718: 00000000 nop
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71c: 3c020000 lui v0,0x0
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720: 8c42000c lw v0,12(v0)
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724: 04420005 bltzl v0,73c <thread_saved_pc+0x34>
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728: 00001021 move v0,zero
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72c: 8c830200 lw v1,512(a0)
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730: 00021080 sll v0,v0,0x2
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734: 00431021 addu v0,v0,v1
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738: 8c420000 lw v0,0(v0)
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73c: 03e00008 jr ra
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740: 00000000 nop
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The specific line that leads a different assembly being produced is:
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unsigned long thread_saved_pc(struct task_struct *tsk)
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...
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return ((unsigned long *)t->reg29)[schedule_mfi.pc_offset]; <---
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The problem here is that the compiler was given the right to use DSP
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instructions with the -mdsp / -mdspr2 command-line switches and
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performed some optimization for us and used DSP ASE instructions where
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we are not checking that the running CPU actually supports DSP ASE.
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This patch fixes the issue by partially reverting commit 32a7ede for
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arch/mips/kernel/Makefile in order to remove the -mdsp / -mdspr2
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compiler command-line switches such that we are now guaranteed that the
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compiler will not optimize using DSP ASE reserved instructions. We also
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need to fixup the rddsp/wrdsp and m{t,h}{hi,lo}{0,1,2,3} macros in
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arch/mips/include/asm/mipsregs.h to tell the assembler that we are going
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to explicitely use DSP ASE reserved instructions.
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Signed-off-by: Florian Fainelli <florian@openwrt.org>
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---
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Ralf, John,
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This should be part of your 3.9-rc3 pull request if I may ;)
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arch/mips/include/asm/mipsregs.h | 209 ++++++++++++++++++++++++++++++++++----
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arch/mips/kernel/Makefile | 14 ---
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2 files changed, 190 insertions(+), 33 deletions(-)
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--- a/arch/mips/include/asm/mipsregs.h
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+++ b/arch/mips/include/asm/mipsregs.h
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@@ -1166,7 +1166,10 @@ do { \
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unsigned int __dspctl; \
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\
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__asm__ __volatile__( \
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+ " .set push \n" \
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+ " .set dsp \n" \
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" rddsp %0, %x1 \n" \
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+ " .set pop \n" \
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: "=r" (__dspctl) \
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: "i" (mask)); \
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__dspctl; \
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@@ -1175,30 +1178,198 @@ do { \
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#define wrdsp(val, mask) \
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do { \
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__asm__ __volatile__( \
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+ " .set push \n" \
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+ " .set dsp \n" \
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" wrdsp %0, %x1 \n" \
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+ " .set pop \n" \
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: \
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: "r" (val), "i" (mask)); \
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} while (0)
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-#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
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-#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
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-#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
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-#define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
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-
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-#define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
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-#define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
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-#define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
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-#define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
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-
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-#define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
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-#define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
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-#define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
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-#define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
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-
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-#define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
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-#define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
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-#define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
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-#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
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+#define mflo0() \
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+({ \
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+ long mflo0; \
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+ __asm__( \
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+ " .set push \n" \
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+ " .set dsp \n" \
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+ " mflo %0, $ac0 \n" \
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+ " .set pop \n" \
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+ : "=r" (mflo0)); \
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+ mflo0; \
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+})
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+
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+#define mflo1() \
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+({ \
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+ long mflo1; \
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+ __asm__( \
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+ " .set push \n" \
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+ " .set dsp \n" \
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+ " mflo %0, $ac1 \n" \
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+ " .set pop \n" \
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+ : "=r" (mflo1)); \
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+ mflo1; \
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+})
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+
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+#define mflo2() \
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+({ \
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+ long mflo2; \
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+ __asm__( \
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+ " .set push \n" \
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+ " .set dsp \n" \
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+ " mflo %0, $ac2 \n" \
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+ " .set pop \n" \
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+ : "=r" (mflo2)); \
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+ mflo2; \
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+})
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+
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+#define mflo3() \
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+({ \
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+ long mflo3; \
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+ __asm__( \
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+ " .set push \n" \
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+ " .set dsp \n" \
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+ " mflo %0, $ac3 \n" \
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+ " .set pop \n" \
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+ : "=r" (mflo3)); \
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+ mflo3; \
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+})
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+
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+#define mfhi0() \
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+({ \
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+ long mfhi0; \
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+ __asm__( \
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+ " .set push \n" \
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+ " .set dsp \n" \
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+ " mfhi %0, $ac0 \n" \
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+ " .set pop \n" \
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+ : "=r" (mfhi0)); \
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+ mfhi0; \
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+})
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+
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+#define mfhi1() \
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+({ \
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+ long mfhi1; \
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+ __asm__( \
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+ " .set push \n" \
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+ " .set dsp \n" \
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+ " mfhi %0, $ac1 \n" \
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+ " .set pop \n" \
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+ : "=r" (mfhi1)); \
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+ mfhi1; \
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+})
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+
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+#define mfhi2() \
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+({ \
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+ long mfhi2; \
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+ __asm__( \
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+ " .set push \n" \
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+ " .set dsp \n" \
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+ " mfhi %0, $ac2 \n" \
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+ " .set pop \n" \
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+ : "=r" (mfhi2)); \
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+ mfhi2; \
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+})
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+
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+#define mfhi3() \
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+({ \
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+ long mfhi3; \
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+ __asm__( \
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+ " .set push \n" \
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+ " .set dsp \n" \
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+ " mfhi %0, $ac3 \n" \
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+ " .set pop \n" \
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+ : "=r" (mfhi3)); \
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+ mfhi3; \
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+})
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+
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+
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+#define mtlo0(x) \
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+({ \
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+ __asm__( \
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+ " .set push \n" \
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+ " .set dsp \n" \
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+ " mtlo %0, $ac0 \n" \
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+ " .set pop \n" \
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+ : \
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+ : "r" (x)); \
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+})
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+
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+#define mtlo1(x) \
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+({ \
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+ __asm__( \
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+ " .set push \n" \
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+ " .set dsp \n" \
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+ " mtlo %0, $ac1 \n" \
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+ " .set pop \n" \
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+ : \
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+ : "r" (x)); \
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+})
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+
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+#define mtlo2(x) \
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+({ \
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+ __asm__( \
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+ " .set push \n" \
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+ " .set dsp \n" \
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+ " mtlo %0, $ac2 \n" \
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+ " .set pop \n" \
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+ : \
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+ : "r" (x)); \
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+})
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+
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+#define mtlo3(x) \
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+({ \
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+ __asm__( \
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+ " .set push \n" \
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+ " .set dsp \n" \
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+ " mtlo %0, $ac3 \n" \
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+ " .set pop \n" \
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+ : \
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+ : "r" (x)); \
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+})
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+
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+#define mthi0(x) \
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+({ \
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+ __asm__( \
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+ " .set push \n" \
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+ " .set dsp \n" \
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+ " mthi %0, $ac0 \n" \
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+ " .set pop \n" \
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+ : \
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+ : "r" (x)); \
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+})
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+
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+#define mthi1(x) \
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+({ \
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+ __asm__( \
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+ " .set push \n" \
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+ " .set dsp \n" \
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+ " mthi %0, $ac1 \n" \
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+ " .set pop \n" \
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+ : \
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+ : "r" (x)); \
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+})
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+
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+#define mthi2(x) \
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+({ \
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+ __asm__( \
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+ " .set push \n" \
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+ " .set dsp \n" \
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+ " mthi %0, $ac2 \n" \
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+ " .set pop \n" \
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+ : \
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+ : "r" (x)); \
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+})
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+
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+#define mthi3(x) \
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+({ \
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+ __asm__( \
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+ " .set push \n" \
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+ " .set dsp \n" \
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+ " mthi %0, $ac3 \n" \
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+ " .set pop \n" \
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+ : \
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+ : "r" (x)); \
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+})
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#else
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--- a/arch/mips/kernel/Makefile
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+++ b/arch/mips/kernel/Makefile
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@@ -109,20 +109,6 @@ obj-$(CONFIG_JUMP_LABEL) += jump_label.o
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ifeq ($(CONFIG_CPU_MIPSR2), y)
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CFLAGS_DSP = -DHAVE_AS_DSP
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-#
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-# Check if assembler supports DSP ASE
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-#
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-ifeq ($(call cc-option-yn,-mdsp), y)
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-CFLAGS_DSP += -mdsp
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-endif
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-
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-#
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-# Check if assembler supports DSP ASE Rev2
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-#
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-ifeq ($(call cc-option-yn,-mdspr2), y)
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-CFLAGS_DSP += -mdspr2
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-endif
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-
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CFLAGS_signal.o = $(CFLAGS_DSP)
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CFLAGS_signal32.o = $(CFLAGS_DSP)
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CFLAGS_process.o = $(CFLAGS_DSP)
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