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@ -61,15 +61,15 @@
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#define CHIP_ID_ID_SHIFT 8
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#define CHIP_ID_REV_MASK 0xff
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#define SYSTEM_CONFIG_CPUCLK_SHIFT 18
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#define SYSTEM_CONFIG_CPUCLK_MASK 0x1
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#define SYSTEM_CONFIG_CPUCLK_320 0x0
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#define SYSTEM_CONFIG_CPUCLK_384 0x1
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#define SYSTEM_CONFIG_SRAM_CS0_MODE_SHIFT 2
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#define SYSTEM_CONFIG_SRAM_CS0_MODE_MASK 0x3
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#define SYSTEM_CONFIG_SRAM_CS0_MODE_NORMAL 0
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#define SYSTEM_CONFIG_SRAM_CS0_MODE_WDT 1
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#define SYSTEM_CONFIG_SRAM_CS0_MODE_BTCOEX 2
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#define RT305X_SYSCFG_CPUCLK_SHIFT 18
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#define RT305X_SYSCFG_CPUCLK_MASK 0x1
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#define RT305X_SYSCFG_CPUCLK_LOW 0x0
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#define RT305X_SYSCFG_CPUCLK_HIGH 0x1
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#define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2
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#define RT305X_SYSCFG_SRAM_CS0_MODE_MASK 0x3
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#define RT305X_SYSCFG_SRAM_CS0_MODE_NORMAL 0
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#define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 1
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#define RT305X_SYSCFG_SRAM_CS0_MODE_BTCOEX 2
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#define RT305X_GPIO_MODE_I2C BIT(0)
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#define RT305X_GPIO_MODE_SPI BIT(1)
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