kernel: bump 4.14 to 4.14.98
Refreshed all patches. Remove upstreamed: - 100-arm-cns3xxx-fix-writing-to-wrong-PCI-registers-after.patch Altered patches: - 721-phy_packets.patch Compile-tested on: ar71xx, cns3xxx, imx6, x86_64 Runtime-tested on: ar71xx, cns3xxx, imx6 Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>v19.07.3_mercusys_ac12_duma
Koen Vandeputte
5 years ago
parent
34e80b5d3b
commit
89bf16ad50
@ -1,74 +0,0 @@
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From 03556dab1cb02d85b50d7be3ee3a3bac001f5991 Mon Sep 17 00:00:00 2001
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From: Koen Vandeputte <koen.vandeputte@ncentric.com>
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Date: Tue, 18 Dec 2018 12:14:06 +0100
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Subject: [PATCH] arm: cns3xxx: fix writing to wrong PCI registers after
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alignment
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Originally, cns3xxx used it's own functions for mapping, reading and writing registers.
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Commit 802b7c06adc7 ("ARM: cns3xxx: Convert PCI to use generic config accessors")
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removed the internal PCI config write function in favor of the generic one:
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cns3xxx_pci_write_config() --> pci_generic_config_write()
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cns3xxx_pci_write_config() expected aligned addresses, being produced by cns3xxx_pci_map_bus()
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while the generic one pci_generic_config_write() actually expects the real address
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as both the function and hardware are capable of byte-aligned writes.
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This currently leads to pci_generic_config_write() writing
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to the wrong registers on some ocasions.
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First issue seen due to this:
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- driver ath9k gets loaded
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- The driver wants to write value 0xA8 to register PCI_LATENCY_TIMER, located at 0x0D
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- cns3xxx_pci_map_bus() aligns the address to 0x0C
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- pci_generic_config_write() effectively writes 0xA8 into register 0x0C (CACHE_LINE_SIZE)
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This seems to cause some slight instability when certain PCI devices are used.
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Another issue example caused by this this is the PCI bus numbering,
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where the primary bus is higher than the secondary, which is impossible.
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Before:
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00:00.0 PCI bridge: Cavium, Inc. Device 3400 (rev 01) (prog-if 00 [Normal decode])
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Flags: bus master, fast devsel, latency 0, IRQ 255
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Bus: primary=02, secondary=01, subordinate=ff, sec-latency=0
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After fix:
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00:00.0 PCI bridge: Cavium, Inc. Device 3400 (rev 01) (prog-if 00 [Normal decode])
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Flags: bus master, fast devsel, latency 0, IRQ 255
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Bus: primary=00, secondary=01, subordinate=02, sec-latency=0
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And very likely some more ..
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Fix all by omitting the alignment being done in the mapping function.
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Fixes: 802b7c06adc7 ("ARM: cns3xxx: Convert PCI to use generic config accessors")
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Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
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CC: Arnd Bergmann <arnd@arndb.de>
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CC: Bjorn Helgaas <bhelgaas@google.com>
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CC: Krzysztof Halasa <khalasa@piap.pl>
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CC: Olof Johansson <olof@lixom.net>
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CC: Robin Leblon <robin.leblon@ncentric.com>
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CC: Rob Herring <robh@kernel.org>
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CC: Russell King <linux@armlinux.org.uk>
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CC: Tim Harvey <tharvey@gateworks.com>
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CC: stable@vger.kernel.org # v4.0+
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---
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arch/arm/mach-cns3xxx/pcie.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/arch/arm/mach-cns3xxx/pcie.c
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+++ b/arch/arm/mach-cns3xxx/pcie.c
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@@ -83,7 +83,7 @@ static void __iomem *cns3xxx_pci_map_bus
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} else /* remote PCI bus */
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base = cnspci->cfg1_regs + ((busno & 0xf) << 20);
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- return base + (where & 0xffc) + (devfn << 12);
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+ return base + where + (devfn << 12);
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}
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static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
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