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octeon: remove 2.6.30 support

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SVN-Revision: 31419
v19.07.3_mercusys_ac12_duma
Gabor Juhos 12 years ago
parent 26b3cdad1c
commit 884a4d47f0
21 changed files with 0 additions and 64036 deletions
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267
target/linux/octeon/config-2.6.30
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@ -1,267 +0,0 @@
# CONFIG_32BIT is not set
CONFIG_64BIT_PHYS_ADDR=y
CONFIG_64BIT=y
# CONFIG_ALTERA_PCIE_CHDMA is not set
# CONFIG_ANDROID_BINDER_IPC is not set
# CONFIG_ANDROID is not set
# CONFIG_ANDROID_LOGGER is not set
# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set
# CONFIG_ANDROID_RAM_CONSOLE is not set
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_ARCH_POPULATES_NODE_MAP=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SUPPORTS_MSI=y
CONFIG_ARCH_SUPPORTS_OPROFILE=y
# CONFIG_ARPD is not set
# CONFIG_B3DFG is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_BCM47XX is not set
# CONFIG_BINARY_PRINTF is not set
CONFIG_BINFMT_ELF32=y
CONFIG_BITREVERSE=y
CONFIG_BLOCK_COMPAT=y
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_CAVIUM_OCTEON_2ND_KERNEL is not set
CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=2
CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED=y
CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION=y
CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT=y
CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT=y
CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY=y
CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB=y
CONFIG_CAVIUM_OCTEON_LOCK_L2=y
CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD=y
# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
CONFIG_CAVIUM_OCTEON_SPECIFIC_OPTIONS=y
CONFIG_CEVT_R4K_LIB=y
CONFIG_CEVT_R4K=y
# CONFIG_CGROUP_SCHED is not set
CONFIG_CMDLINE="console=ttyS0,115200"
# CONFIG_COMEDI is not set
CONFIG_COMPAT_BRK=y
CONFIG_COMPAT=y
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_CPU_CAVIUM_OCTEON=y
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_CPU_HAS_SYNC=y
# CONFIG_CPU_LITTLE_ENDIAN is not set
# CONFIG_CPU_LOONGSON2 is not set
# CONFIG_CPU_MIPS32_R1 is not set
# CONFIG_CPU_MIPS32_R2 is not set
# CONFIG_CPU_MIPS64_R1 is not set
# CONFIG_CPU_MIPS64_R2 is not set
CONFIG_CPU_MIPSR2=y
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R10000 is not set
# CONFIG_CPU_R3000 is not set
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_R5000 is not set
# CONFIG_CPU_R5432 is not set
# CONFIG_CPU_R5500 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_RM9000 is not set
# CONFIG_CPU_SB1 is not set
CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_HIGHMEM=y
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_VR41XX is not set
CONFIG_CRAMFS=y
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_DEBUG_DRIVER is not set
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_KOBJECT is not set
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_SHIRQ is not set
# CONFIG_DEBUG_SLAB is not set
CONFIG_DEBUG_SPINLOCK_SLEEP=y
CONFIG_DEBUG_SPINLOCK=y
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_WRITECOUNT is not set
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DETECT_SOFTLOCKUP=y
CONFIG_DEVKMEM=y
CONFIG_DEVPORT=y
# CONFIG_DM9000 is not set
CONFIG_DMA_COHERENT=y
CONFIG_DNOTIFY=y
# CONFIG_DST is not set
CONFIG_EARLY_PRINTK=y
# CONFIG_ECHO is not set
CONFIG_ELF_CORE=y
CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_ET131X is not set
CONFIG_FAIR_GROUP_SCHED=y
# CONFIG_FAULT_INJECTION is not set
# CONFIG_FLATMEM_MANUAL is not set
CONFIG_FRAME_WARN=2048
# CONFIG_FW_LOADER is not set
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_FIND_LAST_BIT=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_GROUP_SCHED=y
# CONFIG_HAMRADIO is not set
CONFIG_HARDWARE_WATCHPOINTS=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_HAVE_IDE=y
CONFIG_HAVE_MEMORY_PRESENT=y
CONFIG_HAVE_MLOCKED_PAGE_BIT=y
CONFIG_HAVE_MLOCK=y
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_SYSCALL_WRAPPERS=y
# CONFIG_HECI is not set
# CONFIG_HIGH_RES_TIMERS is not set
CONFIG_HW_HAS_PCI=y
CONFIG_HW_RANDOM_OCTEON=y
CONFIG_HW_RANDOM=y
# CONFIG_HZ_100 is not set
CONFIG_HZ=250
CONFIG_HZ_250=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_INOTIFY_USER=y
CONFIG_INOTIFY=y
CONFIG_IRQ_CPU_OCTEON=y
CONFIG_IRQ_CPU=y
CONFIG_IRQ_PER_CPU=y
# CONFIG_KALLSYMS_ALL is not set
CONFIG_KALLSYMS=y
CONFIG_KEXEC=y
# CONFIG_KGDB is not set
CONFIG_LEGACY_PTY_COUNT=256
CONFIG_LEGACY_PTYS=y
# CONFIG_LEMOTE_FULONG is not set
CONFIG_LOCK_KERNEL=y
# CONFIG_LOCK_STAT is not set
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
# CONFIG_MACH_TX39XX is not set
# CONFIG_MACH_TX49XX is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_ME4000 is not set
# CONFIG_MEILHAUS is not set
# CONFIG_MIKROTIK_RB532 is not set
CONFIG_MIPS32_COMPAT=y
CONFIG_MIPS32_N32=y
CONFIG_MIPS32_O32=y
# CONFIG_MIPS_COBALT is not set
CONFIG_MIPS_L1_CACHE_SHIFT=7
# CONFIG_MIPS_MACHINE is not set
# CONFIG_MIPS_MALTA is not set
CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_SIM is not set
CONFIG_MIPS=y
# CONFIG_MISC_DEVICES is not set
# CONFIG_MTD_CFI_INTELEXT is not set
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_MTD_PHYSMAP=y
# CONFIG_NETWORK_FILESYSTEMS is not set
# CONFIG_NO_IOPORT is not set
CONFIG_NR_CPUS=16
CONFIG_NR_CPUS_DEFAULT_16=y
# CONFIG_NXP_STB220 is not set
# CONFIG_NXP_STB225 is not set
CONFIG_OCTEON_ETHERNET=y
CONFIG_OCTEON_MGMT=y
CONFIG_PAGEFLAGS_EXTENDED=y
# CONFIG_PAGE_POISONING is not set
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_PCI=y
# CONFIG_PCI_DEBUG is not set
CONFIG_PCI_DOMAINS=y
CONFIG_PHYS_ADDR_T_64BIT=y
# CONFIG_PLAN9AUTH is not set
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
# CONFIG_POHMELFS is not set
CONFIG_POSIX_MQUEUE_SYSCTL=y
CONFIG_POSIX_MQUEUE=y
# CONFIG_PROBE_INITRD_HEADER is not set
CONFIG_PROC_PAGE_MONITOR=y
# CONFIG_PROVE_LOCKING is not set
# CONFIG_RCU_TORTURE_TEST is not set
CONFIG_RELAY=y
# CONFIG_RT_GROUP_SCHED is not set
# CONFIG_RTL8187SE is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_RUNTIME_DEBUG is not set
CONFIG_SCHED_DEBUG=y
CONFIG_SCHED_OMIT_FRAME_POINTER=y
# CONFIG_SCHEDSTATS is not set
# CONFIG_SCSI_DMA is not set
CONFIG_SECCOMP=y
# CONFIG_SERIAL_8250_EXTENDED is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP28 is not set
# CONFIG_SGI_IP32 is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SLOW_WORK is not set
CONFIG_SMP=y
CONFIG_SPARSEMEM_MANUAL=y
CONFIG_SPARSEMEM_STATIC=y
CONFIG_SPARSEMEM=y
# CONFIG_STAGING_EXCLUDE_BUILD is not set
CONFIG_STAGING=y
CONFIG_STOP_MACHINE=y
CONFIG_SWAP_IO_SPACE=y
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYS_HAS_CPU_CAVIUM_OCTEON=y
CONFIG_SYS_HAS_EARLY_PRINTK=y
CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
CONFIG_SYS_SUPPORTS_HIGHMEM=y
CONFIG_SYS_SUPPORTS_SMP=y
CONFIG_SYSVIPC_COMPAT=y
# CONFIG_TC35815 is not set
# CONFIG_TIMER_STATS is not set
CONFIG_TRACING_SUPPORT=y
CONFIG_UNEVICTABLE_LRU=y
CONFIG_USB_SUPPORT=y
CONFIG_USE_GENERIC_SMP_HELPERS=y
CONFIG_USER_SCHED=y
# CONFIG_VLAN_8021Q is not set
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_WEAK_ORDERING=y
CONFIG_WEAK_REORDERING_BEYOND_LLSC=y
# CONFIG_WLAN_80211 is not set
CONFIG_ZONE_DMA_FLAG=0

25
target/linux/octeon/patches-2.6.30/001-handle_removal_h_constraint.patch
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@ -1,25 +0,0 @@
This is an incomplete proof of concept that I applied to be able to
build a 64 bit kernel with GCC-4.4. It doesn't handle the 32 bit case
or the R4000_WAR case.
Comments welcome.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/include/asm/compiler.h | 7 +++++++
2 files changed, 11 insertions(+), 0 deletions(-)
--- a/arch/mips/include/asm/compiler.h
+++ b/arch/mips/include/asm/compiler.h
@@ -16,4 +16,11 @@
#define GCC_REG_ACCUM "accum"
#endif
+#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 4)
+#define GCC_NO_H_CONSTRAINT
+#ifdef CONFIG_64BIT
+typedef unsigned int uint128_t __attribute__((mode(TI)));
+#endif
+#endif
+
#endif /* _ASM_COMPILER_H */

9383
target/linux/octeon/patches-2.6.30/002-register_defs_pci.patch
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5002
target/linux/octeon/patches-2.6.30/003_pci_pcie_support.patch
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223
target/linux/octeon/patches-2.6.30/004-named_alloc_function.patch
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@ -1,223 +0,0 @@
The MGMT ethernet driver uses these new functions.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/cavium-octeon/executive/cvmx-bootmem.c | 101 ++++++++++++++++++++++
arch/mips/include/asm/octeon/cvmx-bootmem.h | 85 ++++++++++++++++++
2 files changed, 186 insertions(+), 0 deletions(-)
--- a/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
@@ -97,6 +97,32 @@ void *cvmx_bootmem_alloc(uint64_t size,
return cvmx_bootmem_alloc_range(size, alignment, 0, 0);
}
+void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
+ uint64_t max_addr, uint64_t align,
+ char *name)
+{
+ int64_t addr;
+
+ addr = cvmx_bootmem_phy_named_block_alloc(size, min_addr, max_addr,
+ align, name, 0);
+ if (addr >= 0)
+ return cvmx_phys_to_ptr(addr);
+ else
+ return NULL;
+}
+
+void *cvmx_bootmem_alloc_named_address(uint64_t size, uint64_t address,
+ char *name)
+{
+ return cvmx_bootmem_alloc_named_range(size, address, address + size,
+ 0, name);
+}
+
+void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment, char *name)
+{
+ return cvmx_bootmem_alloc_named_range(size, 0, 0, alignment, name);
+}
+
int cvmx_bootmem_free_named(char *name)
{
return cvmx_bootmem_phy_named_block_free(name, 0);
@@ -584,3 +610,78 @@ int cvmx_bootmem_phy_named_block_free(ch
cvmx_bootmem_unlock();
return named_block_ptr != NULL; /* 0 on failure, 1 on success */
}
+
+int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr,
+ uint64_t max_addr,
+ uint64_t alignment,
+ char *name,
+ uint32_t flags)
+{
+ int64_t addr_allocated;
+ struct cvmx_bootmem_named_block_desc *named_block_desc_ptr;
+
+#ifdef DEBUG
+ cvmx_dprintf("cvmx_bootmem_phy_named_block_alloc: size: 0x%llx, min: "
+ "0x%llx, max: 0x%llx, align: 0x%llx, name: %s\n",
+ (unsigned long long)size,
+ (unsigned long long)min_addr,
+ (unsigned long long)max_addr,
+ (unsigned long long)alignment,
+ name);
+#endif
+ if (cvmx_bootmem_desc->major_version != 3) {
+ cvmx_dprintf("ERROR: Incompatible bootmem descriptor version: "
+ "%d.%d at addr: %p\n",
+ (int)cvmx_bootmem_desc->major_version,
+ (int)cvmx_bootmem_desc->minor_version,
+ cvmx_bootmem_desc);
+ return -1;
+ }
+
+ /*
+ * Take lock here, as name lookup/block alloc/name add need to
+ * be atomic.
+ */
+ if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+ cvmx_spinlock_lock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+
+ /* Get pointer to first available named block descriptor */
+ named_block_desc_ptr =
+ cvmx_bootmem_phy_named_block_find(NULL,
+ flags | CVMX_BOOTMEM_FLAG_NO_LOCKING);
+
+ /*
+ * Check to see if name already in use, return error if name
+ * not available or no more room for blocks.
+ */
+ if (cvmx_bootmem_phy_named_block_find(name,
+ flags | CVMX_BOOTMEM_FLAG_NO_LOCKING) || !named_block_desc_ptr) {
+ if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+ cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+ return -1;
+ }
+
+
+ /*
+ * Round size up to mult of minimum alignment bytes We need
+ * the actual size allocated to allow for blocks to be
+ * coallesced when they are freed. The alloc routine does the
+ * same rounding up on all allocations.
+ */
+ size = __ALIGN_MASK(size, (CVMX_BOOTMEM_ALIGNMENT_SIZE - 1));
+
+ addr_allocated = cvmx_bootmem_phy_alloc(size, min_addr, max_addr,
+ alignment,
+ flags | CVMX_BOOTMEM_FLAG_NO_LOCKING);
+ if (addr_allocated >= 0) {
+ named_block_desc_ptr->base_addr = addr_allocated;
+ named_block_desc_ptr->size = size;
+ strncpy(named_block_desc_ptr->name, name,
+ cvmx_bootmem_desc->named_block_name_len);
+ named_block_desc_ptr->name[cvmx_bootmem_desc->named_block_name_len - 1] = 0;
+ }
+
+ if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+ cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+ return addr_allocated;
+}
--- a/arch/mips/include/asm/octeon/cvmx-bootmem.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootmem.h
@@ -183,6 +183,64 @@ extern void *cvmx_bootmem_alloc_range(ui
* Returns 0 on failure,
* !0 on success
*/
+
+
+/**
+ * Allocate a block of memory from the free list that was passed
+ * to the application by the bootloader, and assign it a name in the
+ * global named block table. (part of the cvmx_bootmem_descriptor_t structure)
+ * Named blocks can later be freed.
+ *
+ * @size: Size in bytes of block to allocate
+ * @alignment: Alignment required - must be power of 2
+ * @name: name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes
+ *
+ * Returns a pointer to block of memory, NULL on error
+ */
+extern void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment,
+ char *name);
+
+
+
+/**
+ * Allocate a block of memory from the free list that was passed
+ * to the application by the bootloader, and assign it a name in the
+ * global named block table. (part of the cvmx_bootmem_descriptor_t structure)
+ * Named blocks can later be freed.
+ *
+ * @size: Size in bytes of block to allocate
+ * @address: Physical address to allocate memory at. If this
+ * memory is not available, the allocation fails.
+ * @name: name of block - must be less than CVMX_BOOTMEM_NAME_LEN
+ * bytes
+ *
+ * Returns a pointer to block of memory, NULL on error
+ */
+extern void *cvmx_bootmem_alloc_named_address(uint64_t size, uint64_t address,
+ char *name);
+
+
+
+/**
+ * Allocate a block of memory from a specific range of the free list
+ * that was passed to the application by the bootloader, and assign it
+ * a name in the global named block table. (part of the
+ * cvmx_bootmem_descriptor_t structure) Named blocks can later be
+ * freed. If request cannot be satisfied within the address range
+ * specified, NULL is returned
+ *
+ * @size: Size in bytes of block to allocate
+ * @min_addr: minimum address of range
+ * @max_addr: maximum address of range
+ * @align: Alignment of memory to be allocated. (must be a power of 2)
+ * @name: name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes
+ *
+ * Returns a pointer to block of memory, NULL on error
+ */
+extern void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
+ uint64_t max_addr, uint64_t align,
+ char *name);
+
extern int cvmx_bootmem_free_named(char *name);
/**
@@ -224,6 +282,33 @@ int64_t cvmx_bootmem_phy_alloc(uint64_t
uint32_t flags);
/**
+ * Allocates a named block of physical memory from the free list, at
+ * (optional) requested address and alignment.
+ *
+ * @param size size of region to allocate. All requests are rounded
+ * up to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE
+ * bytes size
+ * @param min_addr Minimum address that block can occupy.
+ * @param max_addr Specifies the maximum address_min (inclusive) that
+ * the allocation can use.
+ * @param alignment Requested alignment of the block. If this
+ * alignment cannot be met, the allocation fails.
+ * This must be a power of 2. (Note: Alignment of
+ * CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and
+ * internally enforced. Requested alignments of less
+ * than CVMX_BOOTMEM_ALIGNMENT_SIZE are set to
+ * CVMX_BOOTMEM_ALIGNMENT_SIZE.)
+ * @param name name to assign to named block
+ * @param flags Flags to control options for the allocation.
+ *
+ * @return physical address of block allocated, or -1 on failure
+ */
+int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr,
+ uint64_t max_addr,
+ uint64_t alignment,
+ char *name, uint32_t flags);
+
+/**
* Finds a named memory block by name.
* Also used for finding an unused entry in the named block table.
*

1642
target/linux/octeon/patches-2.6.30/005-register_defs_octeon_mgmt.patch
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2022
target/linux/octeon/patches-2.6.30/006-octeon_mgmt_driver.patch
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23
target/linux/octeon/patches-2.6.30/007-export_cvmx_sysinfo.patch
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@ -1,23 +0,0 @@
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/cavium-octeon/executive/cvmx-sysinfo.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
--- a/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
@@ -29,6 +29,7 @@
* This module provides system/board/application information obtained
* by the bootloader.
*/
+#include <linux/module.h>
#include <asm/octeon/cvmx.h>
#include <asm/octeon/cvmx-spinlock.h>
@@ -69,6 +70,7 @@ struct cvmx_sysinfo *cvmx_sysinfo_get(vo
{
return &(state.sysinfo);
}
+EXPORT_SYMBOL(cvmx_sysinfo_get);
/**
* This function is used in non-simple executive environments (such as

37
target/linux/octeon/patches-2.6.30/008-more_board_types_constraints.patch
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@ -1,37 +0,0 @@
The bootloader now uses additional board type constants. The
octeon-ethernet driver needs some of the new values.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/include/asm/octeon/cvmx-bootinfo.h | 13 +++++++++++++
1 files changed, 13 insertions(+), 0 deletions(-)
--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
@@ -157,6 +157,13 @@ enum cvmx_board_types_enum {
CVMX_BOARD_TYPE_NIC_XLE_4G = 21,
CVMX_BOARD_TYPE_EBT5600 = 22,
CVMX_BOARD_TYPE_EBH5201 = 23,
+ CVMX_BOARD_TYPE_EBT5200 = 24,
+ CVMX_BOARD_TYPE_CB5600 = 25,
+ CVMX_BOARD_TYPE_CB5601 = 26,
+ CVMX_BOARD_TYPE_CB5200 = 27,
+ /* Special 'generic' board type, supports many boards */
+ CVMX_BOARD_TYPE_GENERIC = 28,
+ CVMX_BOARD_TYPE_EBH5610 = 29,
CVMX_BOARD_TYPE_MAX,
/*
@@ -228,6 +235,12 @@ static inline const char *cvmx_board_typ
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_4G)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5600)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5201)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5200)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5600)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5601)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5200)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_GENERIC)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5610)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX)
/* Customer boards listed here */

51
target/linux/octeon/patches-2.6.30/009-more_chip_specific_feature_tests.patch
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@ -1,51 +0,0 @@
The octeon-ethernet driver needs to check for additional chip specific
features, we add them to the octeon_has_feature() framework.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/include/asm/octeon/octeon-feature.h | 27 +++++++++++++++++++++++++
1 files changed, 27 insertions(+), 0 deletions(-)
--- a/arch/mips/include/asm/octeon/octeon-feature.h
+++ b/arch/mips/include/asm/octeon/octeon-feature.h
@@ -57,6 +57,13 @@ enum octeon_feature {
OCTEON_FEATURE_RAID,
/* Octeon has a builtin USB */
OCTEON_FEATURE_USB,
+ /* Octeon IPD can run without using work queue entries */
+ OCTEON_FEATURE_NO_WPTR,
+ /* Octeon has DFA state machines */
+ OCTEON_FEATURE_DFA,
+ /* Octeon MDIO block supports clause 45 transactions for 10
+ * Gig support */
+ OCTEON_FEATURE_MDIO_CLAUSE_45,
};
static inline int cvmx_fuse_read(int fuse);
@@ -112,6 +119,26 @@ static inline int octeon_has_feature(enu
case OCTEON_FEATURE_USB:
return !(OCTEON_IS_MODEL(OCTEON_CN38XX)
|| OCTEON_IS_MODEL(OCTEON_CN58XX));
+ case OCTEON_FEATURE_NO_WPTR:
+ return (OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX))
+ && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
+ && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X);
+ case OCTEON_FEATURE_DFA:
+ if (!OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && !OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && !OCTEON_IS_MODEL(OCTEON_CN58XX))
+ return 0;
+ else if (OCTEON_IS_MODEL(OCTEON_CN3020))
+ return 0;
+ else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
+ return 1;
+ else
+ return !cvmx_fuse_read(120);
+ case OCTEON_FEATURE_MDIO_CLAUSE_45:
+ return !(OCTEON_IS_MODEL(OCTEON_CN3XXX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)
+ || OCTEON_IS_MODEL(OCTEON_CN50XX));
}
return 0;
}

21
target/linux/octeon/patches-2.6.30/010-export_erratum_function.patch
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@ -1,21 +0,0 @@
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
.../cavium-octeon/executive/cvmx-helper-errata.c | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c
@@ -33,6 +33,8 @@
* these functions directly.
*
*/
+#include <linux/module.h>
+
#include <asm/octeon/octeon.h>
#include <asm/octeon/cvmx-helper-util.h>
@@ -377,3 +379,4 @@ void __cvmx_helper_errata_qlm_disable_2n
}
cvmx_helper_qlm_jtag_update(qlm);
}
+EXPORT_SYMBOL(__cvmx_helper_errata_qlm_disable_2nd_order_cdr);

26533
target/linux/octeon/patches-2.6.30/011-octeon_ethernet_driver.patch
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File diff suppressed because it is too large Load Diff

26
target/linux/octeon/patches-2.6.30/012-hook_up_eth_driver.patch
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@ -1,26 +0,0 @@
The previous patch adds the driver files for octeon-ethernet. Here we
hook them up into the main kernel build system.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
drivers/staging/Kconfig | 2 ++
drivers/staging/Makefile | 1 +
2 files changed, 3 insertions(+), 0 deletions(-)
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@ -115,5 +115,7 @@ source "drivers/staging/line6/Kconfig"
source "drivers/staging/serqt_usb/Kconfig"
+source "drivers/staging/octeon/Kconfig"
+
endif # !STAGING_EXCLUDE_BUILD
endif # STAGING
--- a/drivers/staging/Makefile
+++ b/drivers/staging/Makefile
@@ -40,3 +40,4 @@ obj-$(CONFIG_PLAN9AUTH) += p9auth/
obj-$(CONFIG_HECI) += heci/
obj-$(CONFIG_LINE6_USB) += line6/
obj-$(CONFIG_USB_SERIAL_QUATECH_ESU100) += serqt_usb/
+obj-$(CONFIG_OCTEON_ETHERNET) += octeon/

85
target/linux/octeon/patches-2.6.30/013-compile_fixes.patch
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@ -1,85 +0,0 @@
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c
@@ -272,6 +272,7 @@ fix_ipd_exit:
*
* Returns Zero on success, negative on failure
*/
+#if 0
int __cvmx_helper_errata_asx_pass1(int interface, int port, int cpu_clock_hz)
{
/* Set hi water mark as per errata GMX-4 */
@@ -289,6 +290,7 @@ int __cvmx_helper_errata_asx_pass1(int i
cpu_clock_hz);
return 0;
}
+#endif
/**
* This function needs to be called on all Octeon chips with
--- a/arch/mips/include/asm/octeon/cvmx-helper-errata.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-errata.h
@@ -60,8 +60,8 @@ extern int __cvmx_helper_errata_fix_ipd_
*
* Returns Zero on success, negative on failure
*/
-extern int __cvmx_helper_errata_asx_pass1(int interface, int port,
- int cpu_clock_hz);
+//extern int __cvmx_helper_errata_asx_pass1(int interface, int port,
+// int cpu_clock_hz);
/**
* This function needs to be called on all Octeon chips with
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-util.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-util.c
@@ -356,6 +356,7 @@ int cvmx_helper_get_ipd_port(int interfa
*
* Returns Interface number
*/
+#if 0
int cvmx_helper_get_interface_num(int ipd_port)
{
if (ipd_port < 16)
@@ -372,6 +373,7 @@ int cvmx_helper_get_interface_num(int ip
return -1;
}
+#endif
/**
* Returns the interface index number for an IPD/PKO port
@@ -381,6 +383,7 @@ int cvmx_helper_get_interface_num(int ip
*
* Returns Interface index number
*/
+#if 0
int cvmx_helper_get_interface_index_num(int ipd_port)
{
if (ipd_port < 32)
@@ -395,6 +398,7 @@ int cvmx_helper_get_interface_index_num(
return -1;
}
+#endif
/**
* Initialize the internal QLM JTAG logic to allow programming
--- a/arch/mips/include/asm/octeon/cvmx-helper-util.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-util.h
@@ -205,7 +205,7 @@ static inline void cvmx_helper_free_pack
*
* Returns Interface number
*/
-extern int cvmx_helper_get_interface_num(int ipd_port);
+//extern int cvmx_helper_get_interface_num(int ipd_port);
/**
* Returns the interface index number for an IPD/PKO port
@@ -215,7 +215,7 @@ extern int cvmx_helper_get_interface_num
*
* Returns Interface index number
*/
-extern int cvmx_helper_get_interface_index_num(int ipd_port);
+//extern int cvmx_helper_get_interface_index_num(int ipd_port);
/**
* Initialize the internal QLM JTAG logic to allow programming

8
target/linux/octeon/patches-2.6.30/015-no_werror.patch
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@ -1,8 +0,0 @@
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -18,5 +18,3 @@ obj-$(CONFIG_PCI) +=
obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_PCI) += pcie.o
obj-$(CONFIG_PCI_MSI) += msi.o
-
-EXTRA_CFLAGS += -Werror

351
target/linux/octeon/patches-2.6.30/016-octeon_hw_rng.patch
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@ -1,351 +0,0 @@
From: David Daney <ddaney@caviumnetworks.com>
Date: Thu, 20 Aug 2009 21:10:22 +0000 (-0700)
Subject: MIPS: Octeon: Add hardware RNG platform device.
X-Git-Tag: linux-2.6.32-rc1~34
X-Git-Url: http://www.linux-mips.org/git?p=linux.git;a=commitdiff_plain;h=c691b963;hp=a68577bc6ce2b5e422cdb7a993b1c07cc410e02a
MIPS: Octeon: Add hardware RNG platform device.
Add a platform device for the Octeon Random Number Generator (RNG).
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
Index: linux-2.6.30.8/arch/mips/cavium-octeon/setup.c
===================================================================
--- linux-2.6.30.8.orig/arch/mips/cavium-octeon/setup.c 2009-09-24 17:28:02.000000000 +0200
+++ linux-2.6.30.8/arch/mips/cavium-octeon/setup.c 2009-10-08 13:10:09.000000000 +0200
@@ -32,6 +32,7 @@
#include <asm/time.h>
#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-rnm-defs.h>
#ifdef CONFIG_CAVIUM_DECODE_RSL
extern void cvmx_interrupt_rsl_decode(void);
@@ -925,3 +926,45 @@
return ret;
}
device_initcall(octeon_cf_device_init);
+
+/* Octeon Random Number Generator. */
+static int __init octeon_rng_device_init(void)
+{
+ struct platform_device *pd;
+ int ret = 0;
+
+ struct resource rng_resources[] = {
+ {
+ .flags = IORESOURCE_MEM,
+ .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
+ .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
+ }, {
+ .flags = IORESOURCE_MEM,
+ .start = cvmx_build_io_address(8, 0),
+ .end = cvmx_build_io_address(8, 0) + 0x7
+ }
+ };
+
+ pd = platform_device_alloc("octeon_rng", -1);
+ if (!pd) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ ret = platform_device_add_resources(pd, rng_resources,
+ ARRAY_SIZE(rng_resources));
+ if (ret)
+ goto fail;
+
+ ret = platform_device_add(pd);
+ if (ret)
+ goto fail;
+
+ return ret;
+fail:
+ platform_device_put(pd);
+
+out:
+ return ret;
+}
+device_initcall(octeon_rng_device_init);
Index: linux-2.6.30.8/arch/mips/include/asm/octeon/cvmx-rnm-defs.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-2.6.30.8/arch/mips/include/asm/octeon/cvmx-rnm-defs.h 2009-10-08 13:10:09.000000000 +0200
@@ -0,0 +1,88 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT. See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_RNM_DEFS_H__
+#define __CVMX_RNM_DEFS_H__
+
+#include <linux/types.h>
+
+#define CVMX_RNM_BIST_STATUS \
+ CVMX_ADD_IO_SEG(0x0001180040000008ull)
+#define CVMX_RNM_CTL_STATUS \
+ CVMX_ADD_IO_SEG(0x0001180040000000ull)
+
+union cvmx_rnm_bist_status {
+ uint64_t u64;
+ struct cvmx_rnm_bist_status_s {
+ uint64_t reserved_2_63:62;
+ uint64_t rrc:1;
+ uint64_t mem:1;
+ } s;
+ struct cvmx_rnm_bist_status_s cn30xx;
+ struct cvmx_rnm_bist_status_s cn31xx;
+ struct cvmx_rnm_bist_status_s cn38xx;
+ struct cvmx_rnm_bist_status_s cn38xxp2;
+ struct cvmx_rnm_bist_status_s cn50xx;
+ struct cvmx_rnm_bist_status_s cn52xx;
+ struct cvmx_rnm_bist_status_s cn52xxp1;
+ struct cvmx_rnm_bist_status_s cn56xx;
+ struct cvmx_rnm_bist_status_s cn56xxp1;
+ struct cvmx_rnm_bist_status_s cn58xx;
+ struct cvmx_rnm_bist_status_s cn58xxp1;
+};
+
+union cvmx_rnm_ctl_status {
+ uint64_t u64;
+ struct cvmx_rnm_ctl_status_s {
+ uint64_t reserved_9_63:55;
+ uint64_t ent_sel:4;
+ uint64_t exp_ent:1;
+ uint64_t rng_rst:1;
+ uint64_t rnm_rst:1;
+ uint64_t rng_en:1;
+ uint64_t ent_en:1;
+ } s;
+ struct cvmx_rnm_ctl_status_cn30xx {
+ uint64_t reserved_4_63:60;
+ uint64_t rng_rst:1;
+ uint64_t rnm_rst:1;
+ uint64_t rng_en:1;
+ uint64_t ent_en:1;
+ } cn30xx;
+ struct cvmx_rnm_ctl_status_cn30xx cn31xx;
+ struct cvmx_rnm_ctl_status_cn30xx cn38xx;
+ struct cvmx_rnm_ctl_status_cn30xx cn38xxp2;
+ struct cvmx_rnm_ctl_status_s cn50xx;
+ struct cvmx_rnm_ctl_status_s cn52xx;
+ struct cvmx_rnm_ctl_status_s cn52xxp1;
+ struct cvmx_rnm_ctl_status_s cn56xx;
+ struct cvmx_rnm_ctl_status_s cn56xxp1;
+ struct cvmx_rnm_ctl_status_s cn58xx;
+ struct cvmx_rnm_ctl_status_s cn58xxp1;
+};
+
+#endif
Index: linux-2.6.30.8/drivers/char/hw_random/Kconfig
===================================================================
--- linux-2.6.30.8.orig/drivers/char/hw_random/Kconfig 2009-09-24 17:28:02.000000000 +0200
+++ linux-2.6.30.8/drivers/char/hw_random/Kconfig 2009-10-08 13:10:09.000000000 +0200
@@ -126,6 +126,19 @@
If unsure, say Y.
+config HW_RANDOM_OCTEON
+ tristate "Octeon Random Number Generator support"
+ depends on HW_RANDOM && CPU_CAVIUM_OCTEON
+ default HW_RANDOM
+ ---help---
+ This driver provides kernel-side support for the Random Number
+ Generator hardware found on Octeon processors.
+
+ To compile this driver as a module, choose M here: the
+ module will be called octeon-rng.
+
+ If unsure, say Y.
+
config HW_RANDOM_PASEMI
tristate "PA Semi HW Random Number Generator support"
depends on HW_RANDOM && PPC_PASEMI
Index: linux-2.6.30.8/drivers/char/hw_random/Makefile
===================================================================
--- linux-2.6.30.8.orig/drivers/char/hw_random/Makefile 2009-09-24 17:28:02.000000000 +0200
+++ linux-2.6.30.8/drivers/char/hw_random/Makefile 2009-10-08 13:10:23.000000000 +0200
@@ -15,3 +15,4 @@
obj-$(CONFIG_HW_RANDOM_OMAP) += omap-rng.o
obj-$(CONFIG_HW_RANDOM_PASEMI) += pasemi-rng.o
obj-$(CONFIG_HW_RANDOM_VIRTIO) += virtio-rng.o
+obj-$(CONFIG_HW_RANDOM_OCTEON) += octeon-rng.o
Index: linux-2.6.30.8/drivers/char/hw_random/octeon-rng.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-2.6.30.8/drivers/char/hw_random/octeon-rng.c 2009-10-08 13:10:09.000000000 +0200
@@ -0,0 +1,147 @@
+/*
+ * Hardware Random Number Generator support for Cavium Networks
+ * Octeon processor family.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2009 Cavium Networks
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/hw_random.h>
+#include <linux/io.h>
+
+#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-rnm-defs.h>
+
+struct octeon_rng {
+ struct hwrng ops;
+ void __iomem *control_status;
+ void __iomem *result;
+};
+
+static int octeon_rng_init(struct hwrng *rng)
+{
+ union cvmx_rnm_ctl_status ctl;
+ struct octeon_rng *p = container_of(rng, struct octeon_rng, ops);
+
+ ctl.u64 = 0;
+ ctl.s.ent_en = 1; /* Enable the entropy source. */
+ ctl.s.rng_en = 1; /* Enable the RNG hardware. */
+ cvmx_write_csr((u64)p->control_status, ctl.u64);
+ return 0;
+}
+
+static void octeon_rng_cleanup(struct hwrng *rng)
+{
+ union cvmx_rnm_ctl_status ctl;
+ struct octeon_rng *p = container_of(rng, struct octeon_rng, ops);
+
+ ctl.u64 = 0;
+ /* Disable everything. */
+ cvmx_write_csr((u64)p->control_status, ctl.u64);
+}
+
+static int octeon_rng_data_read(struct hwrng *rng, u32 *data)
+{
+ struct octeon_rng *p = container_of(rng, struct octeon_rng, ops);
+
+ *data = cvmx_read64_uint32((u64)p->result);
+ return sizeof(u32);
+}
+
+static int __devinit octeon_rng_probe(struct platform_device *pdev)
+{
+ struct resource *res_ports;
+ struct resource *res_result;
+ struct octeon_rng *rng;
+ int ret;
+ struct hwrng ops = {
+ .name = "octeon",
+ .init = octeon_rng_init,
+ .cleanup = octeon_rng_cleanup,
+ .data_read = octeon_rng_data_read
+ };
+
+ rng = devm_kzalloc(&pdev->dev, sizeof(*rng), GFP_KERNEL);
+ if (!rng)
+ return -ENOMEM;
+
+ res_ports = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res_ports)
+ goto err_ports;
+
+ res_result = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (!res_result)
+ goto err_ports;
+
+
+ rng->control_status = devm_ioremap_nocache(&pdev->dev,
+ res_ports->start,
+ sizeof(u64));
+ if (!rng->control_status)
+ goto err_ports;
+
+ rng->result = devm_ioremap_nocache(&pdev->dev,
+ res_result->start,
+ sizeof(u64));
+ if (!rng->result)
+ goto err_r;
+
+ rng->ops = ops;
+
+ dev_set_drvdata(&pdev->dev, &rng->ops);
+ ret = hwrng_register(&rng->ops);
+ if (ret)
+ goto err;
+
+ dev_info(&pdev->dev, "Octeon Random Number Generator\n");
+
+ return 0;
+err:
+ devm_iounmap(&pdev->dev, rng->control_status);
+err_r:
+ devm_iounmap(&pdev->dev, rng->result);
+err_ports:
+ devm_kfree(&pdev->dev, rng);
+ return -ENOENT;
+}
+
+static int __exit octeon_rng_remove(struct platform_device *pdev)
+{
+ struct hwrng *rng = dev_get_drvdata(&pdev->dev);
+
+ hwrng_unregister(rng);
+
+ return 0;
+}
+
+static struct platform_driver octeon_rng_driver = {
+ .driver = {
+ .name = "octeon_rng",
+ .owner = THIS_MODULE,
+ },
+ .probe = octeon_rng_probe,
+ .remove = __exit_p(octeon_rng_remove),
+};
+
+static int __init octeon_rng_mod_init(void)
+{
+ return platform_driver_register(&octeon_rng_driver);
+}
+
+static void __exit octeon_rng_mod_exit(void)
+{
+ platform_driver_unregister(&octeon_rng_driver);
+}
+
+module_init(octeon_rng_mod_init);
+module_exit(octeon_rng_mod_exit);
+
+MODULE_AUTHOR("David Daney");
+MODULE_LICENSE("GPL");

371
target/linux/octeon/patches-2.6.30/017-platform_devices.patch
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@ -1,371 +0,0 @@
From: David Daney <ddaney@caviumnetworks.com>
Date: Wed, 16 Sep 2009 21:54:18 +0000 (-0700)
Subject: MIPS: Octeon: Move some platform device registration to its own file.
X-Git-Tag: linux-2.6.32-rc1~29
X-Git-Url: http://www.linux-mips.org/git?p=linux.git;a=commitdiff_plain;h=936c111e;hp=e1302af3482d3955f5a6100160e595e792d5f1e4
MIPS: Octeon: Move some platform device registration to its own file.
There is a bunch of platform device registration in
arch/mips/cavium-octeon/setup.c. We move it to its own file in
preparation for adding more platform devices.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index d6903c3..1394362 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -6,10 +6,10 @@
# License. See the file "COPYING" in the main directory of this archive
# for more details.
#
-# Copyright (C) 2005-2008 Cavium Networks
+# Copyright (C) 2005-2009 Cavium Networks
#
-obj-y := setup.o serial.o octeon-irq.o csrc-octeon.o
+obj-y := setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
obj-y += dma-octeon.o flash_setup.o
obj-y += octeon-memcpy.o
diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
new file mode 100644
index 0000000..be711dd
--- /dev/null
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -0,0 +1,164 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004-2009 Cavium Networks
+ * Copyright (C) 2008 Wind River Systems
+ */
+
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-rnm-defs.h>
+
+static struct octeon_cf_data octeon_cf_data;
+
+static int __init octeon_cf_device_init(void)
+{
+ union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
+ unsigned long base_ptr, region_base, region_size;
+ struct platform_device *pd;
+ struct resource cf_resources[3];
+ unsigned int num_resources;
+ int i;
+ int ret = 0;
+
+ /* Setup octeon-cf platform device if present. */
+ base_ptr = 0;
+ if (octeon_bootinfo->major_version == 1
+ && octeon_bootinfo->minor_version >= 1) {
+ if (octeon_bootinfo->compact_flash_common_base_addr)
+ base_ptr =
+ octeon_bootinfo->compact_flash_common_base_addr;
+ } else {
+ base_ptr = 0x1d000800;
+ }
+
+ if (!base_ptr)
+ return ret;
+
+ /* Find CS0 region. */
+ for (i = 0; i < 8; i++) {
+ mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i));
+ region_base = mio_boot_reg_cfg.s.base << 16;
+ region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
+ if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
+ && base_ptr < region_base + region_size)
+ break;
+ }
+ if (i >= 7) {
+ /* i and i + 1 are CS0 and CS1, both must be less than 8. */
+ goto out;
+ }
+ octeon_cf_data.base_region = i;
+ octeon_cf_data.is16bit = mio_boot_reg_cfg.s.width;
+ octeon_cf_data.base_region_bias = base_ptr - region_base;
+ memset(cf_resources, 0, sizeof(cf_resources));
+ num_resources = 0;
+ cf_resources[num_resources].flags = IORESOURCE_MEM;
+ cf_resources[num_resources].start = region_base;
+ cf_resources[num_resources].end = region_base + region_size - 1;
+ num_resources++;
+
+
+ if (!(base_ptr & 0xfffful)) {
+ /*
+ * Boot loader signals availability of DMA (true_ide
+ * mode) by setting low order bits of base_ptr to
+ * zero.
+ */
+
+ /* Asume that CS1 immediately follows. */
+ mio_boot_reg_cfg.u64 =
+ cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i + 1));
+ region_base = mio_boot_reg_cfg.s.base << 16;
+ region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
+ if (!mio_boot_reg_cfg.s.en)
+ goto out;
+
+ cf_resources[num_resources].flags = IORESOURCE_MEM;
+ cf_resources[num_resources].start = region_base;
+ cf_resources[num_resources].end = region_base + region_size - 1;
+ num_resources++;
+
+ octeon_cf_data.dma_engine = 0;
+ cf_resources[num_resources].flags = IORESOURCE_IRQ;
+ cf_resources[num_resources].start = OCTEON_IRQ_BOOTDMA;
+ cf_resources[num_resources].end = OCTEON_IRQ_BOOTDMA;
+ num_resources++;
+ } else {
+ octeon_cf_data.dma_engine = -1;
+ }
+
+ pd = platform_device_alloc("pata_octeon_cf", -1);
+ if (!pd) {
+ ret = -ENOMEM;
+ goto out;
+ }
+ pd->dev.platform_data = &octeon_cf_data;
+
+ ret = platform_device_add_resources(pd, cf_resources, num_resources);
+ if (ret)
+ goto fail;
+
+ ret = platform_device_add(pd);
+ if (ret)
+ goto fail;
+
+ return ret;
+fail:
+ platform_device_put(pd);
+out:
+ return ret;
+}
+device_initcall(octeon_cf_device_init);
+
+/* Octeon Random Number Generator. */
+static int __init octeon_rng_device_init(void)
+{
+ struct platform_device *pd;
+ int ret = 0;
+
+ struct resource rng_resources[] = {
+ {
+ .flags = IORESOURCE_MEM,
+ .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
+ .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
+ }, {
+ .flags = IORESOURCE_MEM,
+ .start = cvmx_build_io_address(8, 0),
+ .end = cvmx_build_io_address(8, 0) + 0x7
+ }
+ };
+
+ pd = platform_device_alloc("octeon_rng", -1);
+ if (!pd) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ ret = platform_device_add_resources(pd, rng_resources,
+ ARRAY_SIZE(rng_resources));
+ if (ret)
+ goto fail;
+
+ ret = platform_device_add(pd);
+ if (ret)
+ goto fail;
+
+ return ret;
+fail:
+ platform_device_put(pd);
+
+out:
+ return ret;
+}
+device_initcall(octeon_rng_device_init);
+
+MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Platform driver for Octeon SOC");
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 468a120..b321d3b 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -11,7 +11,6 @@
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/io.h>
-#include <linux/irq.h>
#include <linux/serial.h>
#include <linux/smp.h>
#include <linux/types.h>
@@ -33,7 +32,6 @@
#include <asm/time.h>
#include <asm/octeon/octeon.h>
-#include <asm/octeon/cvmx-rnm-defs.h>
#ifdef CONFIG_CAVIUM_DECODE_RSL
extern void cvmx_interrupt_rsl_decode(void);
@@ -825,147 +823,3 @@ void prom_free_prom_memory(void)
CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB option is set */
octeon_hal_setup_reserved32();
}
-
-static struct octeon_cf_data octeon_cf_data;
-
-static int __init octeon_cf_device_init(void)
-{
- union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
- unsigned long base_ptr, region_base, region_size;
- struct platform_device *pd;
- struct resource cf_resources[3];
- unsigned int num_resources;
- int i;
- int ret = 0;
-
- /* Setup octeon-cf platform device if present. */
- base_ptr = 0;
- if (octeon_bootinfo->major_version == 1
- && octeon_bootinfo->minor_version >= 1) {
- if (octeon_bootinfo->compact_flash_common_base_addr)
- base_ptr =
- octeon_bootinfo->compact_flash_common_base_addr;
- } else {
- base_ptr = 0x1d000800;
- }
-
- if (!base_ptr)
- return ret;
-
- /* Find CS0 region. */
- for (i = 0; i < 8; i++) {
- mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i));
- region_base = mio_boot_reg_cfg.s.base << 16;
- region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
- if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
- && base_ptr < region_base + region_size)
- break;
- }
- if (i >= 7) {
- /* i and i + 1 are CS0 and CS1, both must be less than 8. */
- goto out;
- }
- octeon_cf_data.base_region = i;
- octeon_cf_data.is16bit = mio_boot_reg_cfg.s.width;
- octeon_cf_data.base_region_bias = base_ptr - region_base;
- memset(cf_resources, 0, sizeof(cf_resources));
- num_resources = 0;
- cf_resources[num_resources].flags = IORESOURCE_MEM;
- cf_resources[num_resources].start = region_base;
- cf_resources[num_resources].end = region_base + region_size - 1;
- num_resources++;
-
-
- if (!(base_ptr & 0xfffful)) {
- /*
- * Boot loader signals availability of DMA (true_ide
- * mode) by setting low order bits of base_ptr to
- * zero.
- */
-
- /* Asume that CS1 immediately follows. */
- mio_boot_reg_cfg.u64 =
- cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i + 1));
- region_base = mio_boot_reg_cfg.s.base << 16;
- region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
- if (!mio_boot_reg_cfg.s.en)
- goto out;
-
- cf_resources[num_resources].flags = IORESOURCE_MEM;
- cf_resources[num_resources].start = region_base;
- cf_resources[num_resources].end = region_base + region_size - 1;
- num_resources++;
-
- octeon_cf_data.dma_engine = 0;
- cf_resources[num_resources].flags = IORESOURCE_IRQ;
- cf_resources[num_resources].start = OCTEON_IRQ_BOOTDMA;
- cf_resources[num_resources].end = OCTEON_IRQ_BOOTDMA;
- num_resources++;
- } else {
- octeon_cf_data.dma_engine = -1;
- }
-
- pd = platform_device_alloc("pata_octeon_cf", -1);
- if (!pd) {
- ret = -ENOMEM;
- goto out;
- }
- pd->dev.platform_data = &octeon_cf_data;
-
- ret = platform_device_add_resources(pd, cf_resources, num_resources);
- if (ret)
- goto fail;
-
- ret = platform_device_add(pd);
- if (ret)
- goto fail;
-
- return ret;
-fail:
- platform_device_put(pd);
-out:
- return ret;
-}
-device_initcall(octeon_cf_device_init);
-
-/* Octeon Random Number Generator. */
-static int __init octeon_rng_device_init(void)
-{
- struct platform_device *pd;
- int ret = 0;
-
- struct resource rng_resources[] = {
- {
- .flags = IORESOURCE_MEM,
- .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
- .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
- }, {
- .flags = IORESOURCE_MEM,
- .start = cvmx_build_io_address(8, 0),
- .end = cvmx_build_io_address(8, 0) + 0x7
- }
- };
-
- pd = platform_device_alloc("octeon_rng", -1);
- if (!pd) {
- ret = -ENOMEM;
- goto out;
- }
-
- ret = platform_device_add_resources(pd, rng_resources,
- ARRAY_SIZE(rng_resources));
- if (ret)
- goto fail;
-
- ret = platform_device_add(pd);
- if (ret)
- goto fail;
-
- return ret;
-fail:
- platform_device_put(pd);
-
-out:
- return ret;
-}
-device_initcall(octeon_rng_device_init);

17496
target/linux/octeon/patches-2.6.30/018-dwc_otg.patch
View File

File diff suppressed because it is too large Load Diff

77
target/linux/octeon/patches-2.6.30/100-wndap330_hacks.patch
Unescape Escape View File

@ -1,77 +0,0 @@
--- a/drivers/staging/octeon/cvmx-helper-board.c
+++ b/drivers/staging/octeon/cvmx-helper-board.c
@@ -90,7 +90,7 @@ int cvmx_helper_board_get_mii_address(in
case CVMX_BOARD_TYPE_KODAMA:
case CVMX_BOARD_TYPE_EBH3100:
case CVMX_BOARD_TYPE_HIKARI:
- case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
+ //case CVMX_BOARD_TYPE_CN3010_EVB_HS5: /* hack for the WNDAP330 */
case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
/*
@@ -103,6 +103,12 @@ int cvmx_helper_board_get_mii_address(in
return 9;
else
return -1;
+ case CVMX_BOARD_TYPE_CN3010_EVB_HS5: /* hack for the WNDAP330 */
+ /* We have only one port, using GMII */
+ if (ipd_port == 0)
+ return 9;
+ else
+ return -1;
case CVMX_BOARD_TYPE_NAC38:
/* Board has 8 RGMII ports PHYs are 0-7 */
if ((ipd_port >= 0) && (ipd_port < 4))
@@ -205,7 +211,7 @@ cvmx_helper_link_info_t __cvmx_helper_bo
result.s.speed = 1000;
return result;
case CVMX_BOARD_TYPE_EBH3100:
- case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
+ //case CVMX_BOARD_TYPE_CN3010_EVB_HS5: /* hack for the WNDAP330 */
case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
/* Port 1 on these boards is always Gigabit */
@@ -217,6 +223,9 @@ cvmx_helper_link_info_t __cvmx_helper_bo
}
/* Fall through to the generic code below */
break;
+ case CVMX_BOARD_TYPE_CN3010_EVB_HS5: /* hack for the WNDAP330 */
+ is_broadcom_phy = 1;
+ break;
case CVMX_BOARD_TYPE_CUST_NB5:
/* Port 1 on these boards is always Gigabit */
if (ipd_port == 1) {
--- a/drivers/staging/octeon/cvmx-helper-rgmii.c
+++ b/drivers/staging/octeon/cvmx-helper-rgmii.c
@@ -66,13 +66,15 @@ int __cvmx_helper_rgmii_probe(int interf
cvmx_dprintf("ERROR: RGMII initialize called in "
"SPI interface\n");
} else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
- || OCTEON_IS_MODEL(OCTEON_CN30XX)
+ //|| OCTEON_IS_MODEL(OCTEON_CN30XX)
|| OCTEON_IS_MODEL(OCTEON_CN50XX)) {
/*
* On these chips "type" says we're in
* GMII/MII mode. This limits us to 2 ports
*/
num_ports = 2;
+ } else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) {
+ num_ports = 1;
} else {
cvmx_dprintf("ERROR: Unsupported Octeon model in %s\n",
__func__);
--- a/arch/mips/cavium-octeon/pci.c
+++ b/arch/mips/cavium-octeon/pci.c
@@ -95,9 +95,11 @@ const char *octeon_get_pci_interrupts(vo
case CVMX_BOARD_TYPE_EBH3000:
return "";
case CVMX_BOARD_TYPE_EBH3100:
- case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
+ //case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
+ case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
+ return "AAAAAAAAAAAAAABAAAAAAAAAAAAAAABA";
case CVMX_BOARD_TYPE_BBGW_REF:
return "AABCD";
default:

21
target/linux/octeon/patches-2.6.30/105-nb5_fixup.patch
Unescape Escape View File

@ -1,21 +0,0 @@
--- a/arch/mips/cavium-octeon/pci.c
+++ b/arch/mips/cavium-octeon/pci.c
@@ -102,6 +102,8 @@ const char *octeon_get_pci_interrupts(vo
return "AAAAAAAAAAAAAABAAAAAAAAAAAAAAABA";
case CVMX_BOARD_TYPE_BBGW_REF:
return "AABCD";
+ case CVMX_BOARD_TYPE_CUST_NB5:
+ return "ABDABAAAAAAAAAAAAAAAAAAAAAAAAAAA";
default:
return "";
}
--- a/drivers/staging/octeon/cvmx-helper-board.c
+++ b/drivers/staging/octeon/cvmx-helper-board.c
@@ -699,6 +699,7 @@ cvmx_helper_board_usb_clock_types_t __cv
{
switch (cvmx_sysinfo_get()->board_type) {
case CVMX_BOARD_TYPE_BBGW_REF:
+ case CVMX_BOARD_TYPE_CUST_NB5:
return USB_CLOCK_TYPE_CRYSTAL_12;
}
return USB_CLOCK_TYPE_REF_48;

372
target/linux/octeon/patches-2.6.30/106-no_module_reloc.patch
Unescape Escape View File

@ -1,372 +0,0 @@
diff -urN linux-2.6.30.10/arch/mips/Makefile linux-2.6.30.10.new//arch/mips/Makefile
--- linux-2.6.30.10/arch/mips/Makefile 2010-01-29 16:12:01.000000000 +0100
+++ linux-2.6.30.10.new//arch/mips/Makefile 2009-12-04 07:00:07.000000000 +0100
@@ -83,7 +83,7 @@
cflags-y += -G 0 -mno-abicalls -fno-pic -pipe
cflags-y += -msoft-float
LDFLAGS_vmlinux += -G 0 -static -n -nostdlib
-MODFLAGS += -mno-long-calls
+MODFLAGS += -mlong-calls
cflags-y += -ffreestanding
diff -urN linux-2.6.30.10/arch/mips/include/asm/module.h linux-2.6.30.10.new//arch/mips/include/asm/module.h
--- linux-2.6.30.10/arch/mips/include/asm/module.h 2010-01-29 16:12:01.000000000 +0100
+++ linux-2.6.30.10.new//arch/mips/include/asm/module.h 2009-12-04 07:00:07.000000000 +0100
@@ -9,11 +9,6 @@
struct list_head dbe_list;
const struct exception_table_entry *dbe_start;
const struct exception_table_entry *dbe_end;
-
- void *phys_plt_tbl;
- void *virt_plt_tbl;
- unsigned int phys_plt_offset;
- unsigned int virt_plt_offset;
};
typedef uint8_t Elf64_Byte; /* Type for a 8-bit quantity. */
diff -urN linux-2.6.30.10/arch/mips/kernel/module.c linux-2.6.30.10.new//arch/mips/kernel/module.c
--- linux-2.6.30.10/arch/mips/kernel/module.c 2010-01-29 16:12:01.000000000 +0100
+++ linux-2.6.30.10.new//arch/mips/kernel/module.c 2009-12-04 07:00:07.000000000 +0100
@@ -43,116 +43,6 @@
static LIST_HEAD(dbe_list);
static DEFINE_SPINLOCK(dbe_lock);
-/*
- * Get the potential max trampolines size required of the init and
- * non-init sections. Only used if we cannot find enough contiguous
- * physically mapped memory to put the module into.
- */
-static unsigned int
-get_plt_size(const Elf_Ehdr *hdr, const Elf_Shdr *sechdrs,
- const char *secstrings, unsigned int symindex, bool is_init)
-{
- unsigned long ret = 0;
- unsigned int i, j;
- Elf_Sym *syms;
-
- /* Everything marked ALLOC (this includes the exported symbols) */
- for (i = 1; i < hdr->e_shnum; ++i) {
- unsigned int info = sechdrs[i].sh_info;
-
- if (sechdrs[i].sh_type != SHT_REL
- && sechdrs[i].sh_type != SHT_RELA)
- continue;
-
- /* Not a valid relocation section? */
- if (info >= hdr->e_shnum)
- continue;
-
- /* Don't bother with non-allocated sections */
- if (!(sechdrs[info].sh_flags & SHF_ALLOC))
- continue;
-
- /* If it's called *.init*, and we're not init, we're
- not interested */
- if ((strstr(secstrings + sechdrs[i].sh_name, ".init") != 0)
- != is_init)
- continue;
-
- syms = (Elf_Sym *) sechdrs[symindex].sh_addr;
- if (sechdrs[i].sh_type == SHT_REL) {
- Elf_Mips_Rel *rel = (void *) sechdrs[i].sh_addr;
- unsigned int size = sechdrs[i].sh_size / sizeof(*rel);
-
- for (j = 0; j < size; ++j) {
- Elf_Sym *sym;
-
- if (ELF_MIPS_R_TYPE(rel[j]) != R_MIPS_26)
- continue;
-
- sym = syms + ELF_MIPS_R_SYM(rel[j]);
- if (!is_init && sym->st_shndx != SHN_UNDEF)
- continue;
-
- ret += 4 * sizeof(int);
- }
- } else {
- Elf_Mips_Rela *rela = (void *) sechdrs[i].sh_addr;
- unsigned int size = sechdrs[i].sh_size / sizeof(*rela);
-
- for (j = 0; j < size; ++j) {
- Elf_Sym *sym;
-
- if (ELF_MIPS_R_TYPE(rela[j]) != R_MIPS_26)
- continue;
-
- sym = syms + ELF_MIPS_R_SYM(rela[j]);
- if (!is_init && sym->st_shndx != SHN_UNDEF)
- continue;
-
- ret += 4 * sizeof(int);
- }
- }
- }
-
- return ret;
-}
-
-#ifndef MODULE_START
-static void *alloc_phys(unsigned long size)
-{
- unsigned order;
- struct page *page;
- struct page *p;
-
- size = PAGE_ALIGN(size);
- order = get_order(size);
-
- page = alloc_pages(GFP_KERNEL | __GFP_NORETRY | __GFP_NOWARN |
- __GFP_THISNODE, order);
- if (!page)
- return NULL;
-
- split_page(page, order);
-
- for (p = page + (size >> PAGE_SHIFT); p < page + (1 << order); ++p)
- __free_page(p);
-
- return page_address(page);
-}
-#endif
-
-static void free_phys(void *ptr, unsigned long size)
-{
- struct page *page;
- struct page *end;
-
- page = virt_to_page(ptr);
- end = page + (PAGE_ALIGN(size) >> PAGE_SHIFT);
-
- for (; page < end; ++page)
- __free_page(page);
-}
-
void *module_alloc(unsigned long size)
{
#ifdef MODULE_START
@@ -168,101 +58,23 @@
return __vmalloc_area(area, GFP_KERNEL, PAGE_KERNEL);
#else
- void *ptr;
-
if (size == 0)
return NULL;
-
- ptr = alloc_phys(size);
-
- /* If we failed to allocate physically contiguous memory,
- * fall back to regular vmalloc. The module loader code will
- * create jump tables to handle long jumps */
- if (!ptr)
- return vmalloc(size);
-
- return ptr;
-#endif
-}
-
-static inline bool is_phys_addr(void *ptr)
-{
-#ifdef CONFIG_64BIT
- return (KSEGX((unsigned long)ptr) == CKSEG0);
-#else
- return (KSEGX(ptr) == KSEG0);
+ return vmalloc(size);
#endif
}
/* Free memory returned from module_alloc */
void module_free(struct module *mod, void *module_region)
{
- if (is_phys_addr(module_region)) {
- if (mod->module_init == module_region)
- free_phys(module_region, mod->init_size);
- else if (mod->module_core == module_region)
- free_phys(module_region, mod->core_size);
- else
- BUG();
- } else {
- vfree(module_region);
- }
+ vfree(module_region);
/* FIXME: If module_region == mod->init_region, trim exception
table entries. */
}
-static void *__module_alloc(int size, bool phys)
-{
- void *ptr;
-
- if (phys)
- ptr = kmalloc(size, GFP_KERNEL);
- else
- ptr = vmalloc(size);
- return ptr;
-}
-
-static void __module_free(void *ptr)
-{
- if (is_phys_addr(ptr))
- kfree(ptr);
- else
- vfree(ptr);
-}
-
int module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs,
char *secstrings, struct module *mod)
{
- unsigned int symindex = 0;
- unsigned int core_size, init_size;
- int i;
-
- for (i = 1; i < hdr->e_shnum; i++)
- if (sechdrs[i].sh_type == SHT_SYMTAB)
- symindex = i;
-
- core_size = get_plt_size(hdr, sechdrs, secstrings, symindex, false);
- init_size = get_plt_size(hdr, sechdrs, secstrings, symindex, true);
-
- mod->arch.phys_plt_offset = 0;
- mod->arch.virt_plt_offset = 0;
- mod->arch.phys_plt_tbl = NULL;
- mod->arch.virt_plt_tbl = NULL;
-
- if ((core_size + init_size) == 0)
- return 0;
-
- mod->arch.phys_plt_tbl = __module_alloc(core_size + init_size, 1);
- if (!mod->arch.phys_plt_tbl)
- return -ENOMEM;
-
- mod->arch.virt_plt_tbl = __module_alloc(core_size + init_size, 0);
- if (!mod->arch.virt_plt_tbl) {
- __module_free(mod->arch.phys_plt_tbl);
- mod->arch.phys_plt_tbl = NULL;
- return -ENOMEM;
- }
-
return 0;
}
@@ -285,37 +97,27 @@
return 0;
}
-static Elf_Addr add_plt_entry_to(unsigned *plt_offset,
- void *start, Elf_Addr v)
+static int apply_r_mips_26_rel(struct module *me, u32 *location, Elf_Addr v)
{
- unsigned *tramp = start + *plt_offset;
-
- *plt_offset += 4 * sizeof(int);
-
- /* adjust carry for addiu */
- if (v & 0x00008000)
- v += 0x10000;
-
- tramp[0] = 0x3c190000 | (v >> 16); /* lui t9, hi16 */
- tramp[1] = 0x27390000 | (v & 0xffff); /* addiu t9, t9, lo16 */
- tramp[2] = 0x03200008; /* jr t9 */
- tramp[3] = 0x00000000; /* nop */
+ if (v % 4) {
+ printk(KERN_ERR "module %s: dangerous relocation\n", me->name);
+ return -ENOEXEC;
+ }
- return (Elf_Addr) tramp;
-}
+ if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) {
+ printk(KERN_ERR
+ "module %s: relocation overflow\n",
+ me->name);
+ return -ENOEXEC;
+ }
-static Elf_Addr add_plt_entry(struct module *me, void *location, Elf_Addr v)
-{
- if (is_phys_addr(location))
- return add_plt_entry_to(&me->arch.phys_plt_offset,
- me->arch.phys_plt_tbl, v);
- else
- return add_plt_entry_to(&me->arch.virt_plt_offset,
- me->arch.virt_plt_tbl, v);
+ *location = (*location & ~0x03ffffff) |
+ ((*location + (v >> 2)) & 0x03ffffff);
+ return 0;
}
-static int set_r_mips_26(struct module *me, u32 *location, u32 ofs, Elf_Addr v)
+static int apply_r_mips_26_rela(struct module *me, u32 *location, Elf_Addr v)
{
if (v % 4) {
printk(KERN_ERR "module %s: dangerous relocation\n", me->name);
@@ -323,31 +125,17 @@
}
if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) {
- v = add_plt_entry(me, location, v + (ofs << 2));
- if (!v) {
- printk(KERN_ERR
+ printk(KERN_ERR
"module %s: relocation overflow\n",
me->name);
- return -ENOEXEC;
- }
- ofs = 0;
+ return -ENOEXEC;
}
- *location = (*location & ~0x03ffffff) | ((ofs + (v >> 2)) & 0x03ffffff);
+ *location = (*location & ~0x03ffffff) | ((v >> 2) & 0x03ffffff);
return 0;
}
-static int apply_r_mips_26_rel(struct module *me, u32 *location, Elf_Addr v)
-{
- return set_r_mips_26(me, location, *location & 0x03ffffff, v);
-}
-
-static int apply_r_mips_26_rela(struct module *me, u32 *location, Elf_Addr v)
-{
- return set_r_mips_26(me, location, 0, v);
-}
-
static int apply_r_mips_hi16_rel(struct module *me, u32 *location, Elf_Addr v)
{
struct mips_hi16 *n;
@@ -612,32 +400,11 @@
list_add(&me->arch.dbe_list, &dbe_list);
spin_unlock_irq(&dbe_lock);
}
-
- /* Get rid of the fixup trampoline if we're running the module
- * from physically mapped address space */
- if (me->arch.phys_plt_offset == 0) {
- __module_free(me->arch.phys_plt_tbl);
- me->arch.phys_plt_tbl = NULL;
- }
- if (me->arch.virt_plt_offset == 0) {
- __module_free(me->arch.virt_plt_tbl);
- me->arch.virt_plt_tbl = NULL;
- }
-
return 0;
}
void module_arch_cleanup(struct module *mod)
{
- if (mod->arch.phys_plt_tbl) {
- __module_free(mod->arch.phys_plt_tbl);
- mod->arch.phys_plt_tbl = NULL;
- }
- if (mod->arch.virt_plt_tbl) {
- __module_free(mod->arch.virt_plt_tbl);
- mod->arch.virt_plt_tbl = NULL;
- }
-
spin_lock_irq(&dbe_lock);
list_del(&mod->arch.dbe_list);
spin_unlock_irq(&dbe_lock);
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