brcm47xx: update patches
* this adds sflash support for ssb devices * the flash is now a platform device * minor updates SVN-Revision: 27902v19.07.3_mercusys_ac12_duma
Hauke Mehrtens
13 years ago
parent
85b858fae6
commit
8428ebd8e8
@ -0,0 +1,143 @@
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From be495ba9c365a31cf6a9fa0f67df9a9a9e0f1a1f Mon Sep 17 00:00:00 2001
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From: Hauke Mehrtens <hauke@hauke-m.de>
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Date: Sat, 23 Jul 2011 23:57:06 +0200
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Subject: [PATCH 14/26] ssb: move flash to chipcommon
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Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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---
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arch/mips/bcm47xx/nvram.c | 8 +++---
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arch/mips/bcm47xx/wgt634u.c | 8 +++---
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drivers/ssb/driver_mipscore.c | 31 +++++++++++++++++++---------
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include/linux/ssb/ssb_driver_chipcommon.h | 18 ++++++++++++++++
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include/linux/ssb/ssb_driver_mips.h | 4 ---
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5 files changed, 47 insertions(+), 22 deletions(-)
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--- a/arch/mips/bcm47xx/nvram.c
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+++ b/arch/mips/bcm47xx/nvram.c
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@@ -27,7 +27,7 @@ static char nvram_buf[NVRAM_SPACE];
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static void early_nvram_init(void)
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{
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#ifdef CONFIG_BCM47XX_SSB
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- struct ssb_mipscore *mcore_ssb;
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+ struct ssb_chipcommon *ssb_cc;
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#endif
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#ifdef CONFIG_BCM47XX_BCMA
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struct bcma_drv_cc *bcma_cc;
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@@ -42,9 +42,9 @@ static void early_nvram_init(void)
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switch (bcm47xx_bus_type) {
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#ifdef CONFIG_BCM47XX_SSB
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case BCM47XX_BUS_TYPE_SSB:
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- mcore_ssb = &bcm47xx_bus.ssb.mipscore;
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- base = mcore_ssb->flash_window;
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- lim = mcore_ssb->flash_window_size;
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+ ssb_cc = &bcm47xx_bus.ssb.chipco;
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+ base = ssb_cc->pflash.window;
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+ lim = ssb_cc->pflash.window_size;
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break;
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#endif
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#ifdef CONFIG_BCM47XX_BCMA
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--- a/arch/mips/bcm47xx/wgt634u.c
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+++ b/arch/mips/bcm47xx/wgt634u.c
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@@ -156,10 +156,10 @@ static int __init wgt634u_init(void)
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SSB_CHIPCO_IRQ_GPIO);
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}
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- wgt634u_flash_data.width = mcore->flash_buswidth;
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- wgt634u_flash_resource.start = mcore->flash_window;
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- wgt634u_flash_resource.end = mcore->flash_window
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- + mcore->flash_window_size
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+ wgt634u_flash_data.width = mcore->pflash.buswidth;
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+ wgt634u_flash_resource.start = mcore->pflash.window;
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+ wgt634u_flash_resource.end = mcore->pflash.window
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+ + mcore->pflash.window_size
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- 1;
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return platform_add_devices(wgt634u_devices,
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ARRAY_SIZE(wgt634u_devices));
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--- a/drivers/ssb/driver_mipscore.c
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+++ b/drivers/ssb/driver_mipscore.c
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@@ -190,16 +190,27 @@ static void ssb_mips_flash_detect(struct
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{
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struct ssb_bus *bus = mcore->dev->bus;
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- mcore->flash_buswidth = 2;
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- if (bus->chipco.dev) {
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- mcore->flash_window = 0x1c000000;
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- mcore->flash_window_size = 0x02000000;
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- if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
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- & SSB_CHIPCO_CFG_DS16) == 0)
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- mcore->flash_buswidth = 1;
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- } else {
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- mcore->flash_window = 0x1fc00000;
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- mcore->flash_window_size = 0x00400000;
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+ switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
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+ case SSB_CHIPCO_FLASHT_STSER:
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+ case SSB_CHIPCO_FLASHT_ATSER:
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+ pr_info("serial flash not supported.\n");
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+ break;
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+ case SSB_CHIPCO_FLASHT_PARA:
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+ pr_info("found parallel flash.\n");
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+ bus->chipco.flash_type = SSB_PFLASH;
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+ bus->chipco.pflash.buswidth = 2;
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+ if (bus->chipco.dev) {
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+ bus->chipco.pflash.window = 0x1c000000;
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+ bus->chipco.pflash.window_size = 0x02000000;
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+ if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
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+ & SSB_CHIPCO_CFG_DS16) == 0)
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+ bus->chipco.pflash.buswidth = 1;
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+ } else {
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+ bus->chipco.pflash.window = 0x1fc00000;
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+ bus->chipco.pflash.window_size = 0x00400000;
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+ }
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+ default:
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+ pr_err("flash not supported.\n");
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}
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}
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--- a/include/linux/ssb/ssb_driver_chipcommon.h
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+++ b/include/linux/ssb/ssb_driver_chipcommon.h
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@@ -582,6 +582,18 @@ struct ssb_chipcommon_pmu {
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u32 crystalfreq; /* The active crystal frequency (in kHz) */
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};
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+#ifdef CONFIG_SSB_DRIVER_MIPS
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+enum ssb_flash_type {
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+ SSB_PFLASH,
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+};
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+
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+struct ssb_pflash {
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+ u8 buswidth;
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+ u32 window;
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+ u32 window_size;
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+};
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+#endif /* CONFIG_SSB_DRIVER_MIPS */
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+
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struct ssb_chipcommon {
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struct ssb_device *dev;
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u32 capabilities;
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@@ -589,6 +601,12 @@ struct ssb_chipcommon {
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/* Fast Powerup Delay constant */
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u16 fast_pwrup_delay;
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struct ssb_chipcommon_pmu pmu;
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+#ifdef CONFIG_SSB_DRIVER_MIPS
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+ enum ssb_flash_type flash_type;
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+ union {
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+ struct ssb_pflash pflash;
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+ };
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+#endif /* CONFIG_SSB_DRIVER_MIPS */
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};
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static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
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--- a/include/linux/ssb/ssb_driver_mips.h
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+++ b/include/linux/ssb/ssb_driver_mips.h
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@@ -19,10 +19,6 @@ struct ssb_mipscore {
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int nr_serial_ports;
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struct ssb_serial_port serial_ports[4];
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-
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- u8 flash_buswidth;
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- u32 flash_window;
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- u32 flash_window_size;
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};
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extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
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@ -0,0 +1,697 @@
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From 980da78179592a3f5f99168bc5af415835aa8c13 Mon Sep 17 00:00:00 2001
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From: Hauke Mehrtens <hauke@hauke-m.de>
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Date: Sun, 24 Jul 2011 20:20:36 +0200
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Subject: [PATCH 15/26] ssb: add serial flash support
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Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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---
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drivers/ssb/Kconfig | 6 +
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drivers/ssb/Makefile | 1 +
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drivers/ssb/driver_chipcommon_sflash.c | 556 +++++++++++++++++++++++++++++
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drivers/ssb/driver_mipscore.c | 6 +
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drivers/ssb/ssb_private.h | 4 +
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include/linux/ssb/ssb_driver_chipcommon.h | 30 ++-
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6 files changed, 601 insertions(+), 2 deletions(-)
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create mode 100644 drivers/ssb/driver_chipcommon_sflash.c
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--- a/drivers/ssb/Kconfig
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+++ b/drivers/ssb/Kconfig
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@@ -137,6 +137,12 @@ config SSB_DRIVER_MIPS
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If unsure, say N
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+config SSB_SFLASH
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+ bool
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+ depends on SSB_DRIVER_MIPS
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+ default y
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+
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+
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# Assumption: We are on embedded, if we compile the MIPS core.
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config SSB_EMBEDDED
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bool
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--- a/drivers/ssb/Makefile
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+++ b/drivers/ssb/Makefile
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@@ -11,6 +11,7 @@ ssb-$(CONFIG_SSB_SDIOHOST) += sdio.o
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# built-in drivers
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ssb-y += driver_chipcommon.o
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ssb-y += driver_chipcommon_pmu.o
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+ssb-$(CONFIG_SSB_SFLASH) += driver_chipcommon_sflash.o
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ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o
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ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o
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ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o
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--- /dev/null
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+++ b/drivers/ssb/driver_chipcommon_sflash.c
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@@ -0,0 +1,556 @@
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+/*
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+ * Broadcom SiliconBackplane chipcommon serial flash interface
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+ *
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+ * Copyright 2011, Jonas Gorski <jonas.gorski@gmail.com>
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+ * Copyright 2010, Broadcom Corporation
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+ *
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+ * Licensed under the GNU/GPL. See COPYING for details.
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+ */
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+
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+#include <linux/ssb/ssb.h>
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+#include <linux/ssb/ssb_driver_chipcommon.h>
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+#include <linux/delay.h>
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+
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+#include "ssb_private.h"
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+
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+#define NUM_RETRIES 3
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+
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+
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+/* Issue a serial flash command */
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+static inline void ssb_sflash_cmd(struct ssb_chipcommon *cc, u32 opcode)
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+{
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+ chipco_write32(cc, SSB_CHIPCO_FLASHCTL,
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+ SSB_CHIPCO_FLASHCTL_START | opcode);
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+ while (chipco_read32(cc, SSB_CHIPCO_FLASHCTL)
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+ & SSB_CHIPCO_FLASHCTL_BUSY)
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+ ;
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+}
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+
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+
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+static inline void ssb_sflash_write_u8(struct ssb_chipcommon *cc,
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+ u32 offset, u8 byte)
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+{
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+ chipco_write32(cc, SSB_CHIPCO_FLASHADDR, offset);
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+ chipco_write32(cc, SSB_CHIPCO_FLASHDATA, byte);
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+}
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+
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+/* Initialize serial flash access */
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+int ssb_sflash_init(struct ssb_chipcommon *cc)
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+{
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+ u32 id, id2;
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+
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+ memset(&cc->sflash, 0, sizeof(struct ssb_sflash));
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+
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+ switch (cc->capabilities & SSB_CHIPCO_CAP_FLASHT) {
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+ case SSB_CHIPCO_FLASHT_STSER:
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+ /* Probe for ST chips */
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+ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_DP);
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+ chipco_write32(cc, SSB_CHIPCO_FLASHADDR, 0);
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+ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_RES);
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+ id = chipco_read32(cc, SSB_CHIPCO_FLASHDATA);
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+ cc->sflash.blocksize = 64 * 1024;
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+ switch (id) {
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+ case 0x11:
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+ /* ST M25P20 2 Mbit Serial Flash */
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+ cc->sflash.numblocks = 4;
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+ break;
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+ case 0x12:
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+ /* ST M25P40 4 Mbit Serial Flash */
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+ cc->sflash.numblocks = 8;
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+ break;
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+ case 0x13:
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+ /* ST M25P80 8 Mbit Serial Flash */
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+ cc->sflash.numblocks = 16;
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+ break;
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+ case 0x14:
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+ /* ST M25P16 16 Mbit Serial Flash */
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+ cc->sflash.numblocks = 32;
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+ break;
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+ case 0x15:
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+ /* ST M25P32 32 Mbit Serial Flash */
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+ cc->sflash.numblocks = 64;
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+ break;
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+ case 0x16:
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+ /* ST M25P64 64 Mbit Serial Flash */
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+ cc->sflash.numblocks = 128;
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+ break;
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+ case 0x17:
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+ /* ST M25FL128 128 Mbit Serial Flash */
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+ cc->sflash.numblocks = 256;
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+ break;
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+ case 0xbf:
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+ /* All of the following flashes are SST with
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+ * 4KB subsectors. Others should be added but
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+ * We'll have to revamp the way we identify them
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+ * since RES is not eough to disambiguate them.
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+ */
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+ cc->sflash.blocksize = 4 * 1024;
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+ chipco_write32(cc, SSB_CHIPCO_FLASHADDR, 1);
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+ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_RES);
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+ id2 = chipco_read32(cc, SSB_CHIPCO_FLASHDATA);
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+ switch (id2) {
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+ case 1:
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+ /* SST25WF512 512 Kbit Serial Flash */
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+ case 0x48:
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+ /* SST25VF512 512 Kbit Serial Flash */
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+ cc->sflash.numblocks = 16;
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+ break;
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+ case 2:
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+ /* SST25WF010 1 Mbit Serial Flash */
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+ case 0x49:
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+ /* SST25VF010 1 Mbit Serial Flash */
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+ cc->sflash.numblocks = 32;
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+ break;
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+ case 3:
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+ /* SST25WF020 2 Mbit Serial Flash */
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+ case 0x43:
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+ /* SST25VF020 2 Mbit Serial Flash */
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+ cc->sflash.numblocks = 64;
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+ break;
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+ case 4:
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+ /* SST25WF040 4 Mbit Serial Flash */
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+ case 0x44:
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+ /* SST25VF040 4 Mbit Serial Flash */
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+ case 0x8d:
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+ /* SST25VF040B 4 Mbit Serial Flash */
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+ cc->sflash.numblocks = 128;
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+ break;
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+ case 5:
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+ /* SST25WF080 8 Mbit Serial Flash */
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+ case 0x8e:
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+ /* SST25VF080B 8 Mbit Serial Flash */
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+ cc->sflash.numblocks = 256;
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+ break;
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+ case 0x41:
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+ /* SST25VF016 16 Mbit Serial Flash */
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+ cc->sflash.numblocks = 512;
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+ break;
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+ case 0x4a:
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+ /* SST25VF032 32 Mbit Serial Flash */
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+ cc->sflash.numblocks = 1024;
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+ break;
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+ case 0x4b:
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+ /* SST25VF064 64 Mbit Serial Flash */
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+ cc->sflash.numblocks = 2048;
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+ break;
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+ }
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+ break;
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+ }
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+ break;
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+
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+ case SSB_CHIPCO_FLASHT_ATSER:
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+ /* Probe for Atmel chips */
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+ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_AT_STATUS);
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+ id = chipco_read32(cc, SSB_CHIPCO_FLASHDATA) & 0x3c;
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+ switch (id) {
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+ case 0xc:
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+ /* Atmel AT45DB011 1Mbit Serial Flash */
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+ cc->sflash.blocksize = 256;
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+ cc->sflash.numblocks = 512;
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+ break;
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+ case 0x14:
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+ /* Atmel AT45DB021 2Mbit Serial Flash */
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+ cc->sflash.blocksize = 256;
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+ cc->sflash.numblocks = 1024;
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+ break;
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+ case 0x1c:
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+ /* Atmel AT45DB041 4Mbit Serial Flash */
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+ cc->sflash.blocksize = 256;
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+ cc->sflash.numblocks = 2048;
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+ break;
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+ case 0x24:
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+ /* Atmel AT45DB081 8Mbit Serial Flash */
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+ cc->sflash.blocksize = 256;
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+ cc->sflash.numblocks = 4096;
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+ break;
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+ case 0x2c:
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+ /* Atmel AT45DB161 16Mbit Serial Flash */
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+ cc->sflash.blocksize = 512;
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+ cc->sflash.numblocks = 4096;
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+ break;
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+ case 0x34:
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+ /* Atmel AT45DB321 32Mbit Serial Flash */
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+ cc->sflash.blocksize = 512;
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+ cc->sflash.numblocks = 8192;
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+ break;
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+ case 0x3c:
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+ /* Atmel AT45DB642 64Mbit Serial Flash */
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+ cc->sflash.blocksize = 1024;
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+ cc->sflash.numblocks = 8192;
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+ break;
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+ }
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+ break;
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+ }
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+
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+ cc->sflash.size = cc->sflash.blocksize * cc->sflash.numblocks;
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+
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+ return cc->sflash.size ? 0 : -ENODEV;
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+}
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+
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+/* Read len bytes starting at offset into buf. Returns number of bytes read. */
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+int ssb_sflash_read(struct ssb_chipcommon *cc, u32 offset, u32 len,
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+ u8 *buf)
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+{
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+ u8 *from, *to;
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+ u32 cnt, i;
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+
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+ if (!len)
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+ return 0;
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+
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+ if ((offset + len) > cc->sflash.size)
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+ return -EINVAL;
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+
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+ if ((len >= 4) && (offset & 3))
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+ cnt = 4 - (offset & 3);
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+ else if ((len >= 4) && ((u32)buf & 3))
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+ cnt = 4 - ((u32)buf & 3);
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+ else
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+ cnt = len;
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+
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+
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+ if (cc->dev->id.revision == 12)
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+ from = (u8 *)KSEG1ADDR(SSB_FLASH2 + offset);
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+ else
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+ from = (u8 *)KSEG0ADDR(SSB_FLASH2 + offset);
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+
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+ to = (u8 *)buf;
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+
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+ if (cnt < 4) {
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+ for (i = 0; i < cnt; i++) {
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+ *to = readb(from);
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+ from++;
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+ to++;
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+ }
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+ return cnt;
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+ }
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+
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+ while (cnt >= 4) {
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+ *(u32 *)to = readl(from);
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+ from += 4;
|
||||
+ to += 4;
|
||||
+ cnt -= 4;
|
||||
+ }
|
||||
+
|
||||
+ return len - cnt;
|
||||
+}
|
||||
+
|
||||
+/* Poll for command completion. Returns zero when complete. */
|
||||
+int ssb_sflash_poll(struct ssb_chipcommon *cc, u32 offset)
|
||||
+{
|
||||
+ if (offset >= cc->sflash.size)
|
||||
+ return -22;
|
||||
+
|
||||
+ switch (cc->capabilities & SSB_CHIPCO_CAP_FLASHT) {
|
||||
+ case SSB_CHIPCO_FLASHT_STSER:
|
||||
+ /* Check for ST Write In Progress bit */
|
||||
+ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_RDSR);
|
||||
+ return chipco_read32(cc, SSB_CHIPCO_FLASHDATA)
|
||||
+ & SSB_CHIPCO_FLASHSTA_ST_WIP;
|
||||
+ case SSB_CHIPCO_FLASHT_ATSER:
|
||||
+ /* Check for Atmel Ready bit */
|
||||
+ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_AT_STATUS);
|
||||
+ return !(chipco_read32(cc, SSB_CHIPCO_FLASHDATA)
|
||||
+ & SSB_CHIPCO_FLASHSTA_AT_READY);
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+
|
||||
+static int sflash_st_write(struct ssb_chipcommon *cc, u32 offset, u32 len,
|
||||
+ const u8 *buf)
|
||||
+{
|
||||
+ struct ssb_bus *bus = cc->dev->bus;
|
||||
+ int ret = 0;
|
||||
+ bool is4712b0 = (bus->chip_id == 0x4712) && (bus->chip_rev == 3);
|
||||
+ u32 mask;
|
||||
+
|
||||
+
|
||||
+ /* Enable writes */
|
||||
+ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_WREN);
|
||||
+ if (is4712b0) {
|
||||
+ mask = 1 << 14;
|
||||
+ ssb_sflash_write_u8(cc, offset, *buf++);
|
||||
+ /* Set chip select */
|
||||
+ chipco_set32(cc, SSB_CHIPCO_GPIOOUT, mask);
|
||||
+ /* Issue a page program with the first byte */
|
||||
+ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_PP);
|
||||
+ ret = 1;
|
||||
+ offset++;
|
||||
+ len--;
|
||||
+ while (len > 0) {
|
||||
+ if ((offset & 255) == 0) {
|
||||
+ /* Page boundary, drop cs and return */
|
||||
+ chipco_mask32(cc, SSB_CHIPCO_GPIOOUT, ~mask);
|
||||
+ udelay(1);
|
||||
+ if (!ssb_sflash_poll(cc, offset)) {
|
||||
+ /* Flash rejected command */
|
||||
+ return -EAGAIN;
|
||||
+ }
|
||||
+ return ret;
|
||||
+ } else {
|
||||
+ /* Write single byte */
|
||||
+ ssb_sflash_cmd(cc, *buf++);
|
||||
+ }
|
||||
+ ret++;
|
||||
+ offset++;
|
||||
+ len--;
|
||||
+ }
|
||||
+ /* All done, drop cs */
|
||||
+ chipco_mask32(cc, SSB_CHIPCO_GPIOOUT, ~mask);
|
||||
+ udelay(1);
|
||||
+ if (!ssb_sflash_poll(cc, offset)) {
|
||||
+ /* Flash rejected command */
|
||||
+ return -EAGAIN;
|
||||
+ }
|
||||
+ } else if (cc->dev->id.revision >= 20) {
|
||||
+ ssb_sflash_write_u8(cc, offset, *buf++);
|
||||
+ /* Issue a page program with CSA bit set */
|
||||
+ ssb_sflash_cmd(cc,
|
||||
+ SSB_CHIPCO_FLASHCTL_ST_CSA |
|
||||
+ SSB_CHIPCO_FLASHCTL_ST_PP);
|
||||
+ ret = 1;
|
||||
+ offset++;
|
||||
+ len--;
|
||||
+ while (len > 0) {
|
||||
+ if ((offset & 255) == 0) {
|
||||
+ /* Page boundary, poll droping cs and return */
|
||||
+ chipco_write32(cc, SSB_CHIPCO_FLASHCTL, 0);
|
||||
+ udelay(1);
|
||||
+ if (!ssb_sflash_poll(cc, offset)) {
|
||||
+ /* Flash rejected command */
|
||||
+ return -EAGAIN;
|
||||
+ }
|
||||
+ return ret;
|
||||
+ } else {
|
||||
+ /* Write single byte */
|
||||
+ ssb_sflash_cmd(cc,
|
||||
+ SSB_CHIPCO_FLASHCTL_ST_CSA |
|
||||
+ *buf++);
|
||||
+ }
|
||||
+ ret++;
|
||||
+ offset++;
|
||||
+ len--;
|
||||
+ }
|
||||
+ /* All done, drop cs & poll */
|
||||
+ chipco_write32(cc, SSB_CHIPCO_FLASHCTL, 0);
|
||||
+ udelay(1);
|
||||
+ if (!ssb_sflash_poll(cc, offset)) {
|
||||
+ /* Flash rejected command */
|
||||
+ return -EAGAIN;
|
||||
+ }
|
||||
+ } else {
|
||||
+ ret = 1;
|
||||
+ ssb_sflash_write_u8(cc, offset, *buf);
|
||||
+ /* Page program */
|
||||
+ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_PP);
|
||||
+ }
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int sflash_at_write(struct ssb_chipcommon *cc, u32 offset, u32 len,
|
||||
+ const u8 *buf)
|
||||
+{
|
||||
+ struct ssb_sflash *sfl = &cc->sflash;
|
||||
+ u32 page, byte, mask;
|
||||
+ int ret = 0;
|
||||
+ mask = sfl->blocksize - 1;
|
||||
+ page = (offset & ~mask) << 1;
|
||||
+ byte = offset & mask;
|
||||
+ /* Read main memory page into buffer 1 */
|
||||
+ if (byte || (len < sfl->blocksize)) {
|
||||
+ int i = 100;
|
||||
+ chipco_write32(cc, SSB_CHIPCO_FLASHADDR, page);
|
||||
+ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_AT_BUF1_LOAD);
|
||||
+ /* 250 us for AT45DB321B */
|
||||
+ while (i > 0 && ssb_sflash_poll(cc, offset)) {
|
||||
+ udelay(10);
|
||||
+ i--;
|
||||
+ }
|
||||
+ BUG_ON(!ssb_sflash_poll(cc, offset));
|
||||
+ }
|
||||
+ /* Write into buffer 1 */
|
||||
+ for (ret = 0; (ret < (int)len) && (byte < sfl->blocksize); ret++) {
|
||||
+ ssb_sflash_write_u8(cc, byte++, *buf++);
|
||||
+ ssb_sflash_cmd(cc,
|
||||
+ SSB_CHIPCO_FLASHCTL_AT_BUF1_WRITE);
|
||||
+ }
|
||||
+ /* Write buffer 1 into main memory page */
|
||||
+ chipco_write32(cc, SSB_CHIPCO_FLASHADDR, page);
|
||||
+ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_AT_BUF1_PROGRAM);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+/* Write len bytes starting at offset into buf. Returns number of bytes
|
||||
+ * written. Caller should poll for completion.
|
||||
+ */
|
||||
+int ssb_sflash_write(struct ssb_chipcommon *cc, u32 offset, u32 len,
|
||||
+ const u8 *buf)
|
||||
+{
|
||||
+ struct ssb_sflash *sfl;
|
||||
+ int ret = 0, tries = NUM_RETRIES;
|
||||
+
|
||||
+ if (!len)
|
||||
+ return 0;
|
||||
+
|
||||
+ if ((offset + len) > cc->sflash.size)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ sfl = &cc->sflash;
|
||||
+ switch (cc->capabilities & SSB_CHIPCO_CAP_FLASHT) {
|
||||
+ case SSB_CHIPCO_FLASHT_STSER:
|
||||
+ do {
|
||||
+ ret = sflash_st_write(cc, offset, len, buf);
|
||||
+ tries--;
|
||||
+ } while (ret == -EAGAIN && tries > 0);
|
||||
+
|
||||
+ if (ret == -EAGAIN && tries == 0) {
|
||||
+ pr_info("ST Flash rejected write\n");
|
||||
+ ret = -EIO;
|
||||
+ }
|
||||
+ break;
|
||||
+ case SSB_CHIPCO_FLASHT_ATSER:
|
||||
+ ret = sflash_at_write(cc, offset, len, buf);
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+/* Erase a region. Returns number of bytes scheduled for erasure.
|
||||
+ * Caller should poll for completion.
|
||||
+ */
|
||||
+int ssb_sflash_erase(struct ssb_chipcommon *cc, u32 offset)
|
||||
+{
|
||||
+ struct ssb_sflash *sfl;
|
||||
+
|
||||
+ if (offset >= cc->sflash.size)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ sfl = &cc->sflash;
|
||||
+ switch (cc->capabilities & SSB_CHIPCO_CAP_FLASHT) {
|
||||
+ case SSB_CHIPCO_FLASHT_STSER:
|
||||
+ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_WREN);
|
||||
+ chipco_write32(cc, SSB_CHIPCO_FLASHADDR, offset);
|
||||
+ /* Newer flashes have "sub-sectors" which can be erased independently
|
||||
+ * with a new command: ST_SSE. The ST_SE command erases 64KB just as
|
||||
+ * before.
|
||||
+ */
|
||||
+ ssb_sflash_cmd(cc, (sfl->blocksize < (64 * 1024)) ? SSB_CHIPCO_FLASHCTL_ST_SSE : SSB_CHIPCO_FLASHCTL_ST_SE);
|
||||
+ return sfl->blocksize;
|
||||
+ case SSB_CHIPCO_FLASHT_ATSER:
|
||||
+ chipco_write32(cc, SSB_CHIPCO_FLASHADDR, offset << 1);
|
||||
+ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_AT_PAGE_ERASE);
|
||||
+ return sfl->blocksize;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+/*
|
||||
+ * writes the appropriate range of flash, a NULL buf simply erases
|
||||
+ * the region of flash
|
||||
+ */
|
||||
+int ssb_sflash_commit(struct ssb_chipcommon *cc, u32 offset, u32 len,
|
||||
+ const u8 *buf)
|
||||
+{
|
||||
+ struct ssb_sflash *sfl;
|
||||
+ u8 *block = NULL, *cur_ptr, *blk_ptr;
|
||||
+ u32 blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
|
||||
+ u32 blk_offset, blk_len, copied;
|
||||
+ int bytes, ret = 0;
|
||||
+
|
||||
+ /* Check address range */
|
||||
+ if (len <= 0)
|
||||
+ return 0;
|
||||
+
|
||||
+ sfl = &cc->sflash;
|
||||
+ if ((offset + len) > sfl->size)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ blocksize = sfl->blocksize;
|
||||
+ mask = blocksize - 1;
|
||||
+
|
||||
+ /* Allocate a block of mem */
|
||||
+ block = kmalloc(blocksize, GFP_KERNEL);
|
||||
+ if (!block)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ while (len) {
|
||||
+ /* Align offset */
|
||||
+ cur_offset = offset & ~mask;
|
||||
+ cur_length = blocksize;
|
||||
+ cur_ptr = block;
|
||||
+
|
||||
+ remainder = blocksize - (offset & mask);
|
||||
+ if (len < remainder)
|
||||
+ cur_retlen = len;
|
||||
+ else
|
||||
+ cur_retlen = remainder;
|
||||
+
|
||||
+ /* buf == NULL means erase only */
|
||||
+ if (buf) {
|
||||
+ /* Copy existing data into holding block if necessary */
|
||||
+ if ((offset & mask) || (len < blocksize)) {
|
||||
+ blk_offset = cur_offset;
|
||||
+ blk_len = cur_length;
|
||||
+ blk_ptr = cur_ptr;
|
||||
+
|
||||
+ /* Copy entire block */
|
||||
+ while (blk_len) {
|
||||
+ copied = ssb_sflash_read(cc,
|
||||
+ blk_offset,
|
||||
+ blk_len, blk_ptr);
|
||||
+ blk_offset += copied;
|
||||
+ blk_len -= copied;
|
||||
+ blk_ptr += copied;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ /* Copy input data into holding block */
|
||||
+ memcpy(cur_ptr + (offset & mask), buf, cur_retlen);
|
||||
+ }
|
||||
+
|
||||
+ /* Erase block */
|
||||
+ ret = ssb_sflash_erase(cc, cur_offset);
|
||||
+ if (ret < 0)
|
||||
+ goto done;
|
||||
+
|
||||
+ while (ssb_sflash_poll(cc, cur_offset));
|
||||
+
|
||||
+ /* buf == NULL means erase only */
|
||||
+ if (!buf) {
|
||||
+ offset += cur_retlen;
|
||||
+ len -= cur_retlen;
|
||||
+ continue;
|
||||
+ }
|
||||
+
|
||||
+ /* Write holding block */
|
||||
+ while (cur_length > 0) {
|
||||
+ bytes = ssb_sflash_write(cc, cur_offset,
|
||||
+ cur_length, cur_ptr);
|
||||
+
|
||||
+ if (bytes < 0) {
|
||||
+ ret = bytes;
|
||||
+ goto done;
|
||||
+ }
|
||||
+
|
||||
+ while (ssb_sflash_poll(cc, cur_offset))
|
||||
+ ;
|
||||
+
|
||||
+ cur_offset += bytes;
|
||||
+ cur_length -= bytes;
|
||||
+ cur_ptr += bytes;
|
||||
+ }
|
||||
+
|
||||
+ offset += cur_retlen;
|
||||
+ len -= cur_retlen;
|
||||
+ buf += cur_retlen;
|
||||
+ }
|
||||
+
|
||||
+ ret = len;
|
||||
+done:
|
||||
+ kfree(block);
|
||||
+ return ret;
|
||||
+}
|
||||
--- a/drivers/ssb/driver_mipscore.c
|
||||
+++ b/drivers/ssb/driver_mipscore.c
|
||||
@@ -193,7 +193,13 @@ static void ssb_mips_flash_detect(struct
|
||||
switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
|
||||
case SSB_CHIPCO_FLASHT_STSER:
|
||||
case SSB_CHIPCO_FLASHT_ATSER:
|
||||
+#ifdef CONFIG_SSB_SFLASH
|
||||
+ pr_info("found serial flash.\n");
|
||||
+ bus->chipco.flash_type = SSB_SFLASH;
|
||||
+ ssb_sflash_init(&bus->chipco);
|
||||
+#else
|
||||
pr_info("serial flash not supported.\n");
|
||||
+#endif /* CONFIG_SSB_SFLASH */
|
||||
break;
|
||||
case SSB_CHIPCO_FLASHT_PARA:
|
||||
pr_info("found parallel flash.\n");
|
||||
--- a/drivers/ssb/ssb_private.h
|
||||
+++ b/drivers/ssb/ssb_private.h
|
||||
@@ -192,6 +192,10 @@ extern int ssb_devices_freeze(struct ssb
|
||||
extern int ssb_devices_thaw(struct ssb_freeze_context *ctx);
|
||||
|
||||
|
||||
+#ifdef CONFIG_SSB_SFLASH
|
||||
+/* driver_chipcommon_sflash.c */
|
||||
+int ssb_sflash_init(struct ssb_chipcommon *cc);
|
||||
+#endif /* CONFIG_SSB_SFLASH */
|
||||
|
||||
/* b43_pci_bridge.c */
|
||||
#ifdef CONFIG_SSB_B43_PCI_BRIDGE
|
||||
--- a/include/linux/ssb/ssb_driver_chipcommon.h
|
||||
+++ b/include/linux/ssb/ssb_driver_chipcommon.h
|
||||
@@ -503,8 +503,10 @@
|
||||
#define SSB_CHIPCO_FLASHCTL_ST_PP 0x0302 /* Page Program */
|
||||
#define SSB_CHIPCO_FLASHCTL_ST_SE 0x02D8 /* Sector Erase */
|
||||
#define SSB_CHIPCO_FLASHCTL_ST_BE 0x00C7 /* Bulk Erase */
|
||||
-#define SSB_CHIPCO_FLASHCTL_ST_DP 0x00B9 /* Deep Power-down */
|
||||
-#define SSB_CHIPCO_FLASHCTL_ST_RSIG 0x03AB /* Read Electronic Signature */
|
||||
+#define SSB_CHIPCO_FLASHCTL_ST_DP 0x00D9 /* Deep Power-down */
|
||||
+#define SSB_CHIPCO_FLASHCTL_ST_RES 0x03AB /* Read Electronic Signature */
|
||||
+#define SSB_CHIPCO_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
|
||||
+#define SSB_CHIPCO_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
|
||||
|
||||
/* Status register bits for ST flashes */
|
||||
#define SSB_CHIPCO_FLASHSTA_ST_WIP 0x01 /* Write In Progress */
|
||||
@@ -585,6 +587,7 @@ struct ssb_chipcommon_pmu {
|
||||
#ifdef CONFIG_SSB_DRIVER_MIPS
|
||||
enum ssb_flash_type {
|
||||
SSB_PFLASH,
|
||||
+ SSB_SFLASH,
|
||||
};
|
||||
|
||||
struct ssb_pflash {
|
||||
@@ -592,6 +595,14 @@ struct ssb_pflash {
|
||||
u32 window;
|
||||
u32 window_size;
|
||||
};
|
||||
+
|
||||
+#ifdef CONFIG_SSB_SFLASH
|
||||
+struct ssb_sflash {
|
||||
+ u32 blocksize; /* Block size */
|
||||
+ u32 numblocks; /* Number of blocks */
|
||||
+ u32 size; /* Total size in bytes */
|
||||
+};
|
||||
+#endif /* CONFIG_SSB_SFLASH */
|
||||
#endif /* CONFIG_SSB_DRIVER_MIPS */
|
||||
|
||||
struct ssb_chipcommon {
|
||||
@@ -605,6 +616,9 @@ struct ssb_chipcommon {
|
||||
enum ssb_flash_type flash_type;
|
||||
union {
|
||||
struct ssb_pflash pflash;
|
||||
+#ifdef CONFIG_SSB_SFLASH
|
||||
+ struct ssb_sflash sflash;
|
||||
+#endif /* CONFIG_SSB_SFLASH */
|
||||
};
|
||||
#endif /* CONFIG_SSB_DRIVER_MIPS */
|
||||
};
|
||||
@@ -666,6 +680,18 @@ extern int ssb_chipco_serial_init(struct
|
||||
struct ssb_serial_port *ports);
|
||||
#endif /* CONFIG_SSB_SERIAL */
|
||||
|
||||
+#ifdef CONFIG_SSB_SFLASH
|
||||
+/* Chipcommon sflash support. */
|
||||
+int ssb_sflash_read(struct ssb_chipcommon *cc, u32 offset, u32 len,
|
||||
+ u8 *buf);
|
||||
+int ssb_sflash_poll(struct ssb_chipcommon *cc, u32 offset);
|
||||
+int ssb_sflash_write(struct ssb_chipcommon *cc, u32 offset, u32 len,
|
||||
+ const u8 *buf);
|
||||
+int ssb_sflash_erase(struct ssb_chipcommon *cc, u32 offset);
|
||||
+int ssb_sflash_commit(struct ssb_chipcommon *cc, u32 offset, u32 len,
|
||||
+ const u8 *buf);
|
||||
+#endif /* CONFIG_SSB_SFLASH */
|
||||
+
|
||||
/* PMU support */
|
||||
extern void ssb_pmu_init(struct ssb_chipcommon *cc);
|
||||
|
||||
@ -0,0 +1,193 @@
|
||||
From 4f314ac9edbc80897f158fdb4e1b1de8a2d0d432 Mon Sep 17 00:00:00 2001
|
||||
From: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
Date: Sun, 24 Jul 2011 21:10:49 +0200
|
||||
Subject: [PATCH 16/26] brcm47xx: add common interface for sflash
|
||||
|
||||
|
||||
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
---
|
||||
arch/mips/bcm47xx/Makefile | 2 +-
|
||||
arch/mips/bcm47xx/bus.c | 94 ++++++++++++++++++++++++++++++
|
||||
arch/mips/bcm47xx/setup.c | 8 +++
|
||||
arch/mips/include/asm/mach-bcm47xx/bus.h | 37 ++++++++++++
|
||||
4 files changed, 140 insertions(+), 1 deletions(-)
|
||||
create mode 100644 arch/mips/bcm47xx/bus.c
|
||||
create mode 100644 arch/mips/include/asm/mach-bcm47xx/bus.h
|
||||
|
||||
--- a/arch/mips/bcm47xx/Makefile
|
||||
+++ b/arch/mips/bcm47xx/Makefile
|
||||
@@ -3,5 +3,5 @@
|
||||
# under Linux.
|
||||
#
|
||||
|
||||
-obj-y += gpio.o irq.o nvram.o prom.o serial.o setup.o time.o
|
||||
+obj-y += gpio.o irq.o nvram.o prom.o serial.o setup.o time.o bus.o
|
||||
obj-$(CONFIG_BCM47XX_SSB) += wgt634u.o
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/bcm47xx/bus.c
|
||||
@@ -0,0 +1,94 @@
|
||||
+/*
|
||||
+ * BCM947xx nvram variable access
|
||||
+ *
|
||||
+ * Copyright (C) 2011 Hauke Mehrtens <hauke@hauke-m.de>
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License as published by the
|
||||
+ * Free Software Foundation; either version 2 of the License, or (at your
|
||||
+ * option) any later version.
|
||||
+ */
|
||||
+
|
||||
+#include <bus.h>
|
||||
+
|
||||
+static int bcm47xx_sflash_bcma_read(struct bcm47xx_sflash *dev, u32 offset, u32 len, u8 *buf)
|
||||
+{
|
||||
+ return bcma_sflash_read(dev->bcc, offset, len, buf);
|
||||
+}
|
||||
+
|
||||
+static int bcm47xx_sflash_bcma_poll(struct bcm47xx_sflash *dev, u32 offset)
|
||||
+{
|
||||
+ return bcma_sflash_poll(dev->bcc, offset);
|
||||
+}
|
||||
+
|
||||
+static int bcm47xx_sflash_bcma_write(struct bcm47xx_sflash *dev, u32 offset, u32 len, const u8 *buf)
|
||||
+{
|
||||
+ return bcma_sflash_write(dev->bcc, offset, len, buf);
|
||||
+}
|
||||
+
|
||||
+static int bcm47xx_sflash_bcma_erase(struct bcm47xx_sflash *dev, u32 offset)
|
||||
+{
|
||||
+ return bcma_sflash_erase(dev->bcc, offset);
|
||||
+}
|
||||
+
|
||||
+static int bcm47xx_sflash_bcma_commit(struct bcm47xx_sflash *dev, u32 offset, u32 len, const u8 *buf)
|
||||
+{
|
||||
+ return bcma_sflash_commit(dev->bcc, offset, len, buf);
|
||||
+}
|
||||
+
|
||||
+void bcm47xx_sflash_struct_bcma_init(struct bcm47xx_sflash *sflash, struct bcma_drv_cc *bcc)
|
||||
+{
|
||||
+ sflash->sflash_type = BCM47XX_BUS_TYPE_BCMA;
|
||||
+ sflash->bcc = bcc;
|
||||
+
|
||||
+ sflash->read = bcm47xx_sflash_bcma_read;
|
||||
+ sflash->poll = bcm47xx_sflash_bcma_poll;
|
||||
+ sflash->write = bcm47xx_sflash_bcma_write;
|
||||
+ sflash->erase = bcm47xx_sflash_bcma_erase;
|
||||
+ sflash->commit = bcm47xx_sflash_bcma_commit;
|
||||
+
|
||||
+ sflash->blocksize = bcc->sflash.blocksize;
|
||||
+ sflash->numblocks = bcc->sflash.numblocks;
|
||||
+ sflash->size = bcc->sflash.size;
|
||||
+}
|
||||
+
|
||||
+static int bcm47xx_sflash_ssb_read(struct bcm47xx_sflash *dev, u32 offset, u32 len, u8 *buf)
|
||||
+{
|
||||
+ return ssb_sflash_read(dev->scc, offset, len, buf);
|
||||
+}
|
||||
+
|
||||
+static int bcm47xx_sflash_ssb_poll(struct bcm47xx_sflash *dev, u32 offset)
|
||||
+{
|
||||
+ return ssb_sflash_poll(dev->scc, offset);
|
||||
+}
|
||||
+
|
||||
+static int bcm47xx_sflash_ssb_write(struct bcm47xx_sflash *dev, u32 offset, u32 len, const u8 *buf)
|
||||
+{
|
||||
+ return ssb_sflash_write(dev->scc, offset, len, buf);
|
||||
+}
|
||||
+
|
||||
+static int bcm47xx_sflash_ssb_erase(struct bcm47xx_sflash *dev, u32 offset)
|
||||
+{
|
||||
+ return ssb_sflash_erase(dev->scc, offset);
|
||||
+}
|
||||
+
|
||||
+static int bcm47xx_sflash_ssb_commit(struct bcm47xx_sflash *dev, u32 offset, u32 len, const u8 *buf)
|
||||
+{
|
||||
+ return ssb_sflash_commit(dev->scc, offset, len, buf);
|
||||
+}
|
||||
+
|
||||
+void bcm47xx_sflash_struct_ssb_init(struct bcm47xx_sflash *sflash, struct ssb_chipcommon *scc)
|
||||
+{
|
||||
+ sflash->sflash_type = BCM47XX_BUS_TYPE_SSB;
|
||||
+ sflash->scc = scc;
|
||||
+
|
||||
+ sflash->read = bcm47xx_sflash_ssb_read;
|
||||
+ sflash->poll = bcm47xx_sflash_ssb_poll;
|
||||
+ sflash->write = bcm47xx_sflash_ssb_write;
|
||||
+ sflash->erase = bcm47xx_sflash_ssb_erase;
|
||||
+ sflash->commit = bcm47xx_sflash_ssb_commit;
|
||||
+
|
||||
+ sflash->blocksize = scc->sflash.blocksize;
|
||||
+ sflash->numblocks = scc->sflash.numblocks;
|
||||
+ sflash->size = scc->sflash.size;
|
||||
+}
|
||||
--- a/arch/mips/bcm47xx/setup.c
|
||||
+++ b/arch/mips/bcm47xx/setup.c
|
||||
@@ -42,6 +42,8 @@ EXPORT_SYMBOL(bcm47xx_bus);
|
||||
enum bcm47xx_bus_type bcm47xx_bus_type;
|
||||
EXPORT_SYMBOL(bcm47xx_bus_type);
|
||||
|
||||
+struct bcm47xx_sflash bcm47xx_sflash;
|
||||
+
|
||||
static void bcm47xx_machine_restart(char *command)
|
||||
{
|
||||
printk(KERN_ALERT "Please stand by while rebooting the system...\n");
|
||||
@@ -290,6 +292,9 @@ static void __init bcm47xx_register_ssb(
|
||||
if (err)
|
||||
panic("Failed to initialize SSB bus (err %d)\n", err);
|
||||
|
||||
+ if (bcm47xx_bus.ssb.chipco.flash_type == SSB_SFLASH)
|
||||
+ bcm47xx_sflash_struct_ssb_init(&bcm47xx_sflash, &bcm47xx_bus.ssb.chipco);
|
||||
+
|
||||
mcore = &bcm47xx_bus.ssb.mipscore;
|
||||
if (nvram_getenv("kernel_args", buf, sizeof(buf)) >= 0) {
|
||||
if (strstr(buf, "console=ttyS1")) {
|
||||
@@ -314,6 +319,9 @@ static void __init bcm47xx_register_bcma
|
||||
err = bcma_host_soc_register(&bcm47xx_bus.bcma);
|
||||
if (err)
|
||||
panic("Failed to initialize BCMA bus (err %d)\n", err);
|
||||
+
|
||||
+ if (bcm47xx_bus.bcma.bus.drv_cc.flash_type == BCMA_SFLASH)
|
||||
+ bcm47xx_sflash_struct_bcma_init(&bcm47xx_sflash, &bcm47xx_bus.bcma.bus.drv_cc);
|
||||
}
|
||||
#endif
|
||||
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/include/asm/mach-bcm47xx/bus.h
|
||||
@@ -0,0 +1,37 @@
|
||||
+/*
|
||||
+ * BCM947xx nvram variable access
|
||||
+ *
|
||||
+ * Copyright (C) 2011 Hauke Mehrtens <hauke@hauke-m.de>
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License as published by the
|
||||
+ * Free Software Foundation; either version 2 of the License, or (at your
|
||||
+ * option) any later version.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/ssb/ssb.h>
|
||||
+#include <linux/bcma/bcma.h>
|
||||
+#include <bcm47xx.h>
|
||||
+
|
||||
+struct bcm47xx_sflash {
|
||||
+ enum bcm47xx_bus_type sflash_type;
|
||||
+ union {
|
||||
+ struct ssb_chipcommon *scc;
|
||||
+ struct bcma_drv_cc *bcc;
|
||||
+ };
|
||||
+
|
||||
+ int (*read)(struct bcm47xx_sflash *dev, u32 offset, u32 len, u8 *buf);
|
||||
+ int (*poll)(struct bcm47xx_sflash *dev, u32 offset);
|
||||
+ int (*write)(struct bcm47xx_sflash *dev, u32 offset, u32 len, const u8 *buf);
|
||||
+ int (*erase)(struct bcm47xx_sflash *dev, u32 offset);
|
||||
+ int (*commit)(struct bcm47xx_sflash *dev, u32 offset, u32 len, const u8 *buf);
|
||||
+
|
||||
+ u32 blocksize; /* Block size */
|
||||
+ u32 numblocks; /* Number of blocks */
|
||||
+ u32 size; /* Total size in bytes */
|
||||
+};
|
||||
+
|
||||
+void bcm47xx_sflash_struct_bcma_init(struct bcm47xx_sflash *sflash, struct bcma_drv_cc *bcc);
|
||||
+void bcm47xx_sflash_struct_ssb_init(struct bcm47xx_sflash *sflash, struct ssb_chipcommon *scc);
|
||||
+
|
||||
+extern struct bcm47xx_sflash bcm47xx_sflash;
|
||||
@ -1,74 +0,0 @@
|
||||
From 89b904335338c86ef2c40e7cc51e19673feb62c1 Mon Sep 17 00:00:00 2001
|
||||
From: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
Date: Sun, 17 Jul 2011 15:02:10 +0200
|
||||
Subject: [PATCH 17/22] bcm47xx: register flash drivers
|
||||
|
||||
|
||||
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
---
|
||||
arch/mips/bcm47xx/setup.c | 50 +++++++++++++++++++++++++++++++++++++++++++++
|
||||
1 files changed, 50 insertions(+), 0 deletions(-)
|
||||
|
||||
--- a/arch/mips/bcm47xx/setup.c
|
||||
+++ b/arch/mips/bcm47xx/setup.c
|
||||
@@ -30,6 +30,7 @@
|
||||
#include <linux/ssb/ssb.h>
|
||||
#include <linux/ssb/ssb_embedded.h>
|
||||
#include <linux/bcma/bcma_soc.h>
|
||||
+#include <linux/platform_device.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/time.h>
|
||||
@@ -357,3 +358,52 @@ static int __init bcm47xx_register_bus_c
|
||||
return 0;
|
||||
}
|
||||
device_initcall(bcm47xx_register_bus_complete);
|
||||
+
|
||||
+static struct resource bcm47xx_pflash_resource = {
|
||||
+ .name = "para",
|
||||
+ .start = 0,
|
||||
+ .end = 0,
|
||||
+ .flags = 0,
|
||||
+};
|
||||
+
|
||||
+static struct platform_device bcm47xx_pflash = {
|
||||
+ .name = "bcm47xx_pflash",
|
||||
+ .resource = &bcm47xx_pflash_resource,
|
||||
+ .num_resources = 1,
|
||||
+};
|
||||
+
|
||||
+static struct resource bcm47xx_sflash_resource = {
|
||||
+ .name = "serial",
|
||||
+ .start = 0,
|
||||
+ .end = 0,
|
||||
+ .flags = 0,
|
||||
+};
|
||||
+
|
||||
+static struct platform_device bcm47xx_sflash = {
|
||||
+ .name = "bcm47xx_sflash",
|
||||
+ .resource = &bcm47xx_sflash_resource,
|
||||
+ .num_resources = 1,
|
||||
+};
|
||||
+
|
||||
+static int __init bcm47xx_register_flash(void)
|
||||
+{
|
||||
+ switch (bcm47xx_active_bus_type) {
|
||||
+#ifdef CONFIG_BCM47XX_SSB
|
||||
+ case BCM47XX_BUS_TYPE_SSB:
|
||||
+ return platform_device_register(&bcm47xx_pflash);
|
||||
+#endif
|
||||
+#ifdef CONFIG_BCM47XX_BCMA
|
||||
+ case BCM47XX_BUS_TYPE_BCMA:
|
||||
+ if (bcm47xx_bus.bcma.bus.drv_cc.flash_type == BCMA_PFLASH) {
|
||||
+ return platform_device_register(&bcm47xx_pflash);
|
||||
+ } else if (bcm47xx_bus.bcma.bus.drv_cc.flash_type == BCMA_SFLASH) {
|
||||
+ return platform_device_register(&bcm47xx_sflash);
|
||||
+ } else {
|
||||
+ printk(KERN_ERR "No flash device found\n");
|
||||
+ return -1;
|
||||
+ }
|
||||
+#endif
|
||||
+ }
|
||||
+ return 0;
|
||||
+}
|
||||
+fs_initcall(bcm47xx_register_flash);
|
||||
@ -1,29 +0,0 @@
|
||||
From 1b23f310d4a7d24efe5dffbbde6b2b84252e2d7b Mon Sep 17 00:00:00 2001
|
||||
From: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
Date: Fri, 22 Jul 2011 14:18:21 +0200
|
||||
Subject: [PATCH 19/22] bcma: to not route irqs on non pci devices
|
||||
|
||||
|
||||
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
---
|
||||
drivers/bcma/driver_pci.c | 9 ++++++++-
|
||||
1 files changed, 8 insertions(+), 1 deletions(-)
|
||||
|
||||
--- a/drivers/bcma/driver_pci.c
|
||||
+++ b/drivers/bcma/driver_pci.c
|
||||
@@ -208,7 +208,14 @@ int bcma_core_pci_irq_ctl(struct bcma_dr
|
||||
{
|
||||
struct pci_dev *pdev = pc->core->bus->host_pci;
|
||||
u32 coremask, tmp;
|
||||
- int err;
|
||||
+ int err = 0;
|
||||
+
|
||||
+ if (core->bus->hosttype != BCMA_HOSTTYPE_PCI) {
|
||||
+ /* This bcma device is not on a PCI host-bus. So the IRQs are
|
||||
+ * not routed through the PCI core.
|
||||
+ * So we must not enable routing through the PCI core. */
|
||||
+ goto out;
|
||||
+ }
|
||||
|
||||
err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp);
|
||||
if (err)
|
||||
@ -0,0 +1,100 @@
|
||||
From 64f3d068654589d6114048ac5933cd4498706cfc Mon Sep 17 00:00:00 2001
|
||||
From: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
Date: Sun, 17 Jul 2011 15:02:10 +0200
|
||||
Subject: [PATCH 20/26] bcm47xx: register flash drivers
|
||||
|
||||
|
||||
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
---
|
||||
arch/mips/bcm47xx/setup.c | 72 +++++++++++++++++++++++++++++++++++++++++++++
|
||||
1 files changed, 72 insertions(+), 0 deletions(-)
|
||||
|
||||
--- a/arch/mips/bcm47xx/setup.c
|
||||
+++ b/arch/mips/bcm47xx/setup.c
|
||||
@@ -30,10 +30,12 @@
|
||||
#include <linux/ssb/ssb.h>
|
||||
#include <linux/ssb/ssb_embedded.h>
|
||||
#include <linux/bcma/bcma_soc.h>
|
||||
+#include <linux/platform_device.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/time.h>
|
||||
#include <bcm47xx.h>
|
||||
+#include <bus.h>
|
||||
#include <asm/mach-bcm47xx/nvram.h>
|
||||
|
||||
union bcm47xx_bus bcm47xx_bus;
|
||||
@@ -365,3 +367,73 @@ static int __init bcm47xx_register_bus_c
|
||||
return 0;
|
||||
}
|
||||
device_initcall(bcm47xx_register_bus_complete);
|
||||
+
|
||||
+static struct resource bcm47xx_pflash_resource = {
|
||||
+ .name = "bcm47xx_pflash",
|
||||
+ .start = 0,
|
||||
+ .end = 0,
|
||||
+ .flags = 0,
|
||||
+};
|
||||
+
|
||||
+static struct platform_device bcm47xx_pflash_dev = {
|
||||
+ .name = "bcm47xx_pflash",
|
||||
+ .resource = &bcm47xx_pflash_resource,
|
||||
+ .num_resources = 1,
|
||||
+};
|
||||
+
|
||||
+static struct resource bcm47xx_sflash_resource = {
|
||||
+ .name = "bcm47xx_sflash",
|
||||
+ .start = 0,
|
||||
+ .end = 0,
|
||||
+ .flags = 0,
|
||||
+};
|
||||
+
|
||||
+static struct platform_device bcm47xx_sflash_dev = {
|
||||
+ .name = "bcm47xx_sflash",
|
||||
+ .resource = &bcm47xx_sflash_resource,
|
||||
+ .num_resources = 1,
|
||||
+};
|
||||
+
|
||||
+static int __init bcm47xx_register_flash(void)
|
||||
+{
|
||||
+#ifdef CONFIG_BCM47XX_SSB
|
||||
+ struct ssb_chipcommon *chipco;
|
||||
+#endif
|
||||
+#ifdef CONFIG_BCM47XX_BCMA
|
||||
+ struct bcma_drv_cc *drv_cc;
|
||||
+#endif
|
||||
+ switch (bcm47xx_bus_type) {
|
||||
+#ifdef CONFIG_BCM47XX_SSB
|
||||
+ case BCM47XX_BUS_TYPE_SSB:
|
||||
+ chipco = &bcm47xx_bus.ssb.chipco;
|
||||
+ if (chipco->flash_type == SSB_PFLASH) {
|
||||
+ bcm47xx_pflash_resource.start = chipco->pflash.window;
|
||||
+ bcm47xx_pflash_resource.end = chipco->pflash.window + chipco->pflash.window_size;
|
||||
+ return platform_device_register(&bcm47xx_pflash_dev);
|
||||
+ } else if (chipco->flash_type == SSB_SFLASH) {
|
||||
+ bcm47xx_sflash_dev.dev.platform_data = &bcm47xx_sflash;
|
||||
+ return platform_device_register(&bcm47xx_sflash_dev);
|
||||
+ } else {
|
||||
+ printk(KERN_ERR "No flash device found\n");
|
||||
+ return -1;
|
||||
+ }
|
||||
+#endif
|
||||
+#ifdef CONFIG_BCM47XX_BCMA
|
||||
+ case BCM47XX_BUS_TYPE_BCMA:
|
||||
+ drv_cc = &bcm47xx_bus.bcma.bus.drv_cc;
|
||||
+ if (drv_cc->flash_type == BCMA_PFLASH) {
|
||||
+ bcm47xx_pflash_resource.start = drv_cc->pflash.window;
|
||||
+ bcm47xx_pflash_resource.end = drv_cc->pflash.window + drv_cc->pflash.window_size;
|
||||
+ return platform_device_register(&bcm47xx_pflash_dev);
|
||||
+ } else if (drv_cc->flash_type == BCMA_SFLASH) {
|
||||
+ bcm47xx_sflash_dev.dev.platform_data = &bcm47xx_sflash;
|
||||
+ return platform_device_register(&bcm47xx_sflash_dev);
|
||||
+ } else {
|
||||
+ printk(KERN_ERR "No flash device found\n");
|
||||
+ return -1;
|
||||
+ }
|
||||
+#endif
|
||||
+ }
|
||||
+ return -1;
|
||||
+}
|
||||
+fs_initcall(bcm47xx_register_flash);
|
||||
@ -1,37 +0,0 @@
|
||||
From f3007275d7706afb1381adb0003f3ba69d359c8f Mon Sep 17 00:00:00 2001
|
||||
From: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
Date: Fri, 22 Jul 2011 17:09:36 +0200
|
||||
Subject: [PATCH 20/22] bcma: small fixes needed to get b43 up with SoC
|
||||
|
||||
When using an SoC these small cahnges are neede to get it up
|
||||
|
||||
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
---
|
||||
drivers/bcma/core.c | 2 ++
|
||||
drivers/bcma/main.c | 3 +++
|
||||
2 files changed, 5 insertions(+), 0 deletions(-)
|
||||
|
||||
--- a/drivers/bcma/core.c
|
||||
+++ b/drivers/bcma/core.c
|
||||
@@ -110,6 +110,8 @@ EXPORT_SYMBOL_GPL(bcma_core_pll_ctl);
|
||||
u32 bcma_core_dma_translation(struct bcma_device *core)
|
||||
{
|
||||
switch (core->bus->hosttype) {
|
||||
+ case BCMA_HOSTTYPE_SOC:
|
||||
+ return 0;
|
||||
case BCMA_HOSTTYPE_PCI:
|
||||
if (bcma_aread32(core, BCMA_IOST) & BCMA_IOST_DMA64)
|
||||
return BCMA_DMA_TRANSLATION_DMA64_CMT;
|
||||
--- a/drivers/bcma/main.c
|
||||
+++ b/drivers/bcma/main.c
|
||||
@@ -99,7 +99,10 @@ static int bcma_register_cores(struct bc
|
||||
core->irq = bus->host_pci->irq;
|
||||
break;
|
||||
case BCMA_HOSTTYPE_SDIO:
|
||||
+ break;
|
||||
case BCMA_HOSTTYPE_SOC:
|
||||
+ core->dev.dma_mask = &core->dev.coherent_dma_mask;
|
||||
+ core->dma_dev = &core->dev;
|
||||
break;
|
||||
}
|
||||
|
||||
@ -0,0 +1,51 @@
|
||||
From 3e889f1cf928c6d87229761a0bc4c18c775a988b Mon Sep 17 00:00:00 2001
|
||||
From: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
Date: Sun, 17 Jul 2011 21:13:32 +0200
|
||||
Subject: [PATCH 21/26] add workarround for wndr3400
|
||||
|
||||
|
||||
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
---
|
||||
drivers/mtd/bcm47xxpart.c | 17 ++++++++++++-----
|
||||
1 files changed, 12 insertions(+), 5 deletions(-)
|
||||
|
||||
--- a/drivers/mtd/bcm47xxpart.c
|
||||
+++ b/drivers/mtd/bcm47xxpart.c
|
||||
@@ -78,11 +78,12 @@ struct trx_header {
|
||||
|
||||
#define NVRAM_SPACE 0x8000
|
||||
|
||||
-#define ROUTER_NETGEAR_WGR614L 1
|
||||
-#define ROUTER_NETGEAR_WNR834B 2
|
||||
-#define ROUTER_NETGEAR_WNDR3300 3
|
||||
-#define ROUTER_NETGEAR_WNR3500L 4
|
||||
-#define ROUTER_SIMPLETECH_SIMPLESHARE 5
|
||||
+#define ROUTER_NETGEAR_WGR614L 1
|
||||
+#define ROUTER_NETGEAR_WNR834B 2
|
||||
+#define ROUTER_NETGEAR_WNDR3300 3
|
||||
+#define ROUTER_NETGEAR_WNR3500L 4
|
||||
+#define ROUTER_SIMPLETECH_SIMPLESHARE 5
|
||||
+#define ROUTER_NETGEAR_WNDR3400 6
|
||||
|
||||
static struct mtd_partition bcm47xx_parts[] = {
|
||||
{ name: "cfe", offset:0, size:0, mask_flags:MTD_WRITEABLE, },
|
||||
@@ -400,6 +401,11 @@ static int get_router(void)
|
||||
return ROUTER_NETGEAR_WNR3500L;
|
||||
}
|
||||
|
||||
+ if (boardnum == 1 && boardtype == 0xb4cf && boardrev == 0x1100) {
|
||||
+ /* Netgear WNDR3400 */
|
||||
+ return ROUTER_NETGEAR_WNDR3400;
|
||||
+ }
|
||||
+
|
||||
if (boardtype == 0x042f
|
||||
&& boardrev == 0x10
|
||||
&& boardflags == 0
|
||||
@@ -440,6 +446,7 @@ static int parse_bcm47xx_partitions(stru
|
||||
case ROUTER_NETGEAR_WNR834B:
|
||||
case ROUTER_NETGEAR_WNDR3300:
|
||||
case ROUTER_NETGEAR_WNR3500L:
|
||||
+ case ROUTER_NETGEAR_WNDR3400:
|
||||
/* Netgear: checksum is @ 0x003AFFF8 for 4M flash or checksum
|
||||
* is @ 0x007AFFF8 for 8M flash
|
||||
*/
|
||||
@ -1,7 +1,7 @@
|
||||
From 6dd27601bee9b3c26cdb67246b6da51dd696ac34 Mon Sep 17 00:00:00 2001
|
||||
From e6730c06cfc827d715f43e9bd276ae939bb86af9 Mon Sep 17 00:00:00 2001
|
||||
From: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
Date: Fri, 22 Jul 2011 17:11:51 +0200
|
||||
Subject: [PATCH 22/22] bcma: use randoom mac address as long as reading it out does not work
|
||||
Subject: [PATCH 23/26] bcma: use randoom mac address as long as reading it out does not work
|
||||
|
||||
|
||||
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
@ -0,0 +1,118 @@
|
||||
From 1d693b2c9d5943cbe938f879041b837cd004737f Mon Sep 17 00:00:00 2001
|
||||
From: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
Date: Sat, 23 Jul 2011 18:29:38 +0200
|
||||
Subject: [PATCH 25/26] bcm47xx: read nvram from sflash
|
||||
|
||||
bcm47xx: add sflash support to nvram
|
||||
|
||||
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
---
|
||||
arch/mips/bcm47xx/nvram.c | 86 +++++++++++++++++++++++++++++++++++++++++++-
|
||||
1 files changed, 84 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/arch/mips/bcm47xx/nvram.c
|
||||
+++ b/arch/mips/bcm47xx/nvram.c
|
||||
@@ -20,11 +20,12 @@
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/mach-bcm47xx/nvram.h>
|
||||
#include <asm/mach-bcm47xx/bcm47xx.h>
|
||||
+#include <asm/mach-bcm47xx/bus.h>
|
||||
|
||||
static char nvram_buf[NVRAM_SPACE];
|
||||
|
||||
/* Probe for NVRAM header */
|
||||
-static void early_nvram_init(void)
|
||||
+static void early_nvram_init_pflash(void)
|
||||
{
|
||||
#ifdef CONFIG_BCM47XX_SSB
|
||||
struct ssb_chipcommon *ssb_cc;
|
||||
@@ -86,7 +87,88 @@ found:
|
||||
for (i = 0; i < sizeof(struct nvram_header); i += 4)
|
||||
*dst++ = *src++;
|
||||
for (; i < header->len && i < NVRAM_SPACE; i += 4)
|
||||
- *dst++ = le32_to_cpu(*src++);
|
||||
+ *dst++ = *src++;
|
||||
+}
|
||||
+
|
||||
+static int early_nvram_init_sflash(void)
|
||||
+{
|
||||
+ struct nvram_header header;
|
||||
+ u32 off;
|
||||
+ int ret;
|
||||
+ char *dst;
|
||||
+ int len;
|
||||
+
|
||||
+ /* check if the struct is already initilized */
|
||||
+ if (!bcm47xx_sflash.size)
|
||||
+ return -1;
|
||||
+
|
||||
+ off = FLASH_MIN;
|
||||
+ while (off <= bcm47xx_sflash.size) {
|
||||
+ ret = bcm47xx_sflash.read(&bcm47xx_sflash, off - NVRAM_SPACE, sizeof(header), (u8 *)&header);
|
||||
+ if (ret != sizeof(header))
|
||||
+ return ret;
|
||||
+ if (header.magic == NVRAM_HEADER)
|
||||
+ goto found;
|
||||
+ off <<= 1;
|
||||
+ }
|
||||
+
|
||||
+ off = FLASH_MIN;
|
||||
+ while (off <= bcm47xx_sflash.size) {
|
||||
+ ret = bcm47xx_sflash.read(&bcm47xx_sflash, off - (2 * NVRAM_SPACE), sizeof(header), (u8 *)&header);
|
||||
+ if (ret != sizeof(header))
|
||||
+ return ret;
|
||||
+ if (header.magic == NVRAM_HEADER)
|
||||
+ goto found;
|
||||
+ off <<= 1;
|
||||
+ }
|
||||
+ return -1;
|
||||
+
|
||||
+found:
|
||||
+ len = NVRAM_SPACE;
|
||||
+ dst = nvram_buf;
|
||||
+ while (len) {
|
||||
+ ret = bcm47xx_sflash.read(&bcm47xx_sflash, off - (2 * NVRAM_SPACE), len, dst);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+ off += ret;
|
||||
+ len -= ret;
|
||||
+ dst += ret;
|
||||
+ }
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void early_nvram_init(void)
|
||||
+{
|
||||
+ int err = 0;
|
||||
+
|
||||
+ switch (bcm47xx_bus_type) {
|
||||
+#ifdef CONFIG_BCM47XX_SSB
|
||||
+ case BCM47XX_BUS_TYPE_SSB:
|
||||
+ if (bcm47xx_bus.ssb.chipco.flash_type == SSB_PFLASH) {
|
||||
+ early_nvram_init_pflash();
|
||||
+ } else if (bcm47xx_bus.ssb.chipco.flash_type == SSB_SFLASH) {
|
||||
+ err = early_nvram_init_sflash();
|
||||
+ if (err < 0)
|
||||
+ printk(KERN_WARNING "can not read from flash: %i\n", err);
|
||||
+ } else {
|
||||
+ printk(KERN_WARNING "unknow flash type\n");
|
||||
+ }
|
||||
+ break;
|
||||
+#endif
|
||||
+#ifdef CONFIG_BCM47XX_BCMA
|
||||
+ case BCM47XX_BUS_TYPE_BCMA:
|
||||
+ if (bcm47xx_bus.bcma.bus.drv_cc.flash_type == BCMA_PFLASH) {
|
||||
+ early_nvram_init_pflash();
|
||||
+ } else if (bcm47xx_bus.bcma.bus.drv_cc.flash_type == BCMA_SFLASH) {
|
||||
+ err = early_nvram_init_sflash();
|
||||
+ if (err < 0)
|
||||
+ printk(KERN_WARNING "can not read from flash: %i\n", err);
|
||||
+ } else {
|
||||
+ printk(KERN_WARNING "unknow flash type\n");
|
||||
+ }
|
||||
+ break;
|
||||
+#endif
|
||||
+ }
|
||||
}
|
||||
|
||||
int nvram_getenv(char *name, char *val, size_t val_len)
|
||||
@ -0,0 +1,47 @@
|
||||
From f6e41db3ee7ead99e1398def222c14893fc265de Mon Sep 17 00:00:00 2001
|
||||
From: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
Date: Thu, 4 Aug 2011 21:09:48 +0200
|
||||
Subject: [PATCH 26/26] bcma: export needed gpio functions
|
||||
|
||||
|
||||
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
---
|
||||
drivers/bcma/driver_chipcommon.c | 5 +++++
|
||||
1 files changed, 5 insertions(+), 0 deletions(-)
|
||||
|
||||
--- a/drivers/bcma/driver_chipcommon.c
|
||||
+++ b/drivers/bcma/driver_chipcommon.c
|
||||
@@ -80,16 +80,19 @@ u32 bcma_chipco_gpio_in(struct bcma_drv_
|
||||
{
|
||||
return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask;
|
||||
}
|
||||
+EXPORT_SYMBOL_GPL(bcma_chipco_gpio_in);
|
||||
|
||||
u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
|
||||
{
|
||||
return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
|
||||
}
|
||||
+EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out);
|
||||
|
||||
u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
|
||||
{
|
||||
return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
|
||||
}
|
||||
+EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen);
|
||||
|
||||
u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
|
||||
{
|
||||
@@ -101,11 +104,13 @@ u32 bcma_chipco_gpio_intmask(struct bcma
|
||||
{
|
||||
return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
|
||||
}
|
||||
+EXPORT_SYMBOL_GPL(bcma_chipco_gpio_intmask);
|
||||
|
||||
u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
|
||||
{
|
||||
return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
|
||||
}
|
||||
+EXPORT_SYMBOL_GPL(bcma_chipco_gpio_polarity);
|
||||
|
||||
#ifdef CONFIG_BCMA_DRIVER_MIPS
|
||||
void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
|
||||
Loading…
Reference in New Issue