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ar8216: rework/fix AR8337 MAC swap handling

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In r45970 the MAC swap handling was made opt-in, however some boards
have been forgotten during the conversion. Since the reference design
uses this MAC swapping, and pretty much all known boards using this chip
seem to do so too, enabling the swapping is a more reasonable default
than leaving it disabled.

Change the code to still allow boards to opt-out of this.

Signed-off-by: Felix Fietkau <nbd@openwrt.org>

SVN-Revision: 47956
v19.07.3_mercusys_ac12_duma
Felix Fietkau 9 years ago
parent de50527a38
commit 814d70b2fd
7 changed files with 4 additions and 9 deletions
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1
target/linux/ar71xx/files/arch/mips/ath79/mach-epg5000.c
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@ -98,7 +98,6 @@ static struct ar8327_pad_cfg epg5000_ar8327_pad0_cfg = {
.rxclk_delay_en = true,
.txclk_delay_sel = AR8327_CLK_DELAY_SEL2,
.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
.mac06_exchange_en = true,
};
static struct ar8327_platform_data epg5000_ar8327_data = {

1
target/linux/ar71xx/files/arch/mips/ath79/mach-esr1750.c
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@ -97,7 +97,6 @@ static struct ar8327_pad_cfg esr1750_ar8327_pad0_cfg = {
.rxclk_delay_en = true,
.txclk_delay_sel = AR8327_CLK_DELAY_SEL2,
.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
.mac06_exchange_en = true,
};
static struct ar8327_platform_data esr1750_ar8327_data = {

1
target/linux/ar71xx/files/arch/mips/ath79/mach-f9k1115v2.c
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@ -98,7 +98,6 @@ static struct ar8327_pad_cfg f9k1115v2_ar8327_pad0_cfg = {
.rxclk_delay_en = true,
.txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
.mac06_exchange_en = true,
};
static struct ar8327_pad_cfg f9k1115v2_ar8327_pad6_cfg = {

1
target/linux/ar71xx/files/arch/mips/ath79/mach-nbg6716.c
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@ -320,7 +320,6 @@ static void __init nbg6716_010_setup(void)
nbg6716_ar8327_pad0_cfg.rxclk_delay_en = true;
nbg6716_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
nbg6716_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
nbg6716_ar8327_pad0_cfg.mac06_exchange_en = true;
/* GMAC6 of the AR8337 switch is connected to GMAC1 via SGMII */
nbg6716_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII;

1
target/linux/ar71xx/files/arch/mips/ath79/mach-wlr8100.c
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@ -186,7 +186,6 @@ static void __init wlr8100_010_setup(void)
wlr8100_ar8327_pad0_cfg.rxclk_delay_en = true;
wlr8100_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
wlr8100_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
wlr8100_ar8327_pad0_cfg.mac06_exchange_en = true;
/* GMAC6 of the AR8337 switch is connected to GMAC1 via SGMII */
wlr8100_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII;

6
target/linux/generic/files/drivers/net/phy/ar8327.c
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@ -124,9 +124,6 @@ ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
break;
}
if (cfg->mac06_exchange_en)
t |= AR8337_PAD_MAC06_EXCHANGE_EN;
return t;
}
@ -511,7 +508,10 @@ ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
t = ar8327_get_pad_cfg(pdata->pad0_cfg);
if (chip_is_ar8337(priv) && !pdata->pad0_cfg->mac06_exchange_dis)
t |= AR8337_PAD_MAC06_EXCHANGE_EN;
ar8xxx_write(priv, AR8327_REG_PAD0_MODE, t);
t = ar8327_get_pad_cfg(pdata->pad5_cfg);
ar8xxx_write(priv, AR8327_REG_PAD5_MODE, t);
t = ar8327_get_pad_cfg(pdata->pad6_cfg);

2
target/linux/generic/files/include/linux/ar8216_platform.h
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@ -47,7 +47,7 @@ struct ar8327_pad_cfg {
bool sgmii_delay_en;
enum ar8327_clk_delay_sel txclk_delay_sel;
enum ar8327_clk_delay_sel rxclk_delay_sel;
bool mac06_exchange_en;
bool mac06_exchange_dis;
};
enum ar8327_port_speed {

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