lantiq: add Linux 5.4 support as testing kernel version
Switch to the mainline Lantiq PCIe PHY driver and update the vr9.dtsi accordingly. The Lantiq IRQ SMP support added upstream required changes to the SoC dtsi as well. Following changes are made to the Lantiq kernel patches: 0005-lantiq_etop-pass-struct-device-to-DMA-API-functions.patch 0006-MIPS-lantiq-pass-struct-device-to-DMA-API-functions.patch applied upstream 0008-MIPS-lantiq-backport-old-timer-code.patch access_ok API update because it lost it's type (which was the first) parameter in upstream commit 96d4f267e40f95 ("Remove 'type' argument from access_ok() function") 0024-MIPS-lantiq-autoselect-soc-rev-matching-fw.patch merged into 0026-MIPS-lantiq-Add-GPHY-Firmware-loader.patch 0024-MIPS-lantiq-revert-DSA-switch-driver-PMU-clock-chang.patch revert upstream changes required for upstream xrx200 ethernet and xrx200 (DSA) switch driver but breaking our driver 0026-MIPS-lantiq-Add-GPHY-Firmware-loader.patch required for our driver but dropped upstream, add former upstream version 0028-NET-lantiq-various-etop-fixes.patch now has to use the phy_set_max_speed API instead of modifying phydev->supported. Also call ltq_dma_enable_irq() in ltq_etop_open() based on upstream commit cc973aecf0b054 ("MIPS: lantiq: Do not enable IRQs in dma open") Signed-off-by: Mathias Kresin <dev@kresin.me> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>master
parent
3d5d56487d
commit
6bf179b270
@ -1,12 +1,10 @@
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# CONFIG_MFD_CORE is not set
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CONFIG_MTD_NAND=y
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CONFIG_MTD_NAND_ECC=y
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CONFIG_MTD_NAND_CORE=y
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CONFIG_MTD_NAND_ECC_SW_HAMMING=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_MTD_SPLIT_FIRMWARE_NAME="linux"
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CONFIG_PINCTRL_FALCON=y
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# CONFIG_PSB6970_PHY is not set
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# CONFIG_RESET_LANTIQ is not set
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# CONFIG_RTL8366_SMI is not set
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CONFIG_SOC_FALCON=y
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# CONFIG_SOC_TYPE_XWAY is not set
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# CONFIG_SOC_XWAY is not set
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CONFIG_SPI_FALCON=y
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@ -1,43 +0,0 @@
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From 74e0deb89a8ba27c132b1f0e08643e215b5c1f92 Mon Sep 17 00:00:00 2001
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From: Christoph Hellwig <hch@lst.de>
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Date: Mon, 11 Feb 2019 14:20:00 +0100
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Subject: [PATCH] lantiq_etop: pass struct device to DMA API functions
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The DMA API generally relies on a struct device to work properly, and
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only barely works without one for legacy reasons. Pass the easily
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available struct device from the platform_device to remedy this.
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Note this driver seems to lack dma_unmap_* calls entirely, but fixing
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that is left for another time.
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Signed-off-by: Christoph Hellwig <hch@lst.de>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/ethernet/lantiq_etop.c | 6 ++++--
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1 file changed, 4 insertions(+), 2 deletions(-)
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--- a/drivers/net/ethernet/lantiq_etop.c
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+++ b/drivers/net/ethernet/lantiq_etop.c
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@@ -112,10 +112,12 @@ struct ltq_etop_priv {
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static int
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ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
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{
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+ struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
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+
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ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
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if (!ch->skb[ch->dma.desc])
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return -ENOMEM;
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- ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
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+ ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(&priv->pdev->dev,
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ch->skb[ch->dma.desc]->data, MAX_DMA_DATA_LEN,
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DMA_FROM_DEVICE);
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ch->dma.desc_base[ch->dma.desc].addr =
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@@ -493,7 +495,7 @@ ltq_etop_tx(struct sk_buff *skb, struct
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netif_trans_update(dev);
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spin_lock_irqsave(&priv->lock, flags);
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- desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len,
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+ desc->addr = ((unsigned int) dma_map_single(&priv->pdev->dev, skb->data, len,
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DMA_TO_DEVICE)) - byte_offset;
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wmb();
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desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
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@ -1,50 +0,0 @@
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From 74f03104ed465ff71b11076ef620e4eaa53dbf74 Mon Sep 17 00:00:00 2001
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From: Christoph Hellwig <hch@lst.de>
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Date: Fri, 1 Feb 2019 09:47:44 +0100
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Subject: [PATCH] MIPS: lantiq: pass struct device to DMA API functions
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The DMA API generally relies on a struct device to work properly, and
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only barely works without one for legacy reasons. Pass the easily
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available struct device from the platform_device to remedy this.
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Also use GFP_KERNEL instead of GFP_ATOMIC as the gfp_t for the memory
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allocation, as we aren't in interrupt context or under a lock.
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Note that this whole function looks somewhat bogus given that we never
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even look at the returned dma address, and the CPHYSADDR magic on
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a returned noncached mapping looks "interesting". But I'll leave
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that to people more familiar with the code to sort out.
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Signed-off-by: Christoph Hellwig <hch@lst.de>
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Signed-off-by: Paul Burton <paul.burton@mips.com>
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Cc: John Crispin <john@phrozen.org>
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Cc: Vinod Koul <vkoul@kernel.org>
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Cc: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
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Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
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Cc: Sudip Mukherjee <sudipm.mukherjee@gmail.com>
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Cc: Felipe Balbi <balbi@kernel.org>
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Cc: linux-mips@vger.kernel.org
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Cc: linux-kernel@vger.kernel.org
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Cc: dmaengine@vger.kernel.org
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Cc: netdev@vger.kernel.org
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Cc: linux-usb@vger.kernel.org
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Cc: linux-fbdev@vger.kernel.org
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Cc: alsa-devel@alsa-project.org
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Cc: iommu@lists.linux-foundation.org
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---
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arch/mips/lantiq/xway/vmmc.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/arch/mips/lantiq/xway/vmmc.c
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+++ b/arch/mips/lantiq/xway/vmmc.c
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@@ -31,8 +31,8 @@ static int vmmc_probe(struct platform_de
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dma_addr_t dma;
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cp1_base =
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- (void *) CPHYSADDR(dma_alloc_coherent(NULL, CP1_SIZE,
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- &dma, GFP_ATOMIC));
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+ (void *) CPHYSADDR(dma_alloc_coherent(&pdev->dev, CP1_SIZE,
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+ &dma, GFP_KERNEL));
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gpio_count = of_gpio_count(pdev->dev.of_node);
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while (gpio_count > 0) {
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@ -0,0 +1,25 @@
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From d2fee0bb982195540e4fbe009996fcdbc26d163c Mon Sep 17 00:00:00 2001
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From: Mathias Kresin <dev@kresin.me>
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Date: Thu, 5 Mar 2020 08:17:27 +0100
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Subject: [PATCH] pinctrl: falcon: fix syntax error
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Add the missing semicolon after of_node_put to get the file compiled.
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Fixes: f17d2f54d36d ("pinctrl: falcon: Add of_node_put() before return")
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Cc: stable@vger.kernel.org # v5.4+
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Signed-off-by: Mathias Kresin <dev@kresin.me>
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---
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drivers/pinctrl/pinctrl-falcon.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/drivers/pinctrl/pinctrl-falcon.c
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+++ b/drivers/pinctrl/pinctrl-falcon.c
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@@ -451,7 +451,7 @@ static int pinctrl_falcon_probe(struct p
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falcon_info.clk[*bank] = clk_get(&ppdev->dev, NULL);
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if (IS_ERR(falcon_info.clk[*bank])) {
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dev_err(&ppdev->dev, "failed to get clock\n");
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- of_node_put(np)
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+ of_node_put(np);
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return PTR_ERR(falcon_info.clk[*bank]);
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}
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falcon_info.membase[*bank] = devm_ioremap_resource(&pdev->dev,
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@ -1,45 +0,0 @@
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From ae0c287060749dc72c866484d12bd3cade8c517d Mon Sep 17 00:00:00 2001
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From: Mathias Kresin <dev@kresin.me>
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Date: Fri, 19 Jan 2018 20:19:06 +0100
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Subject: [PATCH] MIPS: lantiq: autoselect matching vr9 rev gphy firmware
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Add a custom xrx200 ethernet phy compatible to load the firmware matching
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the vr9 revision without specifing an expected revision.
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We have quite a few boards in the tree were later produced ones are using
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a more recent vr9. It is impossible to distinguish which revision of the
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vr9 is used without opening the case and removing a heatsink for some of
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them.
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Signed-off-by: Mathias Kresin <dev@kresin.me>
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---
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drivers/soc/lantiq/gphy.c | 11 +++++++++++
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1 file changed, 11 insertions(+)
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--- a/drivers/soc/lantiq/gphy.c
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+++ b/drivers/soc/lantiq/gphy.c
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@@ -55,6 +55,7 @@ static const struct xway_gphy_match_data
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};
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static const struct of_device_id xway_gphy_match[] = {
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+ { .compatible = "lantiq,xrx200-gphy", .data = NULL },
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{ .compatible = "lantiq,xrx200a1x-gphy", .data = &xrx200a1x_gphy_data },
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{ .compatible = "lantiq,xrx200a2x-gphy", .data = &xrx200a2x_gphy_data },
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{ .compatible = "lantiq,xrx300-gphy", .data = &xrx300_gphy_data },
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@@ -111,6 +112,16 @@ static int xway_gphy_of_probe(struct pla
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gphy_fw_name_cfg = of_device_get_match_data(dev);
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+ if (of_device_is_compatible(pdev->dev.of_node, "lantiq,xrx200-gphy"))
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+ switch (ltq_soc_type()) {
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+ case SOC_TYPE_VR9:
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+ gphy_fw_name_cfg = &xrx200a1x_gphy_data;
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+ break;
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+ case SOC_TYPE_VR9_2:
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+ gphy_fw_name_cfg = &xrx200a2x_gphy_data;
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+ break;
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+ }
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+
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priv->gphy_clk_gate = devm_clk_get(dev, NULL);
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if (IS_ERR(priv->gphy_clk_gate)) {
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dev_err(dev, "Failed to lookup gate clock\n");
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@ -0,0 +1,55 @@
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From d0ee51bbb7ce9880749a3d4794ec1fbbcda0f381 Mon Sep 17 00:00:00 2001
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From: Mathias Kresin <dev@kresin.me>
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Date: Sun, 7 Jul 2019 21:45:51 +0200
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Subject: [PATCH] MIPS: lantiq revert DSA switch driver PMU/clock changes
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Switch back to the former used names, to make the legacy switch driver
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happy.
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Signed-off-by: Mathias Kresin <dev@kresin.me>
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---
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arch/mips/lantiq/xway/sysctrl.c | 14 +++++++-------
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1 file changed, 7 insertions(+), 7 deletions(-)
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--- a/arch/mips/lantiq/xway/sysctrl.c
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+++ b/arch/mips/lantiq/xway/sysctrl.c
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@@ -503,7 +503,7 @@ void __init ltq_soc_init(void)
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clkdev_add_pmu("1a800000.pcie", "msi", 1, 1, PMU1_PCIE2_MSI);
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clkdev_add_pmu("1f106a00.pcie", "pdi", 1, 1, PMU1_PCIE2_PDI);
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clkdev_add_pmu("1a800000.pcie", "ctl", 1, 1, PMU1_PCIE2_CTL);
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- clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH | PMU_PPE_DP);
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+ clkdev_add_pmu("1e108000.eth", NULL, 0, 0, PMU_SWITCH | PMU_PPE_DP);
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clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
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clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
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} else if (of_machine_is_compatible("lantiq,ar10")) {
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@@ -511,11 +511,11 @@ void __init ltq_soc_init(void)
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ltq_ar10_fpi_hz(), ltq_ar10_pp32_hz());
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clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
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clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);
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- clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH |
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+ clkdev_add_pmu("1e108000.eth", NULL, 0, 0, PMU_SWITCH |
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PMU_PPE_DP | PMU_PPE_TC);
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clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
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- clkdev_add_pmu("1e108000.gswip", "gphy0", 0, 0, PMU_GPHY);
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- clkdev_add_pmu("1e108000.gswip", "gphy1", 0, 0, PMU_GPHY);
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+ clkdev_add_pmu("1f203020.gphy", NULL, 1, 0, PMU_GPHY);
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+ clkdev_add_pmu("1f203068.gphy", NULL, 1, 0, PMU_GPHY);
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clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
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clkdev_add_pmu("1e116000.mei", "afe", 1, 2, PMU_ANALOG_DSL_AFE);
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clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
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@@ -534,12 +534,12 @@ void __init ltq_soc_init(void)
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clkdev_add_pmu(NULL, "ahb", 1, 0, PMU_AHBM | PMU_AHBS);
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clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
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- clkdev_add_pmu("1e10b308.eth", NULL, 0, 0,
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+ clkdev_add_pmu("1e108000.eth", NULL, 0, 0,
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PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
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PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
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PMU_PPE_QSB | PMU_PPE_TOP);
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- clkdev_add_pmu("1e108000.gswip", "gphy0", 0, 0, PMU_GPHY);
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- clkdev_add_pmu("1e108000.gswip", "gphy1", 0, 0, PMU_GPHY);
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+ clkdev_add_pmu("1f203020.gphy", NULL, 0, 0, PMU_GPHY);
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+ clkdev_add_pmu("1f203068.gphy", NULL, 0, 0, PMU_GPHY);
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clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
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clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
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clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
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@ -0,0 +1,352 @@
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From c8eedcadc38a5e6008d3990fbe0a5285b30335fc Mon Sep 17 00:00:00 2001
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From: Mathias Kresin <dev@kresin.me>
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Date: Sun, 7 Jul 2019 21:48:56 +0200
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Subject: [PATCH] MIPS: lantiq: Add GPHY Firmware loader
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Upstream, the GPHY Firmware loader has been merged into the DSA switch
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driver. But we don't use the driver yet, so bring it back.
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Signed-off-by: Mathias Kresin <dev@kresin.me>
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---
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.../bindings/mips/lantiq/rcu-gphy.txt | 36 +++
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.../devicetree/bindings/mips/lantiq/rcu.txt | 18 ++
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arch/mips/configs/xway_defconfig | 1 +
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arch/mips/lantiq/Kconfig | 4 +
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drivers/soc/lantiq/Makefile | 1 +
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drivers/soc/lantiq/gphy.c | 224 ++++++++++++++++++
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6 files changed, 284 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
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create mode 100644 drivers/soc/lantiq/gphy.c
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
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@@ -0,0 +1,37 @@
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+Lantiq XWAY SoC GPHY binding
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+============================
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+
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+This binding describes a software-defined ethernet PHY, provided by the RCU
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+module on newer Lantiq XWAY SoCs (xRX200 and newer).
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+
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+-------------------------------------------------------------------------------
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+Required properties:
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+- compatible : Should be one of
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+ "lantiq,xrx200-gphy"
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+ "lantiq,xrx200a1x-gphy"
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+ "lantiq,xrx200a2x-gphy"
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+ "lantiq,xrx300-gphy"
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+ "lantiq,xrx330-gphy"
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+- reg : Addrress of the GPHY FW load address register
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+- resets : Must reference the RCU GPHY reset bit
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+- reset-names : One entry, value must be "gphy" or optional "gphy2"
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+- clocks : A reference to the (PMU) GPHY clock gate
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+
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+Optional properties:
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+- lantiq,gphy-mode : GPHY_MODE_GE (default) or GPHY_MODE_FE as defined in
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+ <dt-bindings/mips/lantiq_xway_gphy.h>
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+
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+
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+-------------------------------------------------------------------------------
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+Example for the GPHys on the xRX200 SoCs:
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+
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+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
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+ gphy0: gphy@20 {
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+ compatible = "lantiq,xrx200a2x-gphy";
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+ reg = <0x20 0x4>;
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+
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+ resets = <&reset0 31 30>, <&reset1 7 7>;
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+ reset-names = "gphy", "gphy2";
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+ clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
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+ lantiq,gphy-mode = <GPHY_MODE_GE>;
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+ };
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--- a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
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+++ b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
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@@ -26,6 +26,24 @@ Example of the RCU bindings on a xRX200
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ranges = <0x0 0x203000 0x100>;
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big-endian;
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+ gphy0: gphy@20 {
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+ compatible = "lantiq,xrx200a2x-gphy";
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+ reg = <0x20 0x4>;
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+
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+ resets = <&reset0 31 30>, <&reset1 7 7>;
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+ reset-names = "gphy", "gphy2";
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+ lantiq,gphy-mode = <GPHY_MODE_GE>;
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+ };
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+
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+ gphy1: gphy@68 {
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+ compatible = "lantiq,xrx200a2x-gphy";
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+ reg = <0x68 0x4>;
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+
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+ resets = <&reset0 29 28>, <&reset1 6 6>;
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+ reset-names = "gphy", "gphy2";
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+ lantiq,gphy-mode = <GPHY_MODE_GE>;
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+ };
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+
|
||||
reset0: reset-controller@10 {
|
||||
compatible = "lantiq,xrx200-reset";
|
||||
reg = <0x10 4>, <0x14 4>;
|
||||
--- a/arch/mips/configs/xway_defconfig
|
||||
+++ b/arch/mips/configs/xway_defconfig
|
||||
@@ -13,6 +13,7 @@ CONFIG_EMBEDDED=y
|
||||
# CONFIG_COMPAT_BRK is not set
|
||||
CONFIG_LANTIQ=y
|
||||
CONFIG_PCI_LANTIQ=y
|
||||
+CONFIG_XRX200_PHY_FW=y
|
||||
CONFIG_CPU_MIPS32_R2=y
|
||||
CONFIG_MIPS_VPE_LOADER=y
|
||||
CONFIG_NR_CPUS=2
|
||||
--- a/arch/mips/lantiq/Kconfig
|
||||
+++ b/arch/mips/lantiq/Kconfig
|
||||
@@ -62,4 +62,8 @@ config PCIE_LANTIQ_MSI
|
||||
depends on PCIE_LANTIQ && PCI_MSI
|
||||
default y
|
||||
|
||||
+config XRX200_PHY_FW
|
||||
+ bool "XRX200 PHY firmware loader"
|
||||
+ depends on SOC_XWAY
|
||||
+
|
||||
endif
|
||||
--- a/drivers/soc/lantiq/Makefile
|
||||
+++ b/drivers/soc/lantiq/Makefile
|
||||
@@ -1,2 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
obj-y += fpi-bus.o
|
||||
+obj-$(CONFIG_XRX200_PHY_FW) += gphy.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/soc/lantiq/gphy.c
|
||||
@@ -0,0 +1,235 @@
|
||||
+/*
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ *
|
||||
+ * Copyright (C) 2012 John Crispin <blogic@phrozen.org>
|
||||
+ * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
|
||||
+ * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
|
||||
+ */
|
||||
+
|
||||
+#include <linux/clk.h>
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/dma-mapping.h>
|
||||
+#include <linux/firmware.h>
|
||||
+#include <linux/mfd/syscon.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/reboot.h>
|
||||
+#include <linux/regmap.h>
|
||||
+#include <linux/reset.h>
|
||||
+#include <linux/of_device.h>
|
||||
+#include <linux/of_platform.h>
|
||||
+#include <linux/property.h>
|
||||
+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
|
||||
+
|
||||
+#include <lantiq_soc.h>
|
||||
+
|
||||
+#define XRX200_GPHY_FW_ALIGN (16 * 1024)
|
||||
+
|
||||
+struct xway_gphy_priv {
|
||||
+ struct clk *gphy_clk_gate;
|
||||
+ struct reset_control *gphy_reset;
|
||||
+ struct reset_control *gphy_reset2;
|
||||
+ void __iomem *membase;
|
||||
+ char *fw_name;
|
||||
+};
|
||||
+
|
||||
+struct xway_gphy_match_data {
|
||||
+ char *fe_firmware_name;
|
||||
+ char *ge_firmware_name;
|
||||
+};
|
||||
+
|
||||
+static const struct xway_gphy_match_data xrx200a1x_gphy_data = {
|
||||
+ .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin",
|
||||
+ .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin",
|
||||
+};
|
||||
+
|
||||
+static const struct xway_gphy_match_data xrx200a2x_gphy_data = {
|
||||
+ .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin",
|
||||
+ .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin",
|
||||
+};
|
||||
+
|
||||
+static const struct xway_gphy_match_data xrx300_gphy_data = {
|
||||
+ .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin",
|
||||
+ .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin",
|
||||
+};
|
||||
+
|
||||
+static const struct of_device_id xway_gphy_match[] = {
|
||||
+ { .compatible = "lantiq,xrx200-gphy", .data = NULL },
|
||||
+ { .compatible = "lantiq,xrx200a1x-gphy", .data = &xrx200a1x_gphy_data },
|
||||
+ { .compatible = "lantiq,xrx200a2x-gphy", .data = &xrx200a2x_gphy_data },
|
||||
+ { .compatible = "lantiq,xrx300-gphy", .data = &xrx300_gphy_data },
|
||||
+ { .compatible = "lantiq,xrx330-gphy", .data = &xrx300_gphy_data },
|
||||
+ {},
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, xway_gphy_match);
|
||||
+
|
||||
+static int xway_gphy_load(struct device *dev, struct xway_gphy_priv *priv,
|
||||
+ dma_addr_t *dev_addr)
|
||||
+{
|
||||
+ const struct firmware *fw;
|
||||
+ void *fw_addr;
|
||||
+ dma_addr_t dma_addr;
|
||||
+ size_t size;
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = request_firmware(&fw, priv->fw_name, dev);
|
||||
+ if (ret) {
|
||||
+ dev_err(dev, "failed to load firmware: %s, error: %i\n",
|
||||
+ priv->fw_name, ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ /*
|
||||
+ * GPHY cores need the firmware code in a persistent and contiguous
|
||||
+ * memory area with a 16 kB boundary aligned start address.
|
||||
+ */
|
||||
+ size = fw->size + XRX200_GPHY_FW_ALIGN;
|
||||
+
|
||||
+ fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL);
|
||||
+ if (fw_addr) {
|
||||
+ fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN);
|
||||
+ *dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN);
|
||||
+ memcpy(fw_addr, fw->data, fw->size);
|
||||
+ } else {
|
||||
+ dev_err(dev, "failed to alloc firmware memory\n");
|
||||
+ ret = -ENOMEM;
|
||||
+ }
|
||||
+
|
||||
+ release_firmware(fw);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int xway_gphy_of_probe(struct platform_device *pdev,
|
||||
+ struct xway_gphy_priv *priv)
|
||||
+{
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ const struct xway_gphy_match_data *gphy_fw_name_cfg;
|
||||
+ u32 gphy_mode;
|
||||
+ int ret;
|
||||
+ struct resource *res_gphy;
|
||||
+
|
||||
+ gphy_fw_name_cfg = of_device_get_match_data(dev);
|
||||
+
|
||||
+ if (of_device_is_compatible(pdev->dev.of_node, "lantiq,xrx200-gphy"))
|
||||
+ switch (ltq_soc_type()) {
|
||||
+ case SOC_TYPE_VR9:
|
||||
+ gphy_fw_name_cfg = &xrx200a1x_gphy_data;
|
||||
+ break;
|
||||
+ case SOC_TYPE_VR9_2:
|
||||
+ gphy_fw_name_cfg = &xrx200a2x_gphy_data;
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ priv->gphy_clk_gate = devm_clk_get(dev, NULL);
|
||||
+ if (IS_ERR(priv->gphy_clk_gate)) {
|
||||
+ dev_err(dev, "Failed to lookup gate clock\n");
|
||||
+ return PTR_ERR(priv->gphy_clk_gate);
|
||||
+ }
|
||||
+
|
||||
+ res_gphy = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ priv->membase = devm_ioremap_resource(dev, res_gphy);
|
||||
+ if (IS_ERR(priv->membase))
|
||||
+ return PTR_ERR(priv->membase);
|
||||
+
|
||||
+ priv->gphy_reset = devm_reset_control_get(dev, "gphy");
|
||||
+ if (IS_ERR(priv->gphy_reset)) {
|
||||
+ if (PTR_ERR(priv->gphy_reset) != -EPROBE_DEFER)
|
||||
+ dev_err(dev, "Failed to lookup gphy reset\n");
|
||||
+ return PTR_ERR(priv->gphy_reset);
|
||||
+ }
|
||||
+
|
||||
+ priv->gphy_reset2 = devm_reset_control_get_optional(dev, "gphy2");
|
||||
+ if (IS_ERR(priv->gphy_reset2))
|
||||
+ return PTR_ERR(priv->gphy_reset2);
|
||||
+
|
||||
+ ret = device_property_read_u32(dev, "lantiq,gphy-mode", &gphy_mode);
|
||||
+ /* Default to GE mode */
|
||||
+ if (ret)
|
||||
+ gphy_mode = GPHY_MODE_GE;
|
||||
+
|
||||
+ switch (gphy_mode) {
|
||||
+ case GPHY_MODE_FE:
|
||||
+ priv->fw_name = gphy_fw_name_cfg->fe_firmware_name;
|
||||
+ break;
|
||||
+ case GPHY_MODE_GE:
|
||||
+ priv->fw_name = gphy_fw_name_cfg->ge_firmware_name;
|
||||
+ break;
|
||||
+ default:
|
||||
+ dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int xway_gphy_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ struct xway_gphy_priv *priv;
|
||||
+ dma_addr_t fw_addr = 0;
|
||||
+ int ret;
|
||||
+
|
||||
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
+ if (!priv)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ ret = xway_gphy_of_probe(pdev, priv);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = clk_prepare_enable(priv->gphy_clk_gate);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = xway_gphy_load(dev, priv, &fw_addr);
|
||||
+ if (ret) {
|
||||
+ clk_disable_unprepare(priv->gphy_clk_gate);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ reset_control_assert(priv->gphy_reset);
|
||||
+ reset_control_assert(priv->gphy_reset2);
|
||||
+
|
||||
+ iowrite32be(fw_addr, priv->membase);
|
||||
+
|
||||
+ reset_control_deassert(priv->gphy_reset);
|
||||
+ reset_control_deassert(priv->gphy_reset2);
|
||||
+
|
||||
+ platform_set_drvdata(pdev, priv);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int xway_gphy_remove(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct xway_gphy_priv *priv = platform_get_drvdata(pdev);
|
||||
+
|
||||
+ iowrite32be(0, priv->membase);
|
||||
+
|
||||
+ clk_disable_unprepare(priv->gphy_clk_gate);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct platform_driver xway_gphy_driver = {
|
||||
+ .probe = xway_gphy_probe,
|
||||
+ .remove = xway_gphy_remove,
|
||||
+ .driver = {
|
||||
+ .name = "xway-rcu-gphy",
|
||||
+ .of_match_table = xway_gphy_match,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+module_platform_driver(xway_gphy_driver);
|
||||
+
|
||||
+MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin");
|
||||
+MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin");
|
||||
+MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin");
|
||||
+MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin");
|
||||
+MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin");
|
||||
+MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin");
|
||||
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
|
||||
+MODULE_DESCRIPTION("Lantiq XWAY GPHY Firmware Loader");
|
||||
+MODULE_LICENSE("GPL");
|
Loading…
Reference in New Issue