Hauke Mehrtens
15 years ago
parent
4d1bfc3760
commit
6a78996e76
@ -0,0 +1,154 @@
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CONFIG_32BIT=y
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# CONFIG_64BIT is not set
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CONFIG_ADM6996_SUPPORT=y
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# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
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CONFIG_AMAZON=y
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CONFIG_AMAZON_ASC_UART=y
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CONFIG_AMAZON_MTD=y
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CONFIG_AMAZON_NET_SW=y
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CONFIG_AMAZON_PCI=y
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CONFIG_AMAZON_WDT=y
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# CONFIG_AR7 is not set
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# CONFIG_ARCH_HAS_ILOG2_U32 is not set
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# CONFIG_ARCH_HAS_ILOG2_U64 is not set
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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CONFIG_ARCH_POPULATES_NODE_MAP=y
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# CONFIG_ARCH_SUPPORTS_MSI is not set
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CONFIG_ARCH_SUPPORTS_OPROFILE=y
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CONFIG_ARCH_SUSPEND_POSSIBLE=y
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# CONFIG_BCM47XX is not set
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# CONFIG_BCM63XX is not set
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CONFIG_BITREVERSE=y
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# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
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# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
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CONFIG_CEVT_R4K=y
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CONFIG_CEVT_R4K_LIB=y
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CONFIG_CFG80211_DEFAULT_PS_VALUE=0
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CONFIG_CMDLINE="console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/bin/sh"
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CONFIG_CPU_BIG_ENDIAN=y
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# CONFIG_CPU_CAVIUM_OCTEON is not set
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CONFIG_CPU_HAS_PREFETCH=y
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CONFIG_CPU_HAS_SYNC=y
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# CONFIG_CPU_LITTLE_ENDIAN is not set
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# CONFIG_CPU_LOONGSON2E is not set
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CONFIG_CPU_MIPS32=y
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# CONFIG_CPU_MIPS32_R1 is not set
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CONFIG_CPU_MIPS32_R2=y
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# CONFIG_CPU_MIPS64_R1 is not set
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# CONFIG_CPU_MIPS64_R2 is not set
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CONFIG_CPU_MIPSR2=y
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# CONFIG_CPU_NEVADA is not set
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# CONFIG_CPU_R10000 is not set
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# CONFIG_CPU_R3000 is not set
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# CONFIG_CPU_R4300 is not set
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# CONFIG_CPU_R4X00 is not set
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# CONFIG_CPU_R5000 is not set
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# CONFIG_CPU_R5432 is not set
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# CONFIG_CPU_R5500 is not set
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# CONFIG_CPU_R6000 is not set
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# CONFIG_CPU_R8000 is not set
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# CONFIG_CPU_RM7000 is not set
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# CONFIG_CPU_RM9000 is not set
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# CONFIG_CPU_SB1 is not set
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CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
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CONFIG_CPU_SUPPORTS_HIGHMEM=y
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# CONFIG_CPU_TX39XX is not set
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# CONFIG_CPU_TX49XX is not set
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# CONFIG_CPU_VR41XX is not set
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CONFIG_CSRC_R4K=y
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CONFIG_CSRC_R4K_LIB=y
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CONFIG_DECOMPRESS_LZMA=y
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CONFIG_DEVPORT=y
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# CONFIG_DM9000 is not set
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CONFIG_DMA_NEED_PCI_MAP_STATE=y
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CONFIG_DMA_NONCOHERENT=y
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CONFIG_EARLY_PRINTK=y
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# CONFIG_FSNOTIFY is not set
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
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CONFIG_GENERIC_CMOS_UPDATE=y
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CONFIG_GENERIC_FIND_LAST_BIT=y
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CONFIG_GENERIC_FIND_NEXT_BIT=y
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CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
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CONFIG_HARDWARE_WATCHPOINTS=y
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CONFIG_HAS_DMA=y
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CONFIG_HAS_IOMEM=y
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CONFIG_HAS_IOPORT=y
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CONFIG_HAVE_ARCH_KGDB=y
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CONFIG_HAVE_GENERIC_DMA_COHERENT=y
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CONFIG_HAVE_IDE=y
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CONFIG_HAVE_OPROFILE=y
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CONFIG_HAVE_STD_PC_SERIAL_PORT=y
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CONFIG_HW_HAS_PCI=y
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CONFIG_HW_RANDOM=y
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CONFIG_INITRAMFS_SOURCE=""
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CONFIG_IRQ_CPU=y
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CONFIG_KALLSYMS=y
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# CONFIG_MACH_ALCHEMY is not set
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# CONFIG_MACH_DECSTATION is not set
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# CONFIG_MACH_JAZZ is not set
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# CONFIG_MACH_LOONGSON is not set
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# CONFIG_MACH_TX39XX is not set
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# CONFIG_MACH_TX49XX is not set
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# CONFIG_MACH_VR41XX is not set
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# CONFIG_MIKROTIK_RB532 is not set
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CONFIG_MIPS=y
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# CONFIG_MIPS_COBALT is not set
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CONFIG_MIPS_L1_CACHE_SHIFT=5
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# CONFIG_MIPS_MACHINE is not set
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# CONFIG_MIPS_MALTA is not set
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CONFIG_MIPS_MT_DISABLED=y
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# CONFIG_MIPS_MT_SMP is not set
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# CONFIG_MIPS_MT_SMTC is not set
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# CONFIG_MIPS_SIM is not set
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CONFIG_MTD_AMAZON_BUS_WIDTH_16=y
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# CONFIG_MTD_AMAZON_BUS_WIDTH_32 is not set
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# CONFIG_MTD_AMAZON_BUS_WIDTH_8 is not set
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# CONFIG_MTD_AMAZON_FLASH_SIZE_16 is not set
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# CONFIG_MTD_AMAZON_FLASH_SIZE_2 is not set
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CONFIG_MTD_AMAZON_FLASH_SIZE_4=y
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# CONFIG_MTD_AMAZON_FLASH_SIZE_8 is not set
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CONFIG_MTD_CFI_ADV_OPTIONS=y
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# CONFIG_MTD_CFI_GEOMETRY is not set
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# CONFIG_MTD_CFI_INTELEXT is not set
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CONFIG_MTD_PHYSMAP=y
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CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-3
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CONFIG_MTD_REDBOOT_PARTS=y
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# CONFIG_NET_PCI is not set
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# CONFIG_NO_IOPORT is not set
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# CONFIG_NXP_STB220 is not set
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# CONFIG_NXP_STB225 is not set
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CONFIG_PAGEFLAGS_EXTENDED=y
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CONFIG_PCI_DOMAINS=y
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# CONFIG_PMC_MSP is not set
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# CONFIG_PMC_YOSEMITE is not set
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# CONFIG_PNX8550_JBS is not set
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# CONFIG_PNX8550_STB810 is not set
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# CONFIG_PROBE_INITRD_HEADER is not set
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CONFIG_SCHED_OMIT_FRAME_POINTER=y
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# CONFIG_SCSI_DMA is not set
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# CONFIG_SERIAL_8250 is not set
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# CONFIG_SGI_IP22 is not set
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# CONFIG_SGI_IP27 is not set
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# CONFIG_SGI_IP28 is not set
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# CONFIG_SGI_IP32 is not set
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# CONFIG_SIBYTE_BIGSUR is not set
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# CONFIG_SIBYTE_CARMEL is not set
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# CONFIG_SIBYTE_CRHINE is not set
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# CONFIG_SIBYTE_CRHONE is not set
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# CONFIG_SIBYTE_LITTLESUR is not set
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# CONFIG_SIBYTE_RHONE is not set
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# CONFIG_SIBYTE_SENTOSA is not set
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# CONFIG_SIBYTE_SWARM is not set
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CONFIG_SWAP_IO_SPACE=y
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CONFIG_SYS_HAS_CPU_MIPS32_R1=y
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CONFIG_SYS_HAS_CPU_MIPS32_R2=y
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CONFIG_SYS_HAS_EARLY_PRINTK=y
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CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
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CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
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CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
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CONFIG_TRAD_SIGNALS=y
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# CONFIG_TREE_PREEMPT_RCU is not set
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CONFIG_TREE_RCU=y
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CONFIG_USB_SUPPORT=y
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CONFIG_ZONE_DMA_FLAG=0
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@ -0,0 +1,32 @@
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--- a/arch/mips/kernel/traps.c
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+++ b/arch/mips/kernel/traps.c
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@@ -1537,7 +1537,16 @@ void __cpuinit per_cpu_trap_init(void)
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*/
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if (cpu_has_mips_r2) {
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cp0_compare_irq = (read_c0_intctl() >> 29) & 7;
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+ if (!cp0_compare_irq)
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+ cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
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+
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cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7;
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+ if (!cp0_perfcount_irq)
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+ cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ;
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+
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+ if (arch_fixup_c0_irqs)
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+ arch_fixup_c0_irqs();
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+
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if (cp0_perfcount_irq == cp0_compare_irq)
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cp0_perfcount_irq = -1;
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} else {
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--- a/arch/mips/include/asm/irq.h
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+++ b/arch/mips/include/asm/irq.h
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@@ -158,8 +158,10 @@ extern void free_irqno(unsigned int irq)
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* IE7. Since R2 their number has to be read from the c0_intctl register.
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*/
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#define CP0_LEGACY_COMPARE_IRQ 7
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+#define CP0_LEGACY_PERFCNT_IRQ 7
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extern int cp0_compare_irq;
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extern int cp0_perfcount_irq;
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+extern void __weak arch_fixup_c0_irqs(void);
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#endif /* _ASM_IRQ_H */
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@ -0,0 +1,33 @@
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--- a/arch/mips/kernel/cevt-r4k.c
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+++ b/arch/mips/kernel/cevt-r4k.c
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@@ -22,6 +22,22 @@
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#ifndef CONFIG_MIPS_MT_SMTC
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+/*
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+ * Compare interrupt can be routed and latched outside the core,
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+ * so a single execution hazard barrier may not be enough to give
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+ * it time to clear as seen in the Cause register. 4 time the
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+ * pipeline depth seems reasonably conservative, and empirically
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+ * works better in configurations with high CPU/bus clock ratios.
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+ */
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+
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+#define compare_change_hazard() \
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+ do { \
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+ irq_disable_hazard(); \
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+ irq_disable_hazard(); \
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+ irq_disable_hazard(); \
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+ irq_disable_hazard(); \
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+ } while (0)
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+
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static int mips_next_event(unsigned long delta,
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struct clock_event_device *evt)
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{
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@@ -31,6 +47,7 @@ static int mips_next_event(unsigned long
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cnt = read_c0_count();
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cnt += delta;
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write_c0_compare(cnt);
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+ compare_change_hazard();
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res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
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return res;
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}
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@ -0,0 +1,10 @@
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--- a/drivers/watchdog/Makefile
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+++ b/drivers/watchdog/Makefile
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@@ -113,6 +113,7 @@ obj-$(CONFIG_WDT_RM9K_GPI) += rm9k_wdt.o
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obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
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obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
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obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
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+obj-$(CONFIG_AMAZON_WDT) += amazon_wdt.o
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# PARISC Architecture
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@ -0,0 +1,49 @@
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--- a/arch/mips/Kconfig
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+++ b/arch/mips/Kconfig
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@@ -96,6 +96,22 @@ config BCM63XX
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help
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Support for BCM63XX based boards
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+config AMAZON
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+ bool "Amazon support (EXPERIMENTAL)"
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+ depends on EXPERIMENTAL
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+ select DMA_NONCOHERENT
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+ select IRQ_CPU
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+ select CEVT_R4K
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+ select CSRC_R4K
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+ select SYS_HAS_CPU_MIPS32_R1
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+ select SYS_HAS_CPU_MIPS32_R2
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+ select HAVE_STD_PC_SERIAL_PORT
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+ select SYS_SUPPORTS_BIG_ENDIAN
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+ select SYS_SUPPORTS_32BIT_KERNEL
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+ select SYS_HAS_EARLY_PRINTK
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+ select HW_HAS_PCI
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+ select SWAP_IO_SPACE
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+
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config MIPS_COBALT
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bool "Cobalt Server"
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select CEVT_R4K
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@@ -673,6 +689,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
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endchoice
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+source "arch/mips/amazon/Kconfig"
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source "arch/mips/alchemy/Kconfig"
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source "arch/mips/basler/excite/Kconfig"
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source "arch/mips/bcm63xx/Kconfig"
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--- a/arch/mips/Makefile
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+++ b/arch/mips/Makefile
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@@ -296,6 +296,13 @@ cflags-$(CONFIG_SOC_AU1X00) += -I$(srctr
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#
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+# Infineon AMAZON
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+#
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+core-$(CONFIG_AMAZON) += arch/mips/amazon/
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+cflags-$(CONFIG_AMAZON) += -I$(srctree)/arch/mips/include/asm/mach-amazon
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+load-$(CONFIG_AMAZON) += 0xffffffff80002000
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+
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+#
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# Cobalt Server
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#
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core-$(CONFIG_MIPS_COBALT) += arch/mips/cobalt/
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@ -0,0 +1,7 @@
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--- a/drivers/mtd/maps/Makefile
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+++ b/drivers/mtd/maps/Makefile
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@@ -61,3 +61,4 @@ obj-$(CONFIG_MTD_BFIN_ASYNC) += bfin-asy
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obj-$(CONFIG_MTD_RBTX4939) += rbtx4939-flash.o
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obj-$(CONFIG_MTD_VMU) += vmu-flash.o
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obj-$(CONFIG_MTD_GPIO_ADDR) += gpio-addr-flash.o
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+obj-$(CONFIG_AMAZON_MTD) += amazon.o
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@ -0,0 +1,9 @@
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--- a/drivers/net/Makefile
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+++ b/drivers/net/Makefile
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@@ -286,3 +286,6 @@ obj-$(CONFIG_VIRTIO_NET) += virtio_net.o
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obj-$(CONFIG_SFC) += sfc/
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obj-$(CONFIG_WIMAX) += wimax/
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+
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+obj-$(CONFIG_AMAZON_NET_SW) += amazon_sw.o
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+obj-$(CONFIG_ADM6996_SUPPORT) += admmod.o
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@ -0,0 +1,10 @@
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--- a/drivers/serial/Makefile
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+++ b/drivers/serial/Makefile
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@@ -3,6 +3,7 @@
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#
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obj-$(CONFIG_SERIAL_CORE) += serial_core.o
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+obj-$(CONFIG_AMAZON_ASC_UART) += amazon_asc.o
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obj-$(CONFIG_SERIAL_21285) += 21285.o
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# These Sparc drivers have to appear before others such as 8250
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@ -0,0 +1,56 @@
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--- a/drivers/mtd/chips/cfi_cmdset_0002.c
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+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
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@@ -1079,6 +1079,9 @@ static int __xipram do_write_oneword(str
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int retry_cnt = 0;
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adr += chip->start;
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+#ifdef CONFIG_AMAZON
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+ adr ^= 2;
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+#endif
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spin_lock(chip->mutex);
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ret = get_chip(map, chip, adr, FL_WRITING);
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@@ -1361,7 +1364,11 @@ static int __xipram do_write_buffer(stru
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z = 0;
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while(z < words * map_bankwidth(map)) {
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datum = map_word_load(map, buf);
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+#ifdef CONFIG_AMAZON
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+ map_write(map, datum, (adr + z) ^ 0x2);
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+#else
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map_write(map, datum, adr + z);
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+#endif
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z += map_bankwidth(map);
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buf += map_bankwidth(map);
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@@ -1606,6 +1613,9 @@ static int __xipram do_erase_oneblock(st
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int ret = 0;
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adr += chip->start;
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+#ifdef CONFIG_AMAZON
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+ adr ^= 2;
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+#endif
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spin_lock(chip->mutex);
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ret = get_chip(map, chip, adr, FL_ERASING);
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@@ -1734,6 +1744,10 @@ static int do_atmel_lock(struct map_info
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struct cfi_private *cfi = map->fldrv_priv;
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int ret;
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+#ifdef CONFIG_AMAZON
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+ adr ^= 2;
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+#endif
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+
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spin_lock(chip->mutex);
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ret = get_chip(map, chip, adr + chip->start, FL_LOCKING);
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if (ret)
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@@ -1770,6 +1784,10 @@ static int do_atmel_unlock(struct map_in
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struct cfi_private *cfi = map->fldrv_priv;
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int ret;
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+#ifdef CONFIG_AMAZON
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+ adr ^= 2;
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+#endif
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+
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spin_lock(chip->mutex);
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ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING);
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if (ret)
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