From 64d088d8f9f2fbca75f3240ced5cf40b721dc3f2 Mon Sep 17 00:00:00 2001 From: Sebastian Schaper Date: Tue, 19 May 2020 12:40:17 +0200 Subject: [PATCH] ath79: increase spi clock for D-Link DIR-842 AHB is 258 MHz for this device (CPU_PLL / 3), but there is no difference between 64 MHz and 50 MHz for spi-max-frequency, thus increase to 50 MHz. Tested on revisions C1 and C3. Signed-off-by: Sebastian Schaper --- target/linux/ath79/dts/qca9563_dlink_dir-842-c.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/linux/ath79/dts/qca9563_dlink_dir-842-c.dtsi b/target/linux/ath79/dts/qca9563_dlink_dir-842-c.dtsi index 8071332451..6b2fb1c4a0 100644 --- a/target/linux/ath79/dts/qca9563_dlink_dir-842-c.dtsi +++ b/target/linux/ath79/dts/qca9563_dlink_dir-842-c.dtsi @@ -37,12 +37,13 @@ &spi { status = "okay"; + num-cs = <1>; flash@0 { compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <30000000>; + spi-max-frequency = <50000000>; partitions { compatible = "fixed-partitions";