ipq806x: refresh 4.19 patches
Reworked: - 0034 patchset update Added: - 080 Add support for pinctrl-msm framework Removed: - 0074-ipq806x-usb-Control-USB-master-reset.patch (we now have a dedicated driver for qcom usb) - 0047-mtd-nand-Create-a-BBT-flag-to-access-bad-block-marke (merged upstream) - 310-msm-adhoc-bus-support (it looks like it was never actually used in any dts) Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> [commit subject and description facelift, SoB fix] Signed-off-by: Petr Štetiar <ynezz@true.cz>master
Christian Lamparter
5 years ago
committed by
Petr Štetiar
parent
53801ae1c7
commit
63066d3006
@ -0,0 +1,81 @@
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From 1f924faa8b1e4789ecc06ed0dd58ca3487c89012 Mon Sep 17 00:00:00 2001
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From: Stephen Boyd <sboyd@codeaurora.org>
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Date: Tue, 14 Aug 2018 17:42:23 +0530
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Subject: [PATCH 04/12] dt-bindings: clock: Document qcom,hfpll
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Adds bindings document for qcom,hfpll instantiated within
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the Krait processor subsystem as separate register region.
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Reviewed-by: Rob Herring <robh@kernel.org>
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Signed-off-by: Sricharan R <sricharan@codeaurora.org>
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Tested-by: Craig Tatlor <ctatlor97@gmail.com>
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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.../devicetree/bindings/clock/qcom,hfpll.txt | 60 +++++++++++++++++++
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1 file changed, 60 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.txt
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
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@@ -0,0 +1,60 @@
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+High-Frequency PLL (HFPLL)
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+
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+PROPERTIES
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+
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+- compatible:
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+ Usage: required
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+ Value type: <string>:
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+ shall contain only one of the following. The generic
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+ compatible "qcom,hfpll" should be also included.
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+
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+ "qcom,hfpll-ipq8064", "qcom,hfpll"
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+ "qcom,hfpll-apq8064", "qcom,hfpll"
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+ "qcom,hfpll-msm8974", "qcom,hfpll"
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+ "qcom,hfpll-msm8960", "qcom,hfpll"
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+
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+- reg:
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+ Usage: required
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+ Value type: <prop-encoded-array>
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+ Definition: address and size of HPLL registers. An optional second
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+ element specifies the address and size of the alias
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+ register region.
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+
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+- clocks:
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+ Usage: required
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+ Value type: <prop-encoded-array>
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+ Definition: reference to the xo clock.
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+
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+- clock-names:
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+ Usage: required
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+ Value type: <stringlist>
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+ Definition: must be "xo".
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+
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+- clock-output-names:
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+ Usage: required
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+ Value type: <string>
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+ Definition: Name of the PLL. Typically hfpllX where X is a CPU number
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+ starting at 0. Otherwise hfpll_Y where Y is more specific
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+ such as "l2".
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+
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+Example:
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+
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+1) An HFPLL for the L2 cache.
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+
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+ clock-controller@f9016000 {
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+ compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
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+ reg = <0xf9016000 0x30>;
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+ clocks = <&xo_board>;
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+ clock-names = "xo";
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+ clock-output-names = "hfpll_l2";
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+ };
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+
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+2) An HFPLL for CPU0. This HFPLL has the alias register region.
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+
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+ clock-controller@f908a000 {
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+ compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
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+ reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
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+ clocks = <&xo_board>;
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+ clock-names = "xo";
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+ clock-output-names = "hfpll0";
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+ };
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@ -0,0 +1,236 @@
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From 72ad7207954dd622a662ba884dc6c30a820123f2 Mon Sep 17 00:00:00 2001
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From: Stephen Boyd <sboyd@codeaurora.org>
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Date: Tue, 14 Aug 2018 17:42:24 +0530
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Subject: [PATCH 05/12] clk: qcom: Add MSM8960/APQ8064's HFPLLs
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Describe the HFPLLs present on MSM8960 and APQ8064 devices.
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Acked-by: Rob Herring <robh@kernel.org> (bindings)
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Signed-off-by: Sricharan R <sricharan@codeaurora.org>
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Tested-by: Craig Tatlor <ctatlor97@gmail.com>
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/qcom/gcc-msm8960.c | 172 +++++++++++++++++++
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include/dt-bindings/clock/qcom,gcc-msm8960.h | 2 +
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2 files changed, 174 insertions(+)
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--- a/drivers/clk/qcom/gcc-msm8960.c
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+++ b/drivers/clk/qcom/gcc-msm8960.c
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@@ -30,6 +30,7 @@
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#include "clk-pll.h"
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#include "clk-rcg.h"
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#include "clk-branch.h"
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+#include "clk-hfpll.h"
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#include "reset.h"
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static struct clk_pll pll3 = {
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@@ -86,6 +87,164 @@ static struct clk_regmap pll8_vote = {
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},
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};
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+static struct hfpll_data hfpll0_data = {
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+ .mode_reg = 0x3200,
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+ .l_reg = 0x3208,
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+ .m_reg = 0x320c,
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+ .n_reg = 0x3210,
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+ .config_reg = 0x3204,
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+ .status_reg = 0x321c,
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+ .config_val = 0x7845c665,
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+ .droop_reg = 0x3214,
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+ .droop_val = 0x0108c000,
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+ .min_rate = 600000000UL,
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+ .max_rate = 1800000000UL,
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+};
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+
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+static struct clk_hfpll hfpll0 = {
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+ .d = &hfpll0_data,
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+ .clkr.hw.init = &(struct clk_init_data){
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+ .parent_names = (const char *[]){ "pxo" },
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+ .num_parents = 1,
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+ .name = "hfpll0",
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+ .ops = &clk_ops_hfpll,
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+ .flags = CLK_IGNORE_UNUSED,
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+ },
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+ .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
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+};
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+
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+static struct hfpll_data hfpll1_8064_data = {
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+ .mode_reg = 0x3240,
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+ .l_reg = 0x3248,
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+ .m_reg = 0x324c,
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+ .n_reg = 0x3250,
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+ .config_reg = 0x3244,
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+ .status_reg = 0x325c,
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+ .config_val = 0x7845c665,
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+ .droop_reg = 0x3254,
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+ .droop_val = 0x0108c000,
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+ .min_rate = 600000000UL,
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+ .max_rate = 1800000000UL,
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+};
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+
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+static struct hfpll_data hfpll1_data = {
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+ .mode_reg = 0x3300,
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+ .l_reg = 0x3308,
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+ .m_reg = 0x330c,
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+ .n_reg = 0x3310,
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+ .config_reg = 0x3304,
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+ .status_reg = 0x331c,
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+ .config_val = 0x7845c665,
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+ .droop_reg = 0x3314,
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+ .droop_val = 0x0108c000,
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+ .min_rate = 600000000UL,
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+ .max_rate = 1800000000UL,
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+};
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+
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+static struct clk_hfpll hfpll1 = {
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+ .d = &hfpll1_data,
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+ .clkr.hw.init = &(struct clk_init_data){
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+ .parent_names = (const char *[]){ "pxo" },
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+ .num_parents = 1,
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+ .name = "hfpll1",
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+ .ops = &clk_ops_hfpll,
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+ .flags = CLK_IGNORE_UNUSED,
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+ },
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+ .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
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+};
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+
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+static struct hfpll_data hfpll2_data = {
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+ .mode_reg = 0x3280,
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+ .l_reg = 0x3288,
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+ .m_reg = 0x328c,
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+ .n_reg = 0x3290,
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+ .config_reg = 0x3284,
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+ .status_reg = 0x329c,
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+ .config_val = 0x7845c665,
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+ .droop_reg = 0x3294,
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+ .droop_val = 0x0108c000,
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+ .min_rate = 600000000UL,
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+ .max_rate = 1800000000UL,
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+};
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+
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+static struct clk_hfpll hfpll2 = {
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+ .d = &hfpll2_data,
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+ .clkr.hw.init = &(struct clk_init_data){
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+ .parent_names = (const char *[]){ "pxo" },
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+ .num_parents = 1,
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+ .name = "hfpll2",
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+ .ops = &clk_ops_hfpll,
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+ .flags = CLK_IGNORE_UNUSED,
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+ },
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+ .lock = __SPIN_LOCK_UNLOCKED(hfpll2.lock),
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+};
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+
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+static struct hfpll_data hfpll3_data = {
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+ .mode_reg = 0x32c0,
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+ .l_reg = 0x32c8,
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+ .m_reg = 0x32cc,
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+ .n_reg = 0x32d0,
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+ .config_reg = 0x32c4,
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+ .status_reg = 0x32dc,
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+ .config_val = 0x7845c665,
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+ .droop_reg = 0x32d4,
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+ .droop_val = 0x0108c000,
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+ .min_rate = 600000000UL,
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+ .max_rate = 1800000000UL,
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+};
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+
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+static struct clk_hfpll hfpll3 = {
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+ .d = &hfpll3_data,
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+ .clkr.hw.init = &(struct clk_init_data){
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+ .parent_names = (const char *[]){ "pxo" },
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+ .num_parents = 1,
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+ .name = "hfpll3",
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+ .ops = &clk_ops_hfpll,
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+ .flags = CLK_IGNORE_UNUSED,
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+ },
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+ .lock = __SPIN_LOCK_UNLOCKED(hfpll3.lock),
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+};
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+
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+static struct hfpll_data hfpll_l2_8064_data = {
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+ .mode_reg = 0x3300,
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+ .l_reg = 0x3308,
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+ .m_reg = 0x330c,
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+ .n_reg = 0x3310,
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+ .config_reg = 0x3304,
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+ .status_reg = 0x331c,
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+ .config_val = 0x7845c665,
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+ .droop_reg = 0x3314,
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+ .droop_val = 0x0108c000,
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+ .min_rate = 600000000UL,
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+ .max_rate = 1800000000UL,
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+};
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+
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+static struct hfpll_data hfpll_l2_data = {
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+ .mode_reg = 0x3400,
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+ .l_reg = 0x3408,
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+ .m_reg = 0x340c,
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+ .n_reg = 0x3410,
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+ .config_reg = 0x3404,
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+ .status_reg = 0x341c,
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+ .config_val = 0x7845c665,
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+ .droop_reg = 0x3414,
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+ .droop_val = 0x0108c000,
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+ .min_rate = 600000000UL,
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+ .max_rate = 1800000000UL,
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+};
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+
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+static struct clk_hfpll hfpll_l2 = {
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+ .d = &hfpll_l2_data,
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+ .clkr.hw.init = &(struct clk_init_data){
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+ .parent_names = (const char *[]){ "pxo" },
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+ .num_parents = 1,
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+ .name = "hfpll_l2",
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+ .ops = &clk_ops_hfpll,
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+ .flags = CLK_IGNORE_UNUSED,
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+ },
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+ .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
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+};
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+
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static struct clk_pll pll14 = {
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.l_reg = 0x31c4,
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.m_reg = 0x31c8,
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@@ -3107,6 +3266,9 @@ static struct clk_regmap *gcc_msm8960_cl
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[PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
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[PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
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[RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
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+ [PLL9] = &hfpll0.clkr,
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+ [PLL10] = &hfpll1.clkr,
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+ [PLL12] = &hfpll_l2.clkr,
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};
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static const struct qcom_reset_map gcc_msm8960_resets[] = {
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@@ -3318,6 +3480,11 @@ static struct clk_regmap *gcc_apq8064_cl
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[PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
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[PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
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[RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
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+ [PLL9] = &hfpll0.clkr,
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+ [PLL10] = &hfpll1.clkr,
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+ [PLL12] = &hfpll_l2.clkr,
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+ [PLL16] = &hfpll2.clkr,
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+ [PLL17] = &hfpll3.clkr,
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};
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static const struct qcom_reset_map gcc_apq8064_resets[] = {
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@@ -3477,6 +3644,11 @@ static int gcc_msm8960_probe(struct plat
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if (ret)
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return ret;
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+ if (match->data == &gcc_apq8064_desc) {
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+ hfpll1.d = &hfpll1_8064_data;
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+ hfpll_l2.d = &hfpll_l2_8064_data;
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+ }
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+
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tsens = platform_device_register_data(&pdev->dev, "qcom-tsens", -1,
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NULL, 0);
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if (IS_ERR(tsens))
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--- a/include/dt-bindings/clock/qcom,gcc-msm8960.h
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+++ b/include/dt-bindings/clock/qcom,gcc-msm8960.h
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@@ -319,5 +319,7 @@
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#define CE3_SRC 303
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#define CE3_CORE_CLK 304
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#define CE3_H_CLK 305
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+#define PLL16 306
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+#define PLL17 307
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#endif
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@ -0,0 +1,134 @@
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From 3ddc3564d3c9f097986bd4ccbe34152413811335 Mon Sep 17 00:00:00 2001
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From: Stephen Boyd <sboyd@codeaurora.org>
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Date: Tue, 14 Aug 2018 17:42:27 +0530
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Subject: [PATCH 08/12] clk: qcom: Add KPSS ACC/GCC driver
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The ACC and GCC regions present in KPSSv1 contain registers to
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control clocks and power to each Krait CPU and L2. For CPUfreq
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purposes probe these devices and expose a mux clock that chooses
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between PXO and PLL8.
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Cc: <devicetree@vger.kernel.org>
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Signed-off-by: Sricharan R <sricharan@codeaurora.org>
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Tested-by: Craig Tatlor <ctatlor97@gmail.com>
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/qcom/Kconfig | 8 ++++
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drivers/clk/qcom/Makefile | 1 +
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drivers/clk/qcom/kpss-xcc.c | 87 +++++++++++++++++++++++++++++++++++++
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3 files changed, 96 insertions(+)
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create mode 100644 drivers/clk/qcom/kpss-xcc.c
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--- a/drivers/clk/qcom/Kconfig
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+++ b/drivers/clk/qcom/Kconfig
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@@ -284,3 +284,11 @@ config QCOM_HFPLL
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Support for the high-frequency PLLs present on Qualcomm devices.
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Say Y if you want to support CPU frequency scaling on devices
|
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such as MSM8974, APQ8084, etc.
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+
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+config KPSS_XCC
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+ tristate "KPSS Clock Controller"
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+ depends on COMMON_CLK_QCOM
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+ help
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+ Support for the Krait ACC and GCC clock controllers. Say Y
|
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+ if you want to support CPU frequency scaling on devices such
|
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+ as MSM8960, APQ8064, etc.
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--- a/drivers/clk/qcom/Makefile
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+++ b/drivers/clk/qcom/Makefile
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@@ -45,4 +45,5 @@ obj-$(CONFIG_SDM_DISPCC_845) += dispcc-s
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obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
|
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obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
|
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obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
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+obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
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obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
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--- /dev/null
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+++ b/drivers/clk/qcom/kpss-xcc.c
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@@ -0,0 +1,87 @@
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+// SPDX-License-Identifier: GPL-2.0
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+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
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+
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/module.h>
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+#include <linux/platform_device.h>
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+#include <linux/err.h>
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+#include <linux/io.h>
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+#include <linux/of.h>
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+#include <linux/of_device.h>
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+#include <linux/clk.h>
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+#include <linux/clk-provider.h>
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+
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+static const char *aux_parents[] = {
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+ "pll8_vote",
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+ "pxo",
|
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+};
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+
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+static unsigned int aux_parent_map[] = {
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+ 3,
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+ 0,
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+};
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+
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+static const struct of_device_id kpss_xcc_match_table[] = {
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+ { .compatible = "qcom,kpss-acc-v1", .data = (void *)1UL },
|
||||
+ { .compatible = "qcom,kpss-gcc" },
|
||||
+ {}
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, kpss_xcc_match_table);
|
||||
+
|
||||
+static int kpss_xcc_driver_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ const struct of_device_id *id;
|
||||
+ struct clk *clk;
|
||||
+ struct resource *res;
|
||||
+ void __iomem *base;
|
||||
+ const char *name;
|
||||
+
|
||||
+ id = of_match_device(kpss_xcc_match_table, &pdev->dev);
|
||||
+ if (!id)
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ base = devm_ioremap_resource(&pdev->dev, res);
|
||||
+ if (IS_ERR(base))
|
||||
+ return PTR_ERR(base);
|
||||
+
|
||||
+ if (id->data) {
|
||||
+ if (of_property_read_string_index(pdev->dev.of_node,
|
||||
+ "clock-output-names",
|
||||
+ 0, &name))
|
||||
+ return -ENODEV;
|
||||
+ base += 0x14;
|
||||
+ } else {
|
||||
+ name = "acpu_l2_aux";
|
||||
+ base += 0x28;
|
||||
+ }
|
||||
+
|
||||
+ clk = clk_register_mux_table(&pdev->dev, name, aux_parents,
|
||||
+ ARRAY_SIZE(aux_parents), 0, base, 0, 0x3,
|
||||
+ 0, aux_parent_map, NULL);
|
||||
+
|
||||
+ platform_set_drvdata(pdev, clk);
|
||||
+
|
||||
+ return PTR_ERR_OR_ZERO(clk);
|
||||
+}
|
||||
+
|
||||
+static int kpss_xcc_driver_remove(struct platform_device *pdev)
|
||||
+{
|
||||
+ clk_unregister_mux(platform_get_drvdata(pdev));
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct platform_driver kpss_xcc_driver = {
|
||||
+ .probe = kpss_xcc_driver_probe,
|
||||
+ .remove = kpss_xcc_driver_remove,
|
||||
+ .driver = {
|
||||
+ .name = "kpss-xcc",
|
||||
+ .of_match_table = kpss_xcc_match_table,
|
||||
+ },
|
||||
+};
|
||||
+module_platform_driver(kpss_xcc_driver);
|
||||
+
|
||||
+MODULE_DESCRIPTION("Krait Processor Sub System (KPSS) Clock Driver");
|
||||
+MODULE_LICENSE("GPL v2");
|
||||
+MODULE_ALIAS("platform:kpss-xcc");
|
||||
@ -0,0 +1,99 @@
|
||||
From 40e5ddf4f84869815129551f4a8cfc2c223ebeae Mon Sep 17 00:00:00 2001
|
||||
From: Stephen Boyd <sboyd@codeaurora.org>
|
||||
Date: Tue, 14 Aug 2018 17:42:28 +0530
|
||||
Subject: [PATCH 09/12] dt-bindings: arm: Document qcom,kpss-gcc
|
||||
|
||||
The ACC and GCC regions present in KPSSv1 contain registers to
|
||||
control clocks and power to each Krait CPU and L2. Documenting
|
||||
the bindings here.
|
||||
|
||||
Reviewed-by: Rob Herring <robh@kernel.org>
|
||||
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
||||
Tested-by: Craig Tatlor <ctatlor97@gmail.com>
|
||||
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
||||
---
|
||||
.../bindings/arm/msm/qcom,kpss-acc.txt | 19 ++++++++
|
||||
.../bindings/arm/msm/qcom,kpss-gcc.txt | 44 +++++++++++++++++++
|
||||
2 files changed, 63 insertions(+)
|
||||
create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
|
||||
|
||||
--- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
|
||||
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
|
||||
@@ -21,10 +21,29 @@ PROPERTIES
|
||||
the register region. An optional second element specifies
|
||||
the base address and size of the alias register region.
|
||||
|
||||
+- clocks:
|
||||
+ Usage: required
|
||||
+ Value type: <prop-encoded-array>
|
||||
+ Definition: reference to the pll parents.
|
||||
+
|
||||
+- clock-names:
|
||||
+ Usage: required
|
||||
+ Value type: <stringlist>
|
||||
+ Definition: must be "pll8_vote", "pxo".
|
||||
+
|
||||
+- clock-output-names:
|
||||
+ Usage: optional
|
||||
+ Value type: <string>
|
||||
+ Definition: Name of the output clock. Typically acpuX_aux where X is a
|
||||
+ CPU number starting at 0.
|
||||
+
|
||||
Example:
|
||||
|
||||
clock-controller@2088000 {
|
||||
compatible = "qcom,kpss-acc-v2";
|
||||
reg = <0x02088000 0x1000>,
|
||||
<0x02008000 0x1000>;
|
||||
+ clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
|
||||
+ clock-names = "pll8_vote", "pxo";
|
||||
+ clock-output-names = "acpu0_aux";
|
||||
};
|
||||
--- /dev/null
|
||||
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
|
||||
@@ -0,0 +1,44 @@
|
||||
+Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
|
||||
+
|
||||
+PROPERTIES
|
||||
+
|
||||
+- compatible:
|
||||
+ Usage: required
|
||||
+ Value type: <string>
|
||||
+ Definition: should be one of the following. The generic compatible
|
||||
+ "qcom,kpss-gcc" should also be included.
|
||||
+ "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"
|
||||
+ "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc"
|
||||
+ "qcom,kpss-gcc-msm8974", "qcom,kpss-gcc"
|
||||
+ "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc"
|
||||
+
|
||||
+- reg:
|
||||
+ Usage: required
|
||||
+ Value type: <prop-encoded-array>
|
||||
+ Definition: base address and size of the register region
|
||||
+
|
||||
+- clocks:
|
||||
+ Usage: required
|
||||
+ Value type: <prop-encoded-array>
|
||||
+ Definition: reference to the pll parents.
|
||||
+
|
||||
+- clock-names:
|
||||
+ Usage: required
|
||||
+ Value type: <stringlist>
|
||||
+ Definition: must be "pll8_vote", "pxo".
|
||||
+
|
||||
+- clock-output-names:
|
||||
+ Usage: required
|
||||
+ Value type: <string>
|
||||
+ Definition: Name of the output clock. Typically acpu_l2_aux indicating
|
||||
+ an L2 cache auxiliary clock.
|
||||
+
|
||||
+Example:
|
||||
+
|
||||
+ l2cc: clock-controller@2011000 {
|
||||
+ compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc";
|
||||
+ reg = <0x2011000 0x1000>;
|
||||
+ clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
|
||||
+ clock-names = "pll8_vote", "pxo";
|
||||
+ clock-output-names = "acpu_l2_aux";
|
||||
+ };
|
||||
@ -0,0 +1,55 @@
|
||||
From bf4503ccf321811192cb07f9711556237c3cf668 Mon Sep 17 00:00:00 2001
|
||||
From: Stephen Boyd <sboyd@codeaurora.org>
|
||||
Date: Tue, 14 Aug 2018 17:42:30 +0530
|
||||
Subject: [PATCH 11/12] dt-bindings: clock: Document qcom,krait-cc
|
||||
|
||||
The Krait clock controller controls the krait CPU and the L2 clocks
|
||||
consisting a primary mux and secondary mux. Add document for that.
|
||||
|
||||
Reviewed-by: Rob Herring <robh@kernel.org>
|
||||
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
||||
Tested-by: Craig Tatlor <ctatlor97@gmail.com>
|
||||
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
||||
---
|
||||
.../bindings/clock/qcom,krait-cc.txt | 34 +++++++++++++++++++
|
||||
1 file changed, 34 insertions(+)
|
||||
create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
|
||||
|
||||
--- /dev/null
|
||||
+++ b/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
|
||||
@@ -0,0 +1,34 @@
|
||||
+Krait Clock Controller
|
||||
+
|
||||
+PROPERTIES
|
||||
+
|
||||
+- compatible:
|
||||
+ Usage: required
|
||||
+ Value type: <string>
|
||||
+ Definition: must be one of:
|
||||
+ "qcom,krait-cc-v1"
|
||||
+ "qcom,krait-cc-v2"
|
||||
+
|
||||
+- #clock-cells:
|
||||
+ Usage: required
|
||||
+ Value type: <u32>
|
||||
+ Definition: must be 1
|
||||
+
|
||||
+- clocks:
|
||||
+ Usage: required
|
||||
+ Value type: <prop-encoded-array>
|
||||
+ Definition: reference to the clock parents of hfpll, secondary muxes.
|
||||
+
|
||||
+- clock-names:
|
||||
+ Usage: required
|
||||
+ Value type: <stringlist>
|
||||
+ Definition: must be "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb".
|
||||
+
|
||||
+Example:
|
||||
+
|
||||
+ kraitcc: clock-controller {
|
||||
+ compatible = "qcom,krait-cc-v1";
|
||||
+ clocks = <&hfpll0>, <&hfpll1>, <&acpu0_aux>, <&acpu1_aux>, <qsb>;
|
||||
+ clock-names = "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb";
|
||||
+ #clock-cells = <1>;
|
||||
+ };
|
||||
@ -1,195 +0,0 @@
|
||||
From patchwork Fri Dec 8 09:42:20 2017
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [v4,02/12] clk: mux: Split out register accessors for reuse
|
||||
From: Sricharan R <sricharan@codeaurora.org>
|
||||
X-Patchwork-Id: 10102103
|
||||
Message-Id: <1512726150-7204-3-git-send-email-sricharan@codeaurora.org>
|
||||
To: mturquette@baylibre.com, sboyd@codeaurora.org,
|
||||
devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
|
||||
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
|
||||
viresh.kumar@linaro.org, linux-arm-kernel@lists.infradead.org
|
||||
Cc: sricharan@codeaurora.org
|
||||
Date: Fri, 8 Dec 2017 15:12:20 +0530
|
||||
|
||||
From: Stephen Boyd <sboyd@codeaurora.org>
|
||||
|
||||
We want to reuse the logic in clk-mux.c for other clock drivers
|
||||
that don't use readl as register accessors. Fortunately, there
|
||||
really isn't much to the mux code besides the table indirection
|
||||
and quirk flags if you assume any bit shifting and masking has
|
||||
been done already. Pull that logic out into reusable functions
|
||||
that operate on an optional table and some flags so that other
|
||||
drivers can use the same logic.
|
||||
|
||||
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
---
|
||||
drivers/clk/clk-mux.c | 75 +++++++++++++++++++++++++++-----------------
|
||||
include/linux/clk-provider.h | 9 ++++--
|
||||
2 files changed, 54 insertions(+), 30 deletions(-)
|
||||
|
||||
--- a/drivers/clk/clk-mux.c
|
||||
+++ b/drivers/clk/clk-mux.c
|
||||
@@ -26,35 +26,24 @@
|
||||
* parent - parent is adjustable through clk_set_parent
|
||||
*/
|
||||
|
||||
-static u8 clk_mux_get_parent(struct clk_hw *hw)
|
||||
+unsigned int clk_mux_get_parent(struct clk_hw *hw, unsigned int val,
|
||||
+ unsigned int *table, unsigned long flags)
|
||||
{
|
||||
- struct clk_mux *mux = to_clk_mux(hw);
|
||||
int num_parents = clk_hw_get_num_parents(hw);
|
||||
- u32 val;
|
||||
-
|
||||
- /*
|
||||
- * FIXME need a mux-specific flag to determine if val is bitwise or numeric
|
||||
- * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
|
||||
- * to 0x7 (index starts at one)
|
||||
- * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
|
||||
- * val = 0x4 really means "bit 2, index starts at bit 0"
|
||||
- */
|
||||
- val = clk_readl(mux->reg) >> mux->shift;
|
||||
- val &= mux->mask;
|
||||
|
||||
- if (mux->table) {
|
||||
+ if (table) {
|
||||
int i;
|
||||
|
||||
for (i = 0; i < num_parents; i++)
|
||||
- if (mux->table[i] == val)
|
||||
+ if (table[i] == val)
|
||||
return i;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
- if (val && (mux->flags & CLK_MUX_INDEX_BIT))
|
||||
+ if (val && (flags & CLK_MUX_INDEX_BIT))
|
||||
val = ffs(val) - 1;
|
||||
|
||||
- if (val && (mux->flags & CLK_MUX_INDEX_ONE))
|
||||
+ if (val && (flags & CLK_MUX_INDEX_ONE))
|
||||
val--;
|
||||
|
||||
if (val >= num_parents)
|
||||
@@ -62,23 +51,53 @@ static u8 clk_mux_get_parent(struct clk_
|
||||
|
||||
return val;
|
||||
}
|
||||
+EXPORT_SYMBOL_GPL(clk_mux_get_parent);
|
||||
|
||||
-static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
|
||||
+static u8 _clk_mux_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_mux *mux = to_clk_mux(hw);
|
||||
u32 val;
|
||||
- unsigned long flags = 0;
|
||||
|
||||
- if (mux->table) {
|
||||
- index = mux->table[index];
|
||||
+ /*
|
||||
+ * FIXME need a mux-specific flag to determine if val is bitwise or
|
||||
+ * numeric e.g. sys_clkin_ck's clksel field is 3 bits wide,
|
||||
+ * but ranges from 0x1 to 0x7 (index starts at one)
|
||||
+ * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
|
||||
+ * val = 0x4 really means "bit 2, index starts at bit 0"
|
||||
+ */
|
||||
+ val = clk_readl(mux->reg) >> mux->shift;
|
||||
+ val &= mux->mask;
|
||||
+
|
||||
+ return clk_mux_get_parent(hw, val, mux->table, mux->flags);
|
||||
+}
|
||||
+
|
||||
+unsigned int clk_mux_reindex(u8 index, unsigned int *table,
|
||||
+ unsigned long flags)
|
||||
+{
|
||||
+ unsigned int val = index;
|
||||
+
|
||||
+ if (table) {
|
||||
+ val = table[val];
|
||||
} else {
|
||||
- if (mux->flags & CLK_MUX_INDEX_BIT)
|
||||
- index = 1 << index;
|
||||
+ if (flags & CLK_MUX_INDEX_BIT)
|
||||
+ val = 1 << index;
|
||||
|
||||
- if (mux->flags & CLK_MUX_INDEX_ONE)
|
||||
- index++;
|
||||
+ if (flags & CLK_MUX_INDEX_ONE)
|
||||
+ val++;
|
||||
}
|
||||
|
||||
+ return val;
|
||||
+}
|
||||
+EXPORT_SYMBOL_GPL(clk_mux_reindex);
|
||||
+
|
||||
+static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
|
||||
+{
|
||||
+ struct clk_mux *mux = to_clk_mux(hw);
|
||||
+ u32 val;
|
||||
+ unsigned long flags = 0;
|
||||
+
|
||||
+ index = clk_mux_reindex(index, mux->table, mux->flags);
|
||||
+
|
||||
if (mux->lock)
|
||||
spin_lock_irqsave(mux->lock, flags);
|
||||
else
|
||||
@@ -110,14 +129,14 @@ static int clk_mux_determine_rate(struct
|
||||
}
|
||||
|
||||
const struct clk_ops clk_mux_ops = {
|
||||
- .get_parent = clk_mux_get_parent,
|
||||
+ .get_parent = _clk_mux_get_parent,
|
||||
.set_parent = clk_mux_set_parent,
|
||||
.determine_rate = clk_mux_determine_rate,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_mux_ops);
|
||||
|
||||
const struct clk_ops clk_mux_ro_ops = {
|
||||
- .get_parent = clk_mux_get_parent,
|
||||
+ .get_parent = _clk_mux_get_parent,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_mux_ro_ops);
|
||||
|
||||
@@ -125,7 +144,7 @@ struct clk_hw *clk_hw_register_mux_table
|
||||
const char * const *parent_names, u8 num_parents,
|
||||
unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u32 mask,
|
||||
- u8 clk_mux_flags, u32 *table, spinlock_t *lock)
|
||||
+ u8 clk_mux_flags, unsigned int *table, spinlock_t *lock)
|
||||
{
|
||||
struct clk_mux *mux;
|
||||
struct clk_hw *hw;
|
||||
--- a/include/linux/clk-provider.h
|
||||
+++ b/include/linux/clk-provider.h
|
||||
@@ -468,7 +468,7 @@ void clk_hw_unregister_divider(struct cl
|
||||
struct clk_mux {
|
||||
struct clk_hw hw;
|
||||
void __iomem *reg;
|
||||
- u32 *table;
|
||||
+ unsigned int *table;
|
||||
u32 mask;
|
||||
u8 shift;
|
||||
u8 flags;
|
||||
@@ -486,6 +486,11 @@ struct clk_mux {
|
||||
extern const struct clk_ops clk_mux_ops;
|
||||
extern const struct clk_ops clk_mux_ro_ops;
|
||||
|
||||
+unsigned int clk_mux_get_parent(struct clk_hw *hw, unsigned int val,
|
||||
+ unsigned int *table, unsigned long flags);
|
||||
+unsigned int clk_mux_reindex(u8 index, unsigned int *table,
|
||||
+ unsigned long flags);
|
||||
+
|
||||
struct clk *clk_register_mux(struct device *dev, const char *name,
|
||||
const char * const *parent_names, u8 num_parents,
|
||||
unsigned long flags,
|
||||
@@ -506,7 +511,7 @@ struct clk_hw *clk_hw_register_mux_table
|
||||
const char * const *parent_names, u8 num_parents,
|
||||
unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u32 mask,
|
||||
- u8 clk_mux_flags, u32 *table, spinlock_t *lock);
|
||||
+ u8 clk_mux_flags, unsigned int *table, spinlock_t *lock);
|
||||
|
||||
void clk_unregister_mux(struct clk *clk);
|
||||
void clk_hw_unregister_mux(struct clk_hw *hw);
|
||||
@ -1,209 +0,0 @@
|
||||
From patchwork Fri Dec 8 09:42:26 2017
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [v4,08/12] clk: qcom: Add KPSS ACC/GCC driver
|
||||
From: Sricharan R <sricharan@codeaurora.org>
|
||||
X-Patchwork-Id: 10102023
|
||||
Message-Id: <1512726150-7204-9-git-send-email-sricharan@codeaurora.org>
|
||||
To: mturquette@baylibre.com, sboyd@codeaurora.org,
|
||||
devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
|
||||
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
|
||||
viresh.kumar@linaro.org, linux-arm-kernel@lists.infradead.org
|
||||
Cc: sricharan@codeaurora.org
|
||||
Date: Fri, 8 Dec 2017 15:12:26 +0530
|
||||
|
||||
From: Stephen Boyd <sboyd@codeaurora.org>
|
||||
|
||||
The ACC and GCC regions present in KPSSv1 contain registers to
|
||||
control clocks and power to each Krait CPU and L2. For CPUfreq
|
||||
purposes probe these devices and expose a mux clock that chooses
|
||||
between PXO and PLL8.
|
||||
|
||||
Cc: <devicetree@vger.kernel.org>
|
||||
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
---
|
||||
.../devicetree/bindings/arm/msm/qcom,kpss-acc.txt | 7 ++
|
||||
.../devicetree/bindings/arm/msm/qcom,kpss-gcc.txt | 28 +++++++
|
||||
drivers/clk/qcom/Kconfig | 8 ++
|
||||
drivers/clk/qcom/Makefile | 1 +
|
||||
drivers/clk/qcom/kpss-xcc.c | 96 ++++++++++++++++++++++
|
||||
5 files changed, 140 insertions(+)
|
||||
create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
|
||||
create mode 100644 drivers/clk/qcom/kpss-xcc.c
|
||||
|
||||
--- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
|
||||
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
|
||||
@@ -21,10 +21,17 @@ PROPERTIES
|
||||
the register region. An optional second element specifies
|
||||
the base address and size of the alias register region.
|
||||
|
||||
+- clock-output-names:
|
||||
+ Usage: optional
|
||||
+ Value type: <string>
|
||||
+ Definition: Name of the output clock. Typically acpuX_aux where X is a
|
||||
+ CPU number starting at 0.
|
||||
+
|
||||
Example:
|
||||
|
||||
clock-controller@2088000 {
|
||||
compatible = "qcom,kpss-acc-v2";
|
||||
reg = <0x02088000 0x1000>,
|
||||
<0x02008000 0x1000>;
|
||||
+ clock-output-names = "acpu0_aux";
|
||||
};
|
||||
--- /dev/null
|
||||
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
|
||||
@@ -0,0 +1,28 @@
|
||||
+Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
|
||||
+
|
||||
+PROPERTIES
|
||||
+
|
||||
+- compatible:
|
||||
+ Usage: required
|
||||
+ Value type: <string>
|
||||
+ Definition: should be one of:
|
||||
+ "qcom,kpss-gcc"
|
||||
+
|
||||
+- reg:
|
||||
+ Usage: required
|
||||
+ Value type: <prop-encoded-array>
|
||||
+ Definition: base address and size of the register region
|
||||
+
|
||||
+- clock-output-names:
|
||||
+ Usage: required
|
||||
+ Value type: <string>
|
||||
+ Definition: Name of the output clock. Typically acpu_l2_aux indicating
|
||||
+ an L2 cache auxiliary clock.
|
||||
+
|
||||
+Example:
|
||||
+
|
||||
+ l2cc: clock-controller@2011000 {
|
||||
+ compatible = "qcom,kpss-gcc";
|
||||
+ reg = <0x2011000 0x1000>;
|
||||
+ clock-output-names = "acpu_l2_aux";
|
||||
+ };
|
||||
--- a/drivers/clk/qcom/Kconfig
|
||||
+++ b/drivers/clk/qcom/Kconfig
|
||||
@@ -205,6 +205,14 @@ config QCOM_HFPLL
|
||||
Say Y if you want to support CPU frequency scaling on devices
|
||||
such as MSM8974, APQ8084, etc.
|
||||
|
||||
+config KPSS_XCC
|
||||
+ tristate "KPSS Clock Controller"
|
||||
+ depends on COMMON_CLK_QCOM
|
||||
+ help
|
||||
+ Support for the Krait ACC and GCC clock controllers. Say Y
|
||||
+ if you want to support CPU frequency scaling on devices such
|
||||
+ as MSM8960, APQ8064, etc.
|
||||
+
|
||||
config KRAIT_CLOCKS
|
||||
bool
|
||||
select KRAIT_L2_ACCESSORS
|
||||
--- a/drivers/clk/qcom/Makefile
|
||||
+++ b/drivers/clk/qcom/Makefile
|
||||
@@ -36,4 +36,5 @@ obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8
|
||||
obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
|
||||
obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
|
||||
obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
|
||||
+obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
|
||||
obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/clk/qcom/kpss-xcc.c
|
||||
@@ -0,0 +1,96 @@
|
||||
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify
|
||||
+ * it under the terms of the GNU General Public License version 2 and
|
||||
+ * only version 2 as published by the Free Software Foundation.
|
||||
+ *
|
||||
+ * This program is distributed in the hope that it will be useful,
|
||||
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
+ * GNU General Public License for more details.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/err.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/of.h>
|
||||
+#include <linux/of_device.h>
|
||||
+#include <linux/clk.h>
|
||||
+#include <linux/clk-provider.h>
|
||||
+
|
||||
+static const char *aux_parents[] = {
|
||||
+ "pll8_vote",
|
||||
+ "pxo",
|
||||
+};
|
||||
+
|
||||
+static unsigned int aux_parent_map[] = {
|
||||
+ 3,
|
||||
+ 0,
|
||||
+};
|
||||
+
|
||||
+static const struct of_device_id kpss_xcc_match_table[] = {
|
||||
+ { .compatible = "qcom,kpss-acc-v1", .data = (void *)1UL },
|
||||
+ { .compatible = "qcom,kpss-gcc" },
|
||||
+ {}
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, kpss_xcc_match_table);
|
||||
+
|
||||
+static int kpss_xcc_driver_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ const struct of_device_id *id;
|
||||
+ struct clk *clk;
|
||||
+ struct resource *res;
|
||||
+ void __iomem *base;
|
||||
+ const char *name;
|
||||
+
|
||||
+ id = of_match_device(kpss_xcc_match_table, &pdev->dev);
|
||||
+ if (!id)
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ base = devm_ioremap_resource(&pdev->dev, res);
|
||||
+ if (IS_ERR(base))
|
||||
+ return PTR_ERR(base);
|
||||
+
|
||||
+ if (id->data) {
|
||||
+ if (of_property_read_string_index(pdev->dev.of_node,
|
||||
+ "clock-output-names",
|
||||
+ 0, &name))
|
||||
+ return -ENODEV;
|
||||
+ base += 0x14;
|
||||
+ } else {
|
||||
+ name = "acpu_l2_aux";
|
||||
+ base += 0x28;
|
||||
+ }
|
||||
+
|
||||
+ clk = clk_register_mux_table(&pdev->dev, name, aux_parents,
|
||||
+ ARRAY_SIZE(aux_parents), 0, base, 0, 0x3,
|
||||
+ 0, aux_parent_map, NULL);
|
||||
+
|
||||
+ platform_set_drvdata(pdev, clk);
|
||||
+
|
||||
+ return PTR_ERR_OR_ZERO(clk);
|
||||
+}
|
||||
+
|
||||
+static int kpss_xcc_driver_remove(struct platform_device *pdev)
|
||||
+{
|
||||
+ clk_unregister_mux(platform_get_drvdata(pdev));
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct platform_driver kpss_xcc_driver = {
|
||||
+ .probe = kpss_xcc_driver_probe,
|
||||
+ .remove = kpss_xcc_driver_remove,
|
||||
+ .driver = {
|
||||
+ .name = "kpss-xcc",
|
||||
+ .of_match_table = kpss_xcc_match_table,
|
||||
+ },
|
||||
+};
|
||||
+module_platform_driver(kpss_xcc_driver);
|
||||
+
|
||||
+MODULE_DESCRIPTION("Krait Processor Sub System (KPSS) Clock Driver");
|
||||
+MODULE_LICENSE("GPL v2");
|
||||
+MODULE_ALIAS("platform:kpss-xcc");
|
||||
@ -1,72 +0,0 @@
|
||||
From c7c6a0f50f9ac3620c611ce06ba1f9fafea0444e Mon Sep 17 00:00:00 2001
|
||||
From: Archit Taneja <architt@codeaurora.org>
|
||||
Date: Mon, 3 Aug 2015 10:38:14 +0530
|
||||
Subject: [PATCH 47/69] mtd: nand: Create a BBT flag to access bad block
|
||||
markers in raw mode
|
||||
|
||||
Some controllers can access the factory bad block marker from OOB only
|
||||
when they read it in raw mode. When ECC is enabled, these controllers
|
||||
discard reading/writing bad block markers, preventing access to them
|
||||
altogether.
|
||||
|
||||
The bbt driver assumes MTD_OPS_PLACE_OOB when scanning for bad blocks.
|
||||
This results in the nand driver's ecc->read_oob() op to be called, which
|
||||
works with ECC enabled.
|
||||
|
||||
Create a new BBT option flag that tells nand_bbt to force the mode to
|
||||
MTD_OPS_RAW. This would result in the correct op being called for the
|
||||
underlying nand controller driver.
|
||||
|
||||
Reviewed-by: Andy Gross <agross@codeaurora.org>
|
||||
Signed-off-by: Archit Taneja <architt@codeaurora.org>
|
||||
---
|
||||
drivers/mtd/nand/nand_base.c | 6 +++++-
|
||||
drivers/mtd/nand/nand_bbt.c | 6 +++++-
|
||||
include/linux/mtd/bbm.h | 6 ++++++
|
||||
3 files changed, 16 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/mtd/nand/nand_base.c
|
||||
+++ b/drivers/mtd/nand/nand_base.c
|
||||
@@ -481,7 +481,11 @@ static int nand_default_block_markbad(st
|
||||
} else {
|
||||
ops.len = ops.ooblen = 1;
|
||||
}
|
||||
- ops.mode = MTD_OPS_PLACE_OOB;
|
||||
+
|
||||
+ if (unlikely(chip->bbt_options & NAND_BBT_ACCESS_BBM_RAW))
|
||||
+ ops.mode = MTD_OPS_RAW;
|
||||
+ else
|
||||
+ ops.mode = MTD_OPS_PLACE_OOB;
|
||||
|
||||
/* Write to first/last page(s) if necessary */
|
||||
if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
|
||||
--- a/drivers/mtd/nand/nand_bbt.c
|
||||
+++ b/drivers/mtd/nand/nand_bbt.c
|
||||
@@ -420,7 +420,11 @@ static int scan_block_fast(struct mtd_in
|
||||
ops.oobbuf = buf;
|
||||
ops.ooboffs = 0;
|
||||
ops.datbuf = NULL;
|
||||
- ops.mode = MTD_OPS_PLACE_OOB;
|
||||
+
|
||||
+ if (unlikely(bd->options & NAND_BBT_ACCESS_BBM_RAW))
|
||||
+ ops.mode = MTD_OPS_RAW;
|
||||
+ else
|
||||
+ ops.mode = MTD_OPS_PLACE_OOB;
|
||||
|
||||
for (j = 0; j < numpages; j++) {
|
||||
/*
|
||||
--- a/include/linux/mtd/bbm.h
|
||||
+++ b/include/linux/mtd/bbm.h
|
||||
@@ -116,6 +116,12 @@ struct nand_bbt_descr {
|
||||
#define NAND_BBT_NO_OOB_BBM 0x00080000
|
||||
|
||||
/*
|
||||
+ * Force MTD_OPS_RAW mode when trying to access bad block markes from OOB. To
|
||||
+ * be used by controllers which can access BBM only when ECC is disabled, i.e,
|
||||
+ * when in RAW access mode
|
||||
+ */
|
||||
+#define NAND_BBT_ACCESS_BBM_RAW 0x00100000
|
||||
+/*
|
||||
* Flag set by nand_create_default_bbt_descr(), marking that the nand_bbt_descr
|
||||
* was allocated dynamicaly and must be freed in nand_release(). Has no meaning
|
||||
* in nand_chip.bbt_options.
|
||||
@ -1,71 +0,0 @@
|
||||
From a86bda9f8a7965f0cedd347a9c04800eb9f41ea3 Mon Sep 17 00:00:00 2001
|
||||
From: Vasudevan Murugesan <vmuruges@codeaurora.org>
|
||||
Date: Tue, 21 Jul 2015 10:22:38 +0530
|
||||
Subject: ipq806x: usb: Control USB master reset
|
||||
|
||||
During removal of the glue layer(dwc3-of-simple),
|
||||
USB master reset is set to active and during insertion
|
||||
it is de-activated.
|
||||
|
||||
Change-Id: I537dc810f6cb2a46664ee674840145066432b957
|
||||
Signed-off-by: Vasudevan Murugesan <vmuruges@codeaurora.org>
|
||||
(cherry picked from commit 4611e13580a216812f85f0801b95442d02eeb836)
|
||||
---
|
||||
drivers/usb/dwc3/dwc3-of-simple.c | 22 ++++++++++++++++++++++
|
||||
1 file changed, 12 insertions(+)
|
||||
|
||||
(limited to 'drivers/usb/dwc3/dwc3-of-simple.c')
|
||||
|
||||
--- a/drivers/usb/dwc3/dwc3-of-simple.c
|
||||
+++ b/drivers/usb/dwc3/dwc3-of-simple.c
|
||||
@@ -25,6 +25,7 @@
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/clk.h>
|
||||
+#include <linux/reset.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
@@ -33,6 +34,8 @@ struct dwc3_of_simple {
|
||||
struct device *dev;
|
||||
struct clk **clks;
|
||||
int num_clocks;
|
||||
+ struct reset_control *mstr_rst_30_0;
|
||||
+ struct reset_control *mstr_rst_30_1;
|
||||
};
|
||||
|
||||
static int dwc3_of_simple_clk_init(struct dwc3_of_simple *simple, int count)
|
||||
@@ -102,6 +105,20 @@ static int dwc3_of_simple_probe(struct p
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
+ simple->mstr_rst_30_0 = devm_reset_control_get(dev, "usb30_0_mstr_rst");
|
||||
+
|
||||
+ if (!IS_ERR(simple->mstr_rst_30_0))
|
||||
+ reset_control_deassert(simple->mstr_rst_30_0);
|
||||
+ else
|
||||
+ dev_dbg(simple->dev, "cannot get handle for USB PHY 0 master reset control\n");
|
||||
+
|
||||
+ simple->mstr_rst_30_1 = devm_reset_control_get(dev, "usb30_1_mstr_rst");
|
||||
+
|
||||
+ if (!IS_ERR(simple->mstr_rst_30_1))
|
||||
+ reset_control_deassert(simple->mstr_rst_30_1);
|
||||
+ else
|
||||
+ dev_dbg(simple->dev, "cannot get handle for USB PHY 1 master reset control\n");
|
||||
+
|
||||
ret = of_platform_populate(np, NULL, NULL, dev);
|
||||
if (ret) {
|
||||
for (i = 0; i < simple->num_clocks; i++) {
|
||||
@@ -130,6 +147,12 @@ static int dwc3_of_simple_remove(struct
|
||||
clk_put(simple->clks[i]);
|
||||
}
|
||||
|
||||
+ if (!IS_ERR(simple->mstr_rst_30_0))
|
||||
+ reset_control_assert(simple->mstr_rst_30_0);
|
||||
+
|
||||
+ if (!IS_ERR(simple->mstr_rst_30_1))
|
||||
+ reset_control_assert(simple->mstr_rst_30_1);
|
||||
+
|
||||
of_platform_depopulate(dev);
|
||||
|
||||
pm_runtime_disable(dev);
|
||||
@ -0,0 +1,70 @@
|
||||
From patchwork Mon May 21 20:57:38 2018
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [v5,3/4] ARM: dts: qcom: add gpio-ranges property
|
||||
X-Patchwork-Submitter: Christian Lamparter <chunkeey@gmail.com>
|
||||
X-Patchwork-Id: 917856
|
||||
Message-Id: <0ae3376606a89bcdf3fe753a5c967f7103699e09.1526935804.git.chunkeey@gmail.com>
|
||||
To: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
|
||||
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org
|
||||
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>,
|
||||
Linus Walleij <linus.walleij@linaro.org>,
|
||||
Stephen Boyd <sboyd@kernel.org>, David Brown <david.brown@linaro.org>,
|
||||
Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,
|
||||
Andy Gross <andy.gross@linaro.org>,
|
||||
Sven Eckelmann <sven.eckelmann@openmesh.com>
|
||||
Date: Mon, 21 May 2018 22:57:38 +0200
|
||||
From: Christian Lamparter <chunkeey@gmail.com>
|
||||
List-Id: <linux-gpio.vger.kernel.org>
|
||||
|
||||
This patch adds the gpio-ranges property to almost all of
|
||||
the Qualcomm ARM platforms that utilize the pinctrl-msm
|
||||
framework.
|
||||
|
||||
The gpio-ranges property is part of the gpiolib subsystem.
|
||||
As a result, the binding text is available in section
|
||||
"2.1 gpio- and pin-controller interaction" of
|
||||
Documentation/devicetree/bindings/gpio/gpio.txt
|
||||
|
||||
For more information please see the patch titled:
|
||||
"pinctrl: msm: fix gpio-hog related boot issues" from
|
||||
this series.
|
||||
|
||||
Reported-by: Sven Eckelmann <sven.eckelmann@openmesh.com>
|
||||
Tested-by: Sven Eckelmann <sven.eckelmann@openmesh.com> [ipq4019]
|
||||
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
|
||||
---
|
||||
To help with git bisect, the DT update patch has been intentionally
|
||||
placed after the "pinctrl: msm: fix gpio-hog related boot issues".
|
||||
Otherwise - if the order was reveresed - and bisect decides to split
|
||||
between these two patches, the gpiochip_add_pin_ranges() function
|
||||
will be executed twice with the same parameters for the same pinctrl.
|
||||
---
|
||||
arch/arm/boot/dts/qcom-apq8064.dtsi | 1 +
|
||||
arch/arm/boot/dts/qcom-apq8084.dtsi | 1 +
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 1 +
|
||||
arch/arm/boot/dts/qcom-ipq8064.dtsi | 1 +
|
||||
arch/arm/boot/dts/qcom-mdm9615.dtsi | 1 +
|
||||
arch/arm/boot/dts/qcom-msm8660.dtsi | 1 +
|
||||
arch/arm/boot/dts/qcom-msm8960.dtsi | 1 +
|
||||
arch/arm/boot/dts/qcom-msm8974.dtsi | 1 +
|
||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 3 ++-
|
||||
arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 +
|
||||
arch/arm64/boot/dts/qcom/msm8992.dtsi | 1 +
|
||||
arch/arm64/boot/dts/qcom/msm8994.dtsi | 1 +
|
||||
arch/arm64/boot/dts/qcom/msm8996.dtsi | 1 +
|
||||
13 files changed, 14 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||||
@@ -653,6 +653,7 @@
|
||||
reg = <0x800000 0x4000>;
|
||||
|
||||
gpio-controller;
|
||||
+ gpio-ranges = <&qcom_pinmux 0 0 69>;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
@ -1,22 +0,0 @@
|
||||
Subject: mtd: spi-nor: add mx25l25635f with SECT_4K
|
||||
|
||||
This patch fixes an issue with the creation of the
|
||||
ubi volume on the AVM FRITZ!Box 4040. The mx25l25635f
|
||||
and mx25l25635e support SECT_4K which will set the
|
||||
erase size to 4K. This is used by ubi to calculate
|
||||
VID header offsets. Without this, uboot and linux
|
||||
disagrees about the layout and refuse to attach
|
||||
the ubi volume created by the other.
|
||||
|
||||
---
|
||||
--- a/drivers/mtd/spi-nor/spi-nor.c
|
||||
+++ b/drivers/mtd/spi-nor/spi-nor.c
|
||||
@@ -1031,7 +1031,7 @@ static const struct flash_info spi_nor_i
|
||||
{ "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
|
||||
{ "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
|
||||
{ "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
|
||||
- { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
||||
+ { "mx25l25635f", INFO(0xc22019, 0, 64 * 1024, 512, SECT_4K) },
|
||||
{ "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
|
||||
{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
|
||||
{ "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue