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@ -266,6 +266,35 @@ void ssb_chipco_resume(struct ssb_chipcommon *cc)
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chipco_powercontrol_init(cc);
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}
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void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc, u32 chip_id, u32 *rate,
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u32 *plltype, u32 *n, u32 *m)
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{
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*rate = 0;
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*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
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*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
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switch (*plltype) {
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case SSB_PLLTYPE_2:
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case SSB_PLLTYPE_4:
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case SSB_PLLTYPE_6:
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case SSB_PLLTYPE_7:
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*m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
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break;
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case SSB_PLLTYPE_5:
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*rate = 200000000;
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break;
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case SSB_PLLTYPE_3:
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/* 5350 uses m2 to control mips */
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*m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
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break;
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default:
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*m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
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break;
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}
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if (*rate == 0 && chip_id == 0x5365)
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*rate = 200000000;
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}
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void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
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u32 *plltype, u32 *n, u32 *m)
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{
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