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@ -92,10 +92,6 @@ struct tnetd7200_clocks {
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struct tnetd7200_clock usb;
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} __attribute__ ((packed));
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int ar7_afe_clock = 35328000;
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int ar7_ref_clock = 25000000;
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int ar7_xtal_clock = 24000000;
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int ar7_cpu_clock = 150000000;
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EXPORT_SYMBOL(ar7_cpu_clock);
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int ar7_bus_clock = 125000000;
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@ -182,7 +178,7 @@ static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock,
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u32 *bootcr, u32 bus_clock)
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{
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int product;
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int base_clock = ar7_ref_clock;
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int base_clock = AR7_REF_CLOCK;
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u32 ctrl = clock->ctrl;
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u32 pll = clock->pll;
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int prediv = ((ctrl & PREDIV_MASK) >> PREDIV_SHIFT) + 1;
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@ -195,10 +191,10 @@ static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock,
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base_clock = bus_clock;
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break;
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case BOOT_PLL_SOURCE_REF:
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base_clock = ar7_ref_clock;
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base_clock = AR7_REF_CLOCK;
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break;
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case BOOT_PLL_SOURCE_XTAL:
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base_clock = ar7_xtal_clock;
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base_clock = AR7_XTAL_CLOCK;
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break;
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case BOOT_PLL_SOURCE_CPU:
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base_clock = ar7_cpu_clock;
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@ -236,10 +232,10 @@ static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
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base_clock = ar7_bus_clock;
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break;
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case BOOT_PLL_SOURCE_REF:
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base_clock = ar7_ref_clock;
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base_clock = AR7_REF_CLOCK;
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break;
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case BOOT_PLL_SOURCE_XTAL:
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base_clock = ar7_xtal_clock;
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base_clock = AR7_XTAL_CLOCK;
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break;
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case BOOT_PLL_SOURCE_CPU:
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base_clock = ar7_cpu_clock;
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@ -264,11 +260,11 @@ static void __init tnetd7300_init_clocks(void)
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struct tnetd7300_clocks *clocks = (struct tnetd7300_clocks *)ioremap_nocache(AR7_REGS_POWER + 0x20, sizeof(struct tnetd7300_clocks));
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ar7_bus_clock = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,
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&clocks->bus, bootcr, ar7_afe_clock);
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&clocks->bus, bootcr, AR7_AFE_CLOCK);
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if (*bootcr & BOOT_PLL_ASYNC_MODE) {
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ar7_cpu_clock = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT,
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&clocks->cpu, bootcr, ar7_afe_clock);
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&clocks->cpu, bootcr, AR7_AFE_CLOCK);
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} else {
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ar7_cpu_clock = ar7_bus_clock;
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}
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@ -334,23 +330,23 @@ static int tnetd7200_get_clock_base(int clock_id, u32 *bootcr)
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// Async
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switch (clock_id) {
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case TNETD7200_CLOCK_ID_DSP:
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return ar7_ref_clock;
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return AR7_REF_CLOCK;
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default:
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return ar7_afe_clock;
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}
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return AR7_AFE_CLOCK;
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}
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} else {
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// Sync
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if (*bootcr & BOOT_PLL_2TO1_MODE) {
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// 2:1
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switch (clock_id) {
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case TNETD7200_CLOCK_ID_DSP:
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return ar7_ref_clock;
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return AR7_REF_CLOCK;
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default:
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return ar7_afe_clock;
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return AR7_AFE_CLOCK;
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}
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} else {
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// 1:1
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return ar7_ref_clock;
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return AR7_REF_CLOCK;
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}
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}
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}
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