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cns3xxx: move laguna.c changes out of patches, update it in files/

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Signed-off-by: Felix Fietkau <nbd@nbd.name>
v19.07.3_mercusys_ac12_duma
Felix Fietkau 8 years ago
parent 413eb04e1e
commit 58fbe07560
3 changed files with 64 additions and 133 deletions
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70
target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/laguna.c
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@ -21,6 +21,7 @@
#include <linux/kernel.h>
#include <linux/compiler.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/dma-mapping.h>
#include <linux/serial_core.h>
@ -864,7 +865,6 @@ static struct map_desc laguna_io_desc[] __initdata = {
static void __init laguna_map_io(void)
{
cns3xxx_map_io();
cns3xxx_pcie_iotable_init();
iotable_init(ARRAY_AND_SIZE(laguna_io_desc));
laguna_early_serial_setup();
}
@ -888,14 +888,46 @@ static int laguna_register_gpio(struct gpio *array, size_t num)
return ret;
}
static int __init laguna_pcie_init(void)
/* allow disabling of external isolated PCIe IRQs */
static int cns3xxx_pciextirq = 1;
static int __init cns3xxx_pciextirq_disable(char *s)
{
cns3xxx_pciextirq = 0;
return 1;
}
__setup("noextirq", cns3xxx_pciextirq_disable);
static int __init laguna_pcie_init_irq(void)
{
u32 __iomem *mem = (void __iomem *)(CNS3XXX_GPIOB_BASE_VIRT + 0x0004);
u32 reg = (__raw_readl(mem) >> 26) & 0xf;
int irqs[] = {
IRQ_CNS3XXX_EXTERNAL_PIN0,
IRQ_CNS3XXX_EXTERNAL_PIN1,
IRQ_CNS3XXX_EXTERNAL_PIN2,
154,
};
if (!machine_is_gw2388())
return 0;
return cns3xxx_pcie_init();
/* Verify GPIOB[26:29] == 0001b indicating support for ext irqs */
if (cns3xxx_pciextirq && reg != 1)
cns3xxx_pciextirq = 0;
if (cns3xxx_pciextirq) {
printk("laguna: using isolated PCI interrupts:"
" irq%d/irq%d/irq%d/irq%d\n",
irqs[0], irqs[1], irqs[2], irqs[3]);
cns3xxx_pcie_set_irqs(0, irqs);
} else {
printk("laguna: using shared PCI interrupts: irq%d\n",
IRQ_CNS3XXX_PCIE0_DEVICE);
}
return 0;
}
subsys_initcall(laguna_pcie_init);
subsys_initcall(laguna_pcie_init_irq);
static int __init laguna_model_setup(void)
{
@ -908,8 +940,33 @@ static int __init laguna_model_setup(void)
printk("Running on Gateworks Laguna %s\n", laguna_info.model);
cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
NR_IRQS_CNS3XXX);
cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
NR_IRQS_CNS3XXX + 32);
/*
* If pcie external interrupts are supported and desired
* configure IRQ types and configure pin function.
* Note that cns3xxx_pciextirq is enabled by default, but can be
* unset via the 'noextirq' kernel param or by laguna_pcie_init() if
* the baseboard model does not support this hardware feature.
*/
if (cns3xxx_pciextirq) {
mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0018);
reg = __raw_readl(mem);
/* GPIO26 is gpio, EXT_INT[0:2] not gpio func */
reg &= ~0x3c000000;
reg |= 0x38000000;
__raw_writel(reg, mem);
cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT,
IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32);
irq_set_irq_type(154, IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(93, IRQ_TYPE_LEVEL_HIGH);
irq_set_irq_type(94, IRQ_TYPE_LEVEL_HIGH);
irq_set_irq_type(95, IRQ_TYPE_LEVEL_HIGH);
} else {
cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT,
IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32);
}
if (strncmp(laguna_info.model, "GW", 2) == 0) {
if (laguna_info.config_bitmap & ETH0_LOAD)
@ -1099,5 +1156,6 @@ MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform")
.init_irq = cns3xxx_init_irq,
.init_time = cns3xxx_timer_init,
.init_machine = laguna_init,
.init_late = cns3xxx_pcie_init_late,
.restart = cns3xxx_restart,
MACHINE_END

33
target/linux/cns3xxx/patches-4.4/031-pcie_init.patch
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@ -1,33 +0,0 @@
--- a/arch/arm/mach-cns3xxx/laguna.c
+++ b/arch/arm/mach-cns3xxx/laguna.c
@@ -864,7 +864,6 @@ static struct map_desc laguna_io_desc[]
static void __init laguna_map_io(void)
{
cns3xxx_map_io();
- cns3xxx_pcie_iotable_init();
iotable_init(ARRAY_AND_SIZE(laguna_io_desc));
laguna_early_serial_setup();
}
@@ -888,15 +887,6 @@ static int laguna_register_gpio(struct g
return ret;
}
-static int __init laguna_pcie_init(void)
-{
- if (!machine_is_gw2388())
- return 0;
-
- return cns3xxx_pcie_init();
-}
-subsys_initcall(laguna_pcie_init);
-
static int __init laguna_model_setup(void)
{
u32 __iomem *mem;
@@ -1099,5 +1089,6 @@ MACHINE_START(GW2388, "Gateworks Corpora
.init_irq = cns3xxx_init_irq,
.init_time = cns3xxx_timer_init,
.init_machine = laguna_init,
+ .init_late = cns3xxx_pcie_init_late,
.restart = cns3xxx_restart,
MACHINE_END

94
target/linux/cns3xxx/patches-4.4/110-pci_isolated_interrupts.patch
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@ -1,97 +1,3 @@
--- a/arch/arm/mach-cns3xxx/laguna.c
+++ b/arch/arm/mach-cns3xxx/laguna.c
@@ -21,6 +21,7 @@
#include <linux/kernel.h>
#include <linux/compiler.h>
#include <linux/io.h>
+#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/dma-mapping.h>
#include <linux/serial_core.h>
@@ -887,6 +888,47 @@ static int laguna_register_gpio(struct g
return ret;
}
+/* allow disabling of external isolated PCIe IRQs */
+static int cns3xxx_pciextirq = 1;
+static int __init cns3xxx_pciextirq_disable(char *s)
+{
+ cns3xxx_pciextirq = 0;
+ return 1;
+}
+__setup("noextirq", cns3xxx_pciextirq_disable);
+
+static int __init laguna_pcie_init_irq(void)
+{
+ u32 __iomem *mem = (void __iomem *)(CNS3XXX_GPIOB_BASE_VIRT + 0x0004);
+ u32 reg = (__raw_readl(mem) >> 26) & 0xf;
+ int irqs[] = {
+ IRQ_CNS3XXX_EXTERNAL_PIN0,
+ IRQ_CNS3XXX_EXTERNAL_PIN1,
+ IRQ_CNS3XXX_EXTERNAL_PIN2,
+ 154,
+ };
+
+ if (!machine_is_gw2388())
+ return 0;
+
+ /* Verify GPIOB[26:29] == 0001b indicating support for ext irqs */
+ if (cns3xxx_pciextirq && reg != 1)
+ cns3xxx_pciextirq = 0;
+
+ if (cns3xxx_pciextirq) {
+ printk("laguna: using isolated PCI interrupts:"
+ " irq%d/irq%d/irq%d/irq%d\n",
+ irqs[0], irqs[1], irqs[2], irqs[3]);
+ cns3xxx_pcie_set_irqs(0, irqs);
+ } else {
+ printk("laguna: using shared PCI interrupts: irq%d\n",
+ IRQ_CNS3XXX_PCIE0_DEVICE);
+ }
+
+ return 0;
+}
+subsys_initcall(laguna_pcie_init_irq);
+
static int __init laguna_model_setup(void)
{
u32 __iomem *mem;
@@ -898,8 +940,33 @@ static int __init laguna_model_setup(voi
printk("Running on Gateworks Laguna %s\n", laguna_info.model);
cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
NR_IRQS_CNS3XXX);
- cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
- NR_IRQS_CNS3XXX + 32);
+
+ /*
+ * If pcie external interrupts are supported and desired
+ * configure IRQ types and configure pin function.
+ * Note that cns3xxx_pciextirq is enabled by default, but can be
+ * unset via the 'noextirq' kernel param or by laguna_pcie_init() if
+ * the baseboard model does not support this hardware feature.
+ */
+ if (cns3xxx_pciextirq) {
+ mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0018);
+ reg = __raw_readl(mem);
+ /* GPIO26 is gpio, EXT_INT[0:2] not gpio func */
+ reg &= ~0x3c000000;
+ reg |= 0x38000000;
+ __raw_writel(reg, mem);
+
+ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT,
+ IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32);
+
+ irq_set_irq_type(154, IRQ_TYPE_LEVEL_LOW);
+ irq_set_irq_type(93, IRQ_TYPE_LEVEL_HIGH);
+ irq_set_irq_type(94, IRQ_TYPE_LEVEL_HIGH);
+ irq_set_irq_type(95, IRQ_TYPE_LEVEL_HIGH);
+ } else {
+ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT,
+ IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32);
+ }
if (strncmp(laguna_info.model, "GW", 2) == 0) {
if (laguna_info.config_bitmap & ETH0_LOAD)
--- a/arch/arm/mach-cns3xxx/pcie.c
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -18,6 +18,7 @@

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