cns3xxx: drop 3.14 support
Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 44817v19.07.3_mercusys_ac12_duma
John Crispin
9 years ago
parent
43c66cb434
commit
518d9fd2a0
@ -1,263 +0,0 @@
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CONFIG_ALIGNMENT_TRAP=y
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CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
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CONFIG_ARCH_CNS3XXX=y
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CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
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CONFIG_ARCH_HAS_TICK_BROADCAST=y
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CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
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CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
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CONFIG_ARCH_MULTIPLATFORM=y
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# CONFIG_ARCH_MULTI_CPU_AUTO is not set
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CONFIG_ARCH_MULTI_V6=y
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CONFIG_ARCH_MULTI_V6_V7=y
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CONFIG_ARCH_NR_GPIO=0
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# CONFIG_ARCH_OMAP2 is not set
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CONFIG_ARCH_REQUIRE_GPIOLIB=y
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# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
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# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
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CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
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CONFIG_ARCH_SUSPEND_POSSIBLE=y
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CONFIG_ARCH_USE_BUILTIN_BSWAP=y
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CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
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CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
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CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
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# CONFIG_ARCH_WM8750 is not set
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CONFIG_ARM=y
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# CONFIG_ARM_CPU_SUSPEND is not set
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CONFIG_ARM_GIC=y
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CONFIG_ARM_L1_CACHE_SHIFT=5
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CONFIG_ARM_NR_BANKS=8
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CONFIG_ARM_PATCH_PHYS_VIRT=y
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CONFIG_ARM_THUMB=y
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CONFIG_ATA=y
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CONFIG_ATAGS=y
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# CONFIG_ATA_SFF is not set
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CONFIG_ATA_VERBOSE_ERROR=y
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CONFIG_AUTO_ZRELADDR=y
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CONFIG_BLK_DEV_SD=y
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CONFIG_BROADCOM_PHY=y
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CONFIG_CACHE_L2X0=y
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CONFIG_CLKDEV_LOOKUP=y
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CONFIG_CLONE_BACKWARDS=y
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CONFIG_CNS3XXX_ETH=y
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CONFIG_COMMON_CLK=y
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CONFIG_CPU_32v6=y
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CONFIG_CPU_32v6K=y
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CONFIG_CPU_ABRT_EV6=y
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# CONFIG_CPU_BPREDICT_DISABLE is not set
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CONFIG_CPU_CACHE_V6=y
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CONFIG_CPU_CACHE_VIPT=y
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CONFIG_CPU_COPY_V6=y
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CONFIG_CPU_CP15=y
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CONFIG_CPU_CP15_MMU=y
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CONFIG_CPU_HAS_ASID=y
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# CONFIG_CPU_ICACHE_DISABLE is not set
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CONFIG_CPU_PABRT_V6=y
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CONFIG_CPU_RMAP=y
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CONFIG_CPU_TLB_V6=y
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CONFIG_CPU_V6=y
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CONFIG_CPU_V6K=y
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CONFIG_DCACHE_WORD_ACCESS=y
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CONFIG_DEBUG_BUGVERBOSE=y
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CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
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# CONFIG_DEBUG_UART_8250 is not set
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# CONFIG_DEBUG_UART_PL01X is not set
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# CONFIG_DEBUG_USER is not set
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CONFIG_DMA_CACHE_FIQ_BROADCAST=y
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CONFIG_DTC=y
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CONFIG_EEPROM_AT24=y
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CONFIG_FIQ=y
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CONFIG_FRAME_POINTER=y
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CONFIG_GENERIC_ATOMIC64=y
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CONFIG_GENERIC_BUG=y
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
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CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
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CONFIG_GENERIC_IDLE_POLL_SETUP=y
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CONFIG_GENERIC_IO=y
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CONFIG_GENERIC_IRQ_CHIP=y
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CONFIG_GENERIC_IRQ_SHOW=y
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CONFIG_GENERIC_PCI_IOMAP=y
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CONFIG_GENERIC_SCHED_CLOCK=y
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CONFIG_GENERIC_SMP_IDLE_THREAD=y
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CONFIG_GENERIC_STRNCPY_FROM_USER=y
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CONFIG_GENERIC_STRNLEN_USER=y
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CONFIG_GPIOLIB=y
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CONFIG_GPIO_DEVRES=y
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CONFIG_GPIO_PCA953X=y
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CONFIG_GPIO_PCA953X_IRQ=y
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CONFIG_GPIO_SYSFS=y
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CONFIG_HARDIRQS_SW_RESEND=y
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CONFIG_HAS_DMA=y
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CONFIG_HAS_IOMEM=y
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CONFIG_HAS_IOPORT=y
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# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
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CONFIG_HAVE_ARCH_JUMP_LABEL=y
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CONFIG_HAVE_ARCH_KGDB=y
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CONFIG_HAVE_ARCH_PFN_VALID=y
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CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
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CONFIG_HAVE_ARCH_TRACEHOOK=y
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CONFIG_HAVE_ARM_SCU=y
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# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
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CONFIG_HAVE_BPF_JIT=y
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CONFIG_HAVE_CC_STACKPROTECTOR=y
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CONFIG_HAVE_CLK=y
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CONFIG_HAVE_CLK_PREPARE=y
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CONFIG_HAVE_CONTEXT_TRACKING=y
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CONFIG_HAVE_C_RECORDMCOUNT=y
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CONFIG_HAVE_DEBUG_KMEMLEAK=y
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CONFIG_HAVE_DMA_API_DEBUG=y
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CONFIG_HAVE_DMA_ATTRS=y
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CONFIG_HAVE_DMA_CONTIGUOUS=y
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CONFIG_HAVE_DYNAMIC_FTRACE=y
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CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
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CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
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CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
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CONFIG_HAVE_FUNCTION_TRACER=y
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CONFIG_HAVE_GENERIC_DMA_COHERENT=y
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CONFIG_HAVE_IDE=y
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CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
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CONFIG_HAVE_KERNEL_GZIP=y
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CONFIG_HAVE_KERNEL_LZ4=y
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CONFIG_HAVE_KERNEL_LZMA=y
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CONFIG_HAVE_KERNEL_LZO=y
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CONFIG_HAVE_KERNEL_XZ=y
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CONFIG_HAVE_MEMBLOCK=y
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CONFIG_HAVE_NET_DSA=y
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CONFIG_HAVE_OPROFILE=y
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CONFIG_HAVE_PERF_EVENTS=y
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CONFIG_HAVE_PERF_REGS=y
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CONFIG_HAVE_PERF_USER_STACK_DUMP=y
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CONFIG_HAVE_PROC_CPU=y
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CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
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CONFIG_HAVE_SMP=y
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CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
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CONFIG_HAVE_UID16=y
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CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
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CONFIG_HWMON=y
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CONFIG_HZ_FIXED=0
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CONFIG_HZ_PERIODIC=y
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CONFIG_I2C=y
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CONFIG_I2C_BOARDINFO=y
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CONFIG_I2C_CHARDEV=y
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CONFIG_I2C_CNS3XXX=y
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CONFIG_INITRAMFS_SOURCE=""
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CONFIG_IOMMU_HELPER=y
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CONFIG_IRQCHIP=y
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CONFIG_IRQ_DOMAIN=y
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CONFIG_IRQ_FORCED_THREADING=y
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CONFIG_IRQ_WORK=y
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CONFIG_KTIME_SCALAR=y
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CONFIG_LEDS_GPIO=y
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# CONFIG_LEDS_TRIGGER_NETDEV is not set
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# CONFIG_MACH_CNS3420VB is not set
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CONFIG_MACH_GW2388=y
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CONFIG_MDIO_BOARDINFO=y
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CONFIG_MIGHT_HAVE_CACHE_L2X0=y
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CONFIG_MIGHT_HAVE_PCI=y
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CONFIG_MMC=y
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CONFIG_MMC_BLOCK=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_CNS3XXX=y
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# CONFIG_MMC_SDHCI_PCI is not set
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CONFIG_MMC_SDHCI_PLTFM=y
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# CONFIG_MMC_TIFM_SD is not set
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CONFIG_MODULES_USE_ELF_REL=y
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CONFIG_MTD_M25P80=y
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# CONFIG_MTD_OF_PARTS is not set
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CONFIG_MTD_PHYSMAP=y
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# CONFIG_MTD_PHYSMAP_OF is not set
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CONFIG_MULTI_IRQ_HANDLER=y
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CONFIG_MUTEX_SPIN_ON_OWNER=y
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CONFIG_NEED_DMA_MAP_STATE=y
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CONFIG_NET_FLOW_LIMIT=y
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CONFIG_NET_VENDOR_CAVIUM=y
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CONFIG_NLS=y
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CONFIG_NO_BOOTMEM=y
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CONFIG_NR_CPUS=2
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CONFIG_NTP_PPS=y
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CONFIG_OF=y
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CONFIG_OF_ADDRESS=y
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CONFIG_OF_EARLY_FLATTREE=y
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CONFIG_OF_FLATTREE=y
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CONFIG_OF_GPIO=y
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CONFIG_OF_IRQ=y
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CONFIG_OF_MDIO=y
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CONFIG_OF_MTD=y
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CONFIG_OF_NET=y
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CONFIG_OF_PCI=y
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CONFIG_OF_PCI_IRQ=y
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CONFIG_OLD_SIGACTION=y
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CONFIG_OLD_SIGSUSPEND3=y
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CONFIG_OUTER_CACHE=y
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CONFIG_OUTER_CACHE_SYNC=y
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CONFIG_PAGEFLAGS_EXTENDED=y
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CONFIG_PAGE_OFFSET=0xC0000000
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CONFIG_PCI=y
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CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
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CONFIG_PCI_DOMAINS=y
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CONFIG_PERF_USE_VMALLOC=y
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CONFIG_PHYLIB=y
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CONFIG_PL310_ERRATA_588369=y
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CONFIG_PL310_ERRATA_727915=y
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CONFIG_PL310_ERRATA_769419=y
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CONFIG_PPS=y
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CONFIG_PPS_CLIENT_GPIO=y
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# CONFIG_PREEMPT_RCU is not set
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# CONFIG_PROC_STRIPPED is not set
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CONFIG_RAID_ATTRS=y
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CONFIG_RCU_STALL_COMMON=y
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CONFIG_RFS_ACCEL=y
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CONFIG_RPS=y
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CONFIG_RTC_CLASS=y
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CONFIG_RTC_DRV_DS1672=y
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CONFIG_SATA_AHCI=y
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CONFIG_SATA_AHCI_PLATFORM=y
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CONFIG_SCHED_HRTICK=y
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CONFIG_SCSI=y
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# CONFIG_SCSI_MULTI_LUN is not set
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CONFIG_SENSORS_AD7418=y
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CONFIG_SENSORS_GSC=y
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CONFIG_SERIAL_8250_NR_UARTS=3
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CONFIG_SERIAL_8250_RUNTIME_UARTS=3
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CONFIG_SMP=y
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CONFIG_SMP_ON_UP=y
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CONFIG_SPARSE_IRQ=y
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CONFIG_SPI=y
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CONFIG_SPI_BITBANG=y
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CONFIG_SPI_CNS3XXX=y
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CONFIG_SPI_MASTER=y
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# CONFIG_STAGING is not set
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CONFIG_STOP_MACHINE=y
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CONFIG_SWIOTLB=y
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CONFIG_SYS_SUPPORTS_APM_EMULATION=y
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CONFIG_TICK_CPU_ACCOUNTING=y
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CONFIG_TREE_RCU=y
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CONFIG_UID16=y
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CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
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CONFIG_USB=y
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CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
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CONFIG_USB_CNS3XXX_EHCI=y
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CONFIG_USB_CNS3XXX_OHCI=y
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CONFIG_USB_COMMON=y
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CONFIG_USB_DWC2=y
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# CONFIG_USB_DWC2_DEBUG is not set
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# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_HCD_PLATFORM=y
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CONFIG_USB_EHCI_PCI=y
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# CONFIG_USB_ETH is not set
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CONFIG_USB_GADGET=y
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CONFIG_USB_OHCI_HCD=y
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CONFIG_USB_OHCI_HCD_PLATFORM=y
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CONFIG_USB_SUPPORT=y
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# CONFIG_USB_UHCI_HCD is not set
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CONFIG_USE_OF=y
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CONFIG_VECTORS_BASE=0xffff0000
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CONFIG_VFP=y
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CONFIG_WATCHDOG_NOWAYOUT=y
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CONFIG_XPS=y
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CONFIG_XZ_DEC_ARM=y
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CONFIG_XZ_DEC_BCJ=y
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CONFIG_ZBOOT_ROM_BSS=0
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CONFIG_ZBOOT_ROM_TEXT=0
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CONFIG_ZONE_DMA_FLAG=0
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@ -1,8 +0,0 @@
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--- a/arch/arm/mach-cns3xxx/Makefile
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+++ b/arch/arm/mach-cns3xxx/Makefile
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@@ -1,3 +1,5 @@
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+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
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+
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obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o
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cns3xxx-y += core.o pm.o
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cns3xxx-$(CONFIG_ATAGS) += devices.o
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@ -1,11 +0,0 @@
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--- a/arch/arm/mach-cns3xxx/core.c
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+++ b/arch/arm/mach-cns3xxx/core.c
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@@ -307,7 +307,7 @@ static struct usb_ohci_pdata cns3xxx_usb
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.power_off = csn3xxx_usb_power_off,
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};
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-static struct of_dev_auxdata cns3xxx_auxdata[] __initconst = {
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+static const struct of_dev_auxdata cns3xxx_auxdata[] __initconst = {
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{ "intel,usb-ehci", CNS3XXX_USB_BASE, "ehci-platform", &cns3xxx_usb_ehci_pdata },
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{ "intel,usb-ohci", CNS3XXX_USB_OHCI_BASE, "ohci-platform", &cns3xxx_usb_ohci_pdata },
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{ "cavium,cns3420-ahci", CNS3XXX_SATA2_BASE, "ahci", NULL },
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@ -1,64 +0,0 @@
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--- a/arch/arm/include/asm/glue-cache.h
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+++ b/arch/arm/include/asm/glue-cache.h
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@@ -156,11 +156,19 @@ extern inline void nop_dma_unmap_area(co
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#define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range)
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#define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range)
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#define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range)
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+#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST
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#define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area)
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#define dmac_map_area __glue(_CACHE,_dma_map_area)
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#define dmac_unmap_area __glue(_CACHE,_dma_unmap_area)
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#define dmac_flush_range __glue(_CACHE,_dma_flush_range)
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+#else
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+#define __cpuc_flush_dcache_area __glue(fiq,_flush_kern_dcache_area)
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+
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+#define dmac_map_area __glue(fiq,_dma_map_area)
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+#define dmac_unmap_area __glue(fiq,_dma_unmap_area)
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+#define dmac_flush_range __glue(fiq,_dma_flush_range)
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+#endif /* CONFIG_DMA_CACHE_FIQ_BROADCAST */
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#endif
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#endif
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--- a/arch/arm/mm/Kconfig
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+++ b/arch/arm/mm/Kconfig
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@@ -844,6 +844,17 @@ config DMA_CACHE_RWFO
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in hardware, other workarounds are needed (e.g. cache
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maintenance broadcasting in software via FIQ).
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+config DMA_CACHE_FIQ_BROADCAST
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+ bool "Enable fiq broadcast DMA cache maintenance"
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+ depends on CPU_V6K && SMP
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+ select FIQ
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+ help
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+ The Snoop Control Unit on ARM11MPCore does not detect the
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+ cache maintenance operations and the dma_{map,unmap}_area()
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+ functions may leave stale cache entries on other CPUs. By
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+ enabling this option, fiq broadcast in the ARMv6
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+ DMA cache maintenance functions is performed.
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+
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config OUTER_CACHE
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bool
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--- a/arch/arm/mm/flush.c
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+++ b/arch/arm/mm/flush.c
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@@ -281,6 +281,7 @@ void __sync_icache_dcache(pte_t pteval)
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void flush_dcache_page(struct page *page)
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{
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struct address_space *mapping;
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+ bool skip_broadcast = true;
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/*
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* The zero page is never written to, so never has any dirty
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@@ -291,7 +292,10 @@ void flush_dcache_page(struct page *page
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mapping = page_mapping(page);
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- if (!cache_ops_need_broadcast() &&
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+#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST
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+ skip_broadcast = !cache_ops_need_broadcast();
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+#endif
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+ if (skip_broadcast &&
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mapping && !page_mapped(page))
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clear_bit(PG_dcache_clean, &page->flags);
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else {
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@ -1,59 +0,0 @@
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1. Made the connection between CNS3xxx SOCs(ARCH_CNS3xxx) and MPcore watchdog
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since the CNS3xxx SOCs have ARM11 MPcore CPU.
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2. Enable mpcore_watchdog option as module to default configuration at
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arch/arm/configs/cns3420vb_defconfig.
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Signed-off-by: Tommy Lin <tommy.lin@caviumnetworks.com>
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---
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arch/arm/Kconfig | 1 +
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arch/arm/configs/cns3420vb_defconfig | 2 ++
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arch/arm/mach-cns3xxx/cns3420vb.c | 22 ++++++++++++++++++++++
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3 files changed, 25 insertions(+), 0 deletions(-)
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--- a/arch/arm/configs/cns3420vb_defconfig
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+++ b/arch/arm/configs/cns3420vb_defconfig
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@@ -56,6 +56,8 @@ CONFIG_LEGACY_PTY_COUNT=16
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# CONFIG_HW_RANDOM is not set
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# CONFIG_HWMON is not set
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# CONFIG_VGA_CONSOLE is not set
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+CONFIG_WATCHDOG=y
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+CONFIG_MPCORE_WATCHDOG=m
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# CONFIG_HID_SUPPORT is not set
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# CONFIG_USB_SUPPORT is not set
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CONFIG_MMC=y
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--- a/arch/arm/mach-cns3xxx/cns3420vb.c
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+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
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@@ -206,10 +206,32 @@ static struct platform_device cns3xxx_us
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},
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};
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+/* Watchdog */
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+static struct resource cns3xxx_watchdog_resources[] = {
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+ [0] = {
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+ .start = CNS3XXX_TC11MP_TWD_BASE,
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+ .end = CNS3XXX_TC11MP_TWD_BASE + PAGE_SIZE - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ [1] = {
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+ .start = IRQ_LOCALWDOG,
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+ .end = IRQ_LOCALWDOG,
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+ .flags = IORESOURCE_IRQ,
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+ }
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+};
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+
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+static struct platform_device cns3xxx_watchdog_device = {
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+ .name = "mpcore_wdt",
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+ .id = -1,
|
||||
+ .num_resources = ARRAY_SIZE(cns3xxx_watchdog_resources),
|
||||
+ .resource = cns3xxx_watchdog_resources,
|
||||
+};
|
||||
+
|
||||
/*
|
||||
* Initialization
|
||||
*/
|
||||
static struct platform_device *cns3420_pdevs[] __initdata = {
|
||||
+ &cns3xxx_watchdog_device,
|
||||
&cns3420_nor_pdev,
|
||||
&cns3xxx_usb_ehci_device,
|
||||
&cns3xxx_usb_ohci_device,
|
||||
@ -1,30 +0,0 @@
|
||||
--- a/arch/arm/mach-cns3xxx/Makefile
|
||||
+++ b/arch/arm/mach-cns3xxx/Makefile
|
||||
@@ -5,3 +5,5 @@ cns3xxx-y += core.o pm.o
|
||||
cns3xxx-$(CONFIG_ATAGS) += devices.o
|
||||
cns3xxx-$(CONFIG_PCI) += pcie.o
|
||||
cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
|
||||
+cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o
|
||||
+cns3xxx-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
--- a/arch/arm/mach-cns3xxx/Kconfig
|
||||
+++ b/arch/arm/mach-cns3xxx/Kconfig
|
||||
@@ -6,6 +6,9 @@ config ARCH_CNS3XXX
|
||||
select MIGHT_HAVE_CACHE_L2X0
|
||||
select MIGHT_HAVE_PCI
|
||||
select PCI_DOMAINS if PCI
|
||||
+ select HAVE_ARM_SCU if SMP
|
||||
+ select HAVE_ARM_TWD if LOCAL_TIMERS
|
||||
+ select HAVE_SMP
|
||||
help
|
||||
Support for Cavium Networks CNS3XXX platform.
|
||||
|
||||
--- a/arch/arm/mach-cns3xxx/core.h
|
||||
+++ b/arch/arm/mach-cns3xxx/core.h
|
||||
@@ -13,6 +13,7 @@
|
||||
|
||||
#include <linux/reboot.h>
|
||||
|
||||
+extern struct smp_operations cns3xxx_smp_ops;
|
||||
extern void cns3xxx_timer_init(void);
|
||||
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
@ -1,11 +0,0 @@
|
||||
--- a/arch/arm/mach-cns3xxx/pcie.c
|
||||
+++ b/arch/arm/mach-cns3xxx/pcie.c
|
||||
@@ -370,8 +370,6 @@ static int __init cns3xxx_pcie_init(void
|
||||
for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
|
||||
iotable_init(cns3xxx_pcie[i].cfg_bases,
|
||||
ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
|
||||
- cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
|
||||
- cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
|
||||
cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
|
||||
cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
|
||||
pci_common_init(&cns3xxx_pcie[i].hw_pci);
|
||||
@ -1,40 +0,0 @@
|
||||
--- a/arch/arm/mach-cns3xxx/Kconfig
|
||||
+++ b/arch/arm/mach-cns3xxx/Kconfig
|
||||
@@ -9,6 +9,7 @@ config ARCH_CNS3XXX
|
||||
select HAVE_ARM_SCU if SMP
|
||||
select HAVE_ARM_TWD if LOCAL_TIMERS
|
||||
select HAVE_SMP
|
||||
+ select FIQ
|
||||
help
|
||||
Support for Cavium Networks CNS3XXX platform.
|
||||
|
||||
--- a/arch/arm/mach-cns3xxx/Makefile
|
||||
+++ b/arch/arm/mach-cns3xxx/Makefile
|
||||
@@ -5,5 +5,5 @@ cns3xxx-y += core.o pm.o
|
||||
cns3xxx-$(CONFIG_ATAGS) += devices.o
|
||||
cns3xxx-$(CONFIG_PCI) += pcie.o
|
||||
cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
|
||||
-cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o
|
||||
+cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o cns3xxx_fiq.o
|
||||
cns3xxx-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
--- a/arch/arm/mach-cns3xxx/cns3xxx.h
|
||||
+++ b/arch/arm/mach-cns3xxx/cns3xxx.h
|
||||
@@ -267,6 +267,7 @@
|
||||
#define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100)
|
||||
#define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100)
|
||||
|
||||
+#define MISC_FIQ_CPU(x) MISC_MEM_MAP(0xA58 - (x) * 0x4)
|
||||
/*
|
||||
* Power management and clock control
|
||||
*/
|
||||
--- a/arch/arm/mm/Kconfig
|
||||
+++ b/arch/arm/mm/Kconfig
|
||||
@@ -827,7 +827,7 @@ config KUSER_HELPERS
|
||||
|
||||
config DMA_CACHE_RWFO
|
||||
bool "Enable read/write for ownership DMA cache maintenance"
|
||||
- depends on CPU_V6K && SMP
|
||||
+ depends on CPU_V6K && SMP && !ARCH_CNS3XXX
|
||||
default y
|
||||
help
|
||||
The Snoop Control Unit on ARM11MPCore does not detect the
|
||||
@ -1,45 +0,0 @@
|
||||
--- a/arch/arm/mach-cns3xxx/core.c
|
||||
+++ b/arch/arm/mach-cns3xxx/core.c
|
||||
@@ -17,6 +17,7 @@
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/usb/ehci_pdriver.h>
|
||||
#include <linux/usb/ohci_pdriver.h>
|
||||
+#include <asm/smp_twd.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/time.h>
|
||||
@@ -26,6 +27,8 @@
|
||||
#include "core.h"
|
||||
#include "pm.h"
|
||||
|
||||
+#define IRQ_LOCALTIMER 29
|
||||
+
|
||||
static struct map_desc cns3xxx_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = CNS3XXX_TC11MP_SCU_BASE_VIRT,
|
||||
@@ -159,6 +162,17 @@ static struct irqaction cns3xxx_timer_ir
|
||||
.handler = cns3xxx_timer_interrupt,
|
||||
};
|
||||
|
||||
+static void __init cns3xxx_init_twd(void)
|
||||
+{
|
||||
+#ifdef CONFIG_LOCAL_TIMERS
|
||||
+ static DEFINE_TWD_LOCAL_TIMER(cns3xx_twd_local_timer,
|
||||
+ CNS3XXX_TC11MP_TWD_BASE,
|
||||
+ IRQ_LOCALTIMER);
|
||||
+
|
||||
+ twd_local_timer_register(&cns3xx_twd_local_timer);
|
||||
+#endif
|
||||
+}
|
||||
+
|
||||
/*
|
||||
* Set up the clock source and clock events devices
|
||||
*/
|
||||
@@ -212,6 +226,7 @@ static void __init __cns3xxx_timer_init(
|
||||
setup_irq(timer_irq, &cns3xxx_timer_irq);
|
||||
|
||||
cns3xxx_clockevents_init(timer_irq);
|
||||
+ cns3xxx_init_twd();
|
||||
}
|
||||
|
||||
void __init cns3xxx_timer_init(void)
|
||||
@ -1,19 +0,0 @@
|
||||
--- a/arch/arm/mach-cns3xxx/core.c
|
||||
+++ b/arch/arm/mach-cns3xxx/core.c
|
||||
@@ -50,6 +50,16 @@ static struct map_desc cns3xxx_io_desc[]
|
||||
.pfn = __phys_to_pfn(CNS3XXX_PM_BASE),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
+ }, {
|
||||
+ .virtual = CNS3XXX_PCIE0_IO_BASE_VIRT,
|
||||
+ .pfn = __phys_to_pfn(CNS3XXX_PCIE0_IO_BASE),
|
||||
+ .length = SZ_16M,
|
||||
+ .type = MT_DEVICE,
|
||||
+ }, {
|
||||
+ .virtual = CNS3XXX_PCIE1_IO_BASE_VIRT,
|
||||
+ .pfn = __phys_to_pfn(CNS3XXX_PCIE1_IO_BASE),
|
||||
+ .length = SZ_16M,
|
||||
+ .type = MT_DEVICE,
|
||||
},
|
||||
};
|
||||
|
||||
@ -1,129 +0,0 @@
|
||||
--- a/arch/arm/mach-cns3xxx/pcie.c
|
||||
+++ b/arch/arm/mach-cns3xxx/pcie.c
|
||||
@@ -92,6 +92,79 @@ static void __iomem *cns3xxx_pci_cfg_bas
|
||||
return base + offset;
|
||||
}
|
||||
|
||||
+static inline int check_master_abort(struct pci_bus *bus, unsigned int devfn, int where)
|
||||
+{
|
||||
+ struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
|
||||
+
|
||||
+ /* check PCI-compatible status register after access */
|
||||
+ if (cnspci->linked) {
|
||||
+ void __iomem *host_base;
|
||||
+ u32 sreg, ereg;
|
||||
+
|
||||
+ host_base = (void __iomem *) cnspci->cfg_bases[CNS3XXX_HOST_TYPE].virtual;
|
||||
+ sreg = __raw_readw(host_base + 0x6) & 0xF900;
|
||||
+ ereg = __raw_readl(host_base + 0x104); // Uncorrectable Error Status Reg
|
||||
+
|
||||
+ if (sreg | ereg) {
|
||||
+ /* SREG:
|
||||
+ * BIT15 - Detected Parity Error
|
||||
+ * BIT14 - Signaled System Error
|
||||
+ * BIT13 - Received Master Abort
|
||||
+ * BIT12 - Received Target Abort
|
||||
+ * BIT11 - Signaled Target Abort
|
||||
+ * BIT08 - Master Data Parity Error
|
||||
+ *
|
||||
+ * EREG:
|
||||
+ * BIT20 - Unsupported Request
|
||||
+ * BIT19 - ECRC
|
||||
+ * BIT18 - Malformed TLP
|
||||
+ * BIT17 - Receiver Overflow
|
||||
+ * BIT16 - Unexpected Completion
|
||||
+ * BIT15 - Completer Abort
|
||||
+ * BIT14 - Completion Timeout
|
||||
+ * BIT13 - Flow Control Protocol Error
|
||||
+ * BIT12 - Poisoned TLP
|
||||
+ * BIT04 - Data Link Protocol Error
|
||||
+ *
|
||||
+ * TODO: see Documentation/pci-error-recovery.txt
|
||||
+ * implement error_detected handler
|
||||
+ */
|
||||
+/*
|
||||
+ printk("pci error: %04d:%02x:%02x.%02x sreg=0x%04x ereg=0x%08x", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), sreg, ereg);
|
||||
+ if (sreg & BIT(15)) printk(" <PERR");
|
||||
+ if (sreg & BIT(14)) printk(" >SERR");
|
||||
+ if (sreg & BIT(13)) printk(" <MABRT");
|
||||
+ if (sreg & BIT(12)) printk(" <TABRT");
|
||||
+ if (sreg & BIT(11)) printk(" >TABRT");
|
||||
+ if (sreg & BIT( 8)) printk(" MPERR");
|
||||
+
|
||||
+ if (ereg & BIT(20)) printk(" Unsup");
|
||||
+ if (ereg & BIT(19)) printk(" ECRC");
|
||||
+ if (ereg & BIT(18)) printk(" MTLP");
|
||||
+ if (ereg & BIT(17)) printk(" OFLOW");
|
||||
+ if (ereg & BIT(16)) printk(" Unex");
|
||||
+ if (ereg & BIT(15)) printk(" ABRT");
|
||||
+ if (ereg & BIT(14)) printk(" COMPTO");
|
||||
+ if (ereg & BIT(13)) printk(" FLOW");
|
||||
+ if (ereg & BIT(12)) printk(" PTLP");
|
||||
+ if (ereg & BIT( 4)) printk(" DLINK");
|
||||
+ printk("\n");
|
||||
+*/
|
||||
+ pr_debug("%s failed port%d sreg=0x%04x\n", __func__,
|
||||
+ cnspci->hw_pci.domain, sreg);
|
||||
+
|
||||
+ /* make sure the status bits are reset */
|
||||
+ __raw_writew(sreg, host_base + 6);
|
||||
+ __raw_writel(ereg, host_base + 0x104);
|
||||
+ return 1;
|
||||
+ }
|
||||
+ }
|
||||
+ else
|
||||
+ return 1;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
|
||||
int where, int size, u32 *val)
|
||||
{
|
||||
@@ -108,6 +181,11 @@ static int cns3xxx_pci_read_config(struc
|
||||
|
||||
v = __raw_readl(base);
|
||||
|
||||
+ if (check_master_abort(bus, devfn, where)) {
|
||||
+ printk(KERN_ERR "pci error: %04d:%02x:%02x.%02x %02x(%d)= master_abort on read\n", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);
|
||||
+ return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
+ }
|
||||
+
|
||||
if (bus->number == 0 && devfn == 0 &&
|
||||
(where & 0xffc) == PCI_CLASS_REVISION) {
|
||||
/*
|
||||
@@ -137,11 +215,19 @@ static int cns3xxx_pci_write_config(stru
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
|
||||
v = __raw_readl(base);
|
||||
+ if (check_master_abort(bus, devfn, where)) {
|
||||
+ printk(KERN_ERR "pci error: %04d:%02x:%02x.%02x %02x(%d)=0x%08x master_abort on read\n", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val);
|
||||
+ return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
+ }
|
||||
|
||||
v &= ~(mask << shift);
|
||||
v |= (val & mask) << shift;
|
||||
|
||||
__raw_writel(v, base);
|
||||
+ if (check_master_abort(bus, devfn, where)) {
|
||||
+ printk(KERN_ERR "pci error: %04d:%02x:%02x.%02x %02x(%d)=0x%08x master_abort on write\n", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val);
|
||||
+ return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
+ }
|
||||
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
@@ -352,8 +438,14 @@ static void __init cns3xxx_pcie_hw_init(
|
||||
static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
|
||||
struct pt_regs *regs)
|
||||
{
|
||||
+#if 0
|
||||
+/* R14_ABORT = PC+4 for XSCALE but not ARM11MPCORE
|
||||
+ * ignore imprecise aborts and use PCI-compatible Status register to
|
||||
+ * determine errors instead
|
||||
+ */
|
||||
if (fsr & (1 << 10))
|
||||
regs->ARM_pc += 4;
|
||||
+#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -1,84 +0,0 @@
|
||||
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
|
||||
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
|
||||
@@ -261,11 +261,21 @@ static struct map_desc cns3420_io_desc[]
|
||||
static void __init cns3420_map_io(void)
|
||||
{
|
||||
cns3xxx_map_io();
|
||||
+ cns3xxx_pcie_iotable_init();
|
||||
iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc));
|
||||
|
||||
cns3420_early_serial_setup();
|
||||
}
|
||||
|
||||
+static int __init cns3420vb_pcie_init(void)
|
||||
+{
|
||||
+ if (!machine_is_cns3420vb())
|
||||
+ return 0;
|
||||
+
|
||||
+ return cns3xxx_pcie_init();
|
||||
+}
|
||||
+subsys_initcall(cns3420vb_pcie_init);
|
||||
+
|
||||
MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
|
||||
.atag_offset = 0x100,
|
||||
.nr_irqs = NR_IRQS_CNS3XXX,
|
||||
--- a/arch/arm/mach-cns3xxx/core.h
|
||||
+++ b/arch/arm/mach-cns3xxx/core.h
|
||||
@@ -15,6 +15,7 @@
|
||||
|
||||
extern struct smp_operations cns3xxx_smp_ops;
|
||||
extern void cns3xxx_timer_init(void);
|
||||
+extern void cns3xxx_pcie_iotable_init(void);
|
||||
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
void __init cns3xxx_l2x0_init(void);
|
||||
@@ -24,6 +25,7 @@ static inline void cns3xxx_l2x0_init(voi
|
||||
|
||||
void __init cns3xxx_map_io(void);
|
||||
void __init cns3xxx_init_irq(void);
|
||||
+int __init cns3xxx_pcie_init(void);
|
||||
void cns3xxx_power_off(void);
|
||||
void cns3xxx_restart(enum reboot_mode, const char *);
|
||||
|
||||
--- a/arch/arm/mach-cns3xxx/pcie.c
|
||||
+++ b/arch/arm/mach-cns3xxx/pcie.c
|
||||
@@ -449,7 +449,18 @@ static int cns3xxx_pcie_abort_handler(un
|
||||
return 0;
|
||||
}
|
||||
|
||||
-static int __init cns3xxx_pcie_init(void)
|
||||
+
|
||||
+void __init cns3xxx_pcie_iotable_init()
|
||||
+{
|
||||
+ int i;
|
||||
+
|
||||
+ for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
|
||||
+ iotable_init(cns3xxx_pcie[i].cfg_bases,
|
||||
+ ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+int __init cns3xxx_pcie_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
@@ -460,15 +471,14 @@ static int __init cns3xxx_pcie_init(void
|
||||
"imprecise external abort");
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
|
||||
- iotable_init(cns3xxx_pcie[i].cfg_bases,
|
||||
- ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
|
||||
cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
|
||||
- cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
|
||||
- pci_common_init(&cns3xxx_pcie[i].hw_pci);
|
||||
+ if (cns3xxx_pcie[i].linked) {
|
||||
+ cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
|
||||
+ pci_common_init(&cns3xxx_pcie[i].hw_pci);
|
||||
+ }
|
||||
}
|
||||
|
||||
pci_assign_unassigned_resources();
|
||||
|
||||
return 0;
|
||||
}
|
||||
-device_initcall(cns3xxx_pcie_init);
|
||||
@ -1,31 +0,0 @@
|
||||
--- a/drivers/i2c/busses/Kconfig
|
||||
+++ b/drivers/i2c/busses/Kconfig
|
||||
@@ -386,6 +386,18 @@ config I2C_CBUS_GPIO
|
||||
This driver can also be built as a module. If so, the module
|
||||
will be called i2c-cbus-gpio.
|
||||
|
||||
+config I2C_CNS3XXX
|
||||
+ tristate "Cavium CNS3xxx I2C driver"
|
||||
+ depends on ARCH_CNS3XXX
|
||||
+ help
|
||||
+ Support for Cavium CNS3xxx I2C controller driver.
|
||||
+
|
||||
+ This driver can also be built as a module. If so, the module
|
||||
+ will be called i2c-cns3xxx.
|
||||
+
|
||||
+ Please note that this driver might be needed to bring up other
|
||||
+ devices such as Cavium CNS3xxx Ethernet.
|
||||
+
|
||||
config I2C_CPM
|
||||
tristate "Freescale CPM1 or CPM2 (MPC8xx/826x)"
|
||||
depends on CPM1 || CPM2
|
||||
--- a/drivers/i2c/busses/Makefile
|
||||
+++ b/drivers/i2c/busses/Makefile
|
||||
@@ -95,6 +95,7 @@ obj-$(CONFIG_I2C_BCM_KONA) += i2c-bcm-ko
|
||||
obj-$(CONFIG_I2C_ELEKTOR) += i2c-elektor.o
|
||||
obj-$(CONFIG_I2C_PCA_ISA) += i2c-pca-isa.o
|
||||
obj-$(CONFIG_I2C_SIBYTE) += i2c-sibyte.o
|
||||
+obj-$(CONFIG_I2C_CNS3XXX) += i2c-cns3xxx.o
|
||||
obj-$(CONFIG_SCx200_ACB) += scx200_acb.o
|
||||
obj-$(CONFIG_SCx200_I2C) += scx200_i2c.o
|
||||
|
||||
@ -1,55 +0,0 @@
|
||||
--- a/drivers/spi/Kconfig
|
||||
+++ b/drivers/spi/Kconfig
|
||||
@@ -155,6 +155,13 @@ config SPI_CLPS711X
|
||||
This enables dedicated general purpose SPI/Microwire1-compatible
|
||||
master mode interface (SSI1) for CLPS711X-based CPUs.
|
||||
|
||||
+config SPI_CNS3XXX
|
||||
+ tristate "CNS3XXX SPI controller"
|
||||
+ depends on ARCH_CNS3XXX && SPI_MASTER
|
||||
+ select SPI_BITBANG
|
||||
+ help
|
||||
+ This enables using the CNS3XXX SPI controller in master mode.
|
||||
+
|
||||
config SPI_COLDFIRE_QSPI
|
||||
tristate "Freescale Coldfire QSPI controller"
|
||||
depends on (M520x || M523x || M5249 || M525x || M527x || M528x || M532x)
|
||||
--- a/drivers/spi/Makefile
|
||||
+++ b/drivers/spi/Makefile
|
||||
@@ -22,6 +22,7 @@ obj-$(CONFIG_SPI_BFIN_V3)
|
||||
obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o
|
||||
obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o
|
||||
obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o
|
||||
+obj-$(CONFIG_SPI_CNS3XXX) += spi-cns3xxx.o
|
||||
obj-$(CONFIG_SPI_CLPS711X) += spi-clps711x.o
|
||||
obj-$(CONFIG_SPI_COLDFIRE_QSPI) += spi-coldfire-qspi.o
|
||||
obj-$(CONFIG_SPI_DAVINCI) += spi-davinci.o
|
||||
--- a/drivers/spi/spi-bitbang.c
|
||||
+++ b/drivers/spi/spi-bitbang.c
|
||||
@@ -333,6 +333,10 @@ static int spi_bitbang_transfer_one(stru
|
||||
*/
|
||||
if (!m->is_dma_mapped)
|
||||
t->rx_dma = t->tx_dma = 0;
|
||||
+
|
||||
+ t->last_in_message_list =
|
||||
+ list_is_last(&t->transfer_list, &m->transfers);
|
||||
+
|
||||
status = bitbang->txrx_bufs(spi, t);
|
||||
}
|
||||
if (status > 0)
|
||||
--- a/include/linux/spi/spi.h
|
||||
+++ b/include/linux/spi/spi.h
|
||||
@@ -591,6 +591,13 @@ struct spi_transfer {
|
||||
u32 speed_hz;
|
||||
|
||||
struct list_head transfer_list;
|
||||
+
|
||||
+#ifdef CONFIG_ARCH_CNS3XXX
|
||||
+ unsigned last_in_message_list;
|
||||
+#ifdef CONFIG_SPI_CNS3XXX_2IOREAD
|
||||
+ u8 dio_read;
|
||||
+#endif
|
||||
+#endif
|
||||
};
|
||||
|
||||
/**
|
||||
@ -1,44 +0,0 @@
|
||||
--- a/arch/arm/mach-cns3xxx/devices.c
|
||||
+++ b/arch/arm/mach-cns3xxx/devices.c
|
||||
@@ -40,7 +40,7 @@ static struct resource cns3xxx_ahci_reso
|
||||
static u64 cns3xxx_ahci_dmamask = DMA_BIT_MASK(32);
|
||||
|
||||
static struct platform_device cns3xxx_ahci_pdev = {
|
||||
- .name = "ahci",
|
||||
+ .name = "cns3xxx-ahci",
|
||||
.id = 0,
|
||||
.resource = cns3xxx_ahci_resource,
|
||||
.num_resources = ARRAY_SIZE(cns3xxx_ahci_resource),
|
||||
--- a/drivers/ata/ahci_platform.c
|
||||
+++ b/drivers/ata/ahci_platform.c
|
||||
@@ -31,6 +31,7 @@ enum ahci_type {
|
||||
AHCI, /* standard platform ahci */
|
||||
IMX53_AHCI, /* ahci on i.mx53 */
|
||||
STRICT_AHCI, /* delayed DMA engine start */
|
||||
+ CNS3XXX_AHCI, /* AHCI on cns3xxx */
|
||||
};
|
||||
|
||||
static struct platform_device_id ahci_devtype[] = {
|
||||
@@ -44,6 +45,9 @@ static struct platform_device_id ahci_de
|
||||
.name = "strict-ahci",
|
||||
.driver_data = STRICT_AHCI,
|
||||
}, {
|
||||
+ .name = "cns3xxx-ahci",
|
||||
+ .driver_data = CNS3XXX_AHCI,
|
||||
+ }, {
|
||||
/* sentinel */
|
||||
}
|
||||
};
|
||||
@@ -81,6 +85,12 @@ static const struct ata_port_info ahci_p
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &ahci_platform_ops,
|
||||
},
|
||||
+ [CNS3XXX_AHCI] = {
|
||||
+ .flags = AHCI_FLAG_COMMON,
|
||||
+ .pio_mask = ATA_PIO4,
|
||||
+ .udma_mask = ATA_UDMA6,
|
||||
+ .port_ops = &ahci_platform_retry_srst_ops,
|
||||
+ }
|
||||
};
|
||||
|
||||
static struct scsi_host_template ahci_platform_sht = {
|
||||
@ -1,20 +0,0 @@
|
||||
--- a/drivers/net/ethernet/Kconfig
|
||||
+++ b/drivers/net/ethernet/Kconfig
|
||||
@@ -34,6 +34,7 @@ source "drivers/net/ethernet/calxeda/Kco
|
||||
source "drivers/net/ethernet/chelsio/Kconfig"
|
||||
source "drivers/net/ethernet/cirrus/Kconfig"
|
||||
source "drivers/net/ethernet/cisco/Kconfig"
|
||||
+source "drivers/net/ethernet/cavium/Kconfig"
|
||||
source "drivers/net/ethernet/davicom/Kconfig"
|
||||
|
||||
config DNET
|
||||
--- a/drivers/net/ethernet/Makefile
|
||||
+++ b/drivers/net/ethernet/Makefile
|
||||
@@ -17,6 +17,7 @@ obj-$(CONFIG_NET_BFIN) += adi/
|
||||
obj-$(CONFIG_NET_VENDOR_BROADCOM) += broadcom/
|
||||
obj-$(CONFIG_NET_VENDOR_BROCADE) += brocade/
|
||||
obj-$(CONFIG_NET_CALXEDA_XGMAC) += calxeda/
|
||||
+obj-$(CONFIG_NET_VENDOR_CAVIUM) += cavium/
|
||||
obj-$(CONFIG_NET_VENDOR_CHELSIO) += chelsio/
|
||||
obj-$(CONFIG_NET_VENDOR_CIRRUS) += cirrus/
|
||||
obj-$(CONFIG_NET_VENDOR_CISCO) += cisco/
|
||||
@ -1,104 +0,0 @@
|
||||
--- a/arch/arm/mach-cns3xxx/core.c
|
||||
+++ b/arch/arm/mach-cns3xxx/core.c
|
||||
@@ -103,12 +103,13 @@ static void cns3xxx_timer_set_mode(enum
|
||||
|
||||
switch (mode) {
|
||||
case CLOCK_EVT_MODE_PERIODIC:
|
||||
- reload = pclk * 20 / (3 * HZ) * 0x25000;
|
||||
+ reload = pclk * 1000000 / HZ;
|
||||
writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
|
||||
ctrl |= (1 << 0) | (1 << 2) | (1 << 9);
|
||||
break;
|
||||
case CLOCK_EVT_MODE_ONESHOT:
|
||||
/* period set, and timer enabled in 'next_event' hook */
|
||||
+ writel(0, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
|
||||
ctrl |= (1 << 2) | (1 << 9);
|
||||
break;
|
||||
case CLOCK_EVT_MODE_UNUSED:
|
||||
@@ -136,7 +137,7 @@ static struct clock_event_device cns3xxx
|
||||
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
|
||||
.set_mode = cns3xxx_timer_set_mode,
|
||||
.set_next_event = cns3xxx_timer_set_next_event,
|
||||
- .rating = 350,
|
||||
+ .rating = 300,
|
||||
.cpumask = cpu_all_mask,
|
||||
};
|
||||
|
||||
@@ -183,6 +184,35 @@ static void __init cns3xxx_init_twd(void
|
||||
#endif
|
||||
}
|
||||
|
||||
+static cycle_t cns3xxx_get_cycles(struct clocksource *cs)
|
||||
+{
|
||||
+ u64 val;
|
||||
+
|
||||
+ val = readl(cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
|
||||
+ val &= 0xffff;
|
||||
+
|
||||
+ return ((val << 32) | readl(cns3xxx_tmr1 + TIMER_FREERUN_OFFSET));
|
||||
+}
|
||||
+
|
||||
+static struct clocksource clocksource_cns3xxx = {
|
||||
+ .name = "freerun",
|
||||
+ .rating = 200,
|
||||
+ .read = cns3xxx_get_cycles,
|
||||
+ .mask = CLOCKSOURCE_MASK(48),
|
||||
+ .shift = 16,
|
||||
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
+};
|
||||
+
|
||||
+static void __init cns3xxx_clocksource_init(void)
|
||||
+{
|
||||
+ /* Reset the FreeRunning counter */
|
||||
+ writel((1 << 16), cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
|
||||
+
|
||||
+ clocksource_cns3xxx.mult =
|
||||
+ clocksource_khz2mult(100, clocksource_cns3xxx.shift);
|
||||
+ clocksource_register(&clocksource_cns3xxx);
|
||||
+}
|
||||
+
|
||||
/*
|
||||
* Set up the clock source and clock events devices
|
||||
*/
|
||||
@@ -200,13 +230,12 @@ static void __init __cns3xxx_timer_init(
|
||||
/* stop free running timer3 */
|
||||
writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
|
||||
|
||||
- /* timer1 */
|
||||
- writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);
|
||||
- writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
|
||||
-
|
||||
writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET);
|
||||
writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET);
|
||||
|
||||
+ val = (cns3xxx_cpu_clock() >> 3) * 1000000 / HZ;
|
||||
+ writel(val, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);
|
||||
+
|
||||
/* mask irq, non-mask timer1 overflow */
|
||||
irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
|
||||
irq_mask &= ~(1 << 2);
|
||||
@@ -218,23 +247,9 @@ static void __init __cns3xxx_timer_init(
|
||||
val |= (1 << 9);
|
||||
writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
|
||||
|
||||
- /* timer2 */
|
||||
- writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET);
|
||||
- writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET);
|
||||
-
|
||||
- /* mask irq */
|
||||
- irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
|
||||
- irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5));
|
||||
- writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
|
||||
-
|
||||
- /* down counter */
|
||||
- val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
|
||||
- val |= (1 << 10);
|
||||
- writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
|
||||
-
|
||||
- /* Make irqs happen for the system timer */
|
||||
setup_irq(timer_irq, &cns3xxx_timer_irq);
|
||||
|
||||
+ cns3xxx_clocksource_init();
|
||||
cns3xxx_clockevents_init(timer_irq);
|
||||
cns3xxx_init_twd();
|
||||
}
|
||||
@ -1,82 +0,0 @@
|
||||
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
|
||||
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
|
||||
@@ -245,6 +245,10 @@ static void __init cns3420_init(void)
|
||||
|
||||
cns3xxx_ahci_init();
|
||||
cns3xxx_sdhci_init();
|
||||
+ cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
|
||||
+ NR_IRQS_CNS3XXX);
|
||||
+ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
|
||||
+ NR_IRQS_CNS3XXX + 32);
|
||||
|
||||
pm_power_off = cns3xxx_power_off;
|
||||
}
|
||||
--- a/arch/arm/mach-cns3xxx/core.h
|
||||
+++ b/arch/arm/mach-cns3xxx/core.h
|
||||
@@ -17,12 +17,6 @@ extern struct smp_operations cns3xxx_smp
|
||||
extern void cns3xxx_timer_init(void);
|
||||
extern void cns3xxx_pcie_iotable_init(void);
|
||||
|
||||
-#ifdef CONFIG_CACHE_L2X0
|
||||
-void __init cns3xxx_l2x0_init(void);
|
||||
-#else
|
||||
-static inline void cns3xxx_l2x0_init(void) {}
|
||||
-#endif /* CONFIG_CACHE_L2X0 */
|
||||
-
|
||||
void __init cns3xxx_map_io(void);
|
||||
void __init cns3xxx_init_irq(void);
|
||||
int __init cns3xxx_pcie_init(void);
|
||||
--- a/arch/arm/mach-cns3xxx/Kconfig
|
||||
+++ b/arch/arm/mach-cns3xxx/Kconfig
|
||||
@@ -2,6 +2,8 @@ config ARCH_CNS3XXX
|
||||
bool "Cavium Networks CNS3XXX family" if ARCH_MULTI_V6
|
||||
select ARM_GIC
|
||||
select CPU_V6K
|
||||
+ select ARCH_REQUIRE_GPIOLIB
|
||||
+ select GENERIC_IRQ_CHIP
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select MIGHT_HAVE_CACHE_L2X0
|
||||
select MIGHT_HAVE_PCI
|
||||
--- a/arch/arm/mach-cns3xxx/Makefile
|
||||
+++ b/arch/arm/mach-cns3xxx/Makefile
|
||||
@@ -1,7 +1,7 @@
|
||||
ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
|
||||
|
||||
obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o
|
||||
-cns3xxx-y += core.o pm.o
|
||||
+cns3xxx-y += core.o pm.o gpio.o
|
||||
cns3xxx-$(CONFIG_ATAGS) += devices.o
|
||||
cns3xxx-$(CONFIG_PCI) += pcie.o
|
||||
cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
|
||||
--- a/arch/arm/mach-cns3xxx/cns3xxx.h
|
||||
+++ b/arch/arm/mach-cns3xxx/cns3xxx.h
|
||||
@@ -68,8 +68,10 @@
|
||||
#define SMC_PCELL_ID_3_OFFSET 0xFFC
|
||||
|
||||
#define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */
|
||||
+#define CNS3XXX_GPIOA_BASE_VIRT 0xFB006000
|
||||
|
||||
#define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */
|
||||
+#define CNS3XXX_GPIOB_BASE_VIRT 0xFB007000
|
||||
|
||||
#define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */
|
||||
|
||||
--- a/arch/arm/mach-cns3xxx/core.c
|
||||
+++ b/arch/arm/mach-cns3xxx/core.c
|
||||
@@ -60,6 +60,16 @@ static struct map_desc cns3xxx_io_desc[]
|
||||
.pfn = __phys_to_pfn(CNS3XXX_PCIE1_IO_BASE),
|
||||
.length = SZ_16M,
|
||||
.type = MT_DEVICE,
|
||||
+ }, {
|
||||
+ .virtual = CNS3XXX_GPIOA_BASE_VIRT,
|
||||
+ .pfn = __phys_to_pfn(CNS3XXX_GPIOA_BASE),
|
||||
+ .length = SZ_4K,
|
||||
+ .type = MT_DEVICE,
|
||||
+ }, {
|
||||
+ .virtual = CNS3XXX_GPIOB_BASE_VIRT,
|
||||
+ .pfn = __phys_to_pfn(CNS3XXX_GPIOB_BASE),
|
||||
+ .length = SZ_4K,
|
||||
+ .type = MT_DEVICE,
|
||||
},
|
||||
};
|
||||
|
||||
@ -1,54 +0,0 @@
|
||||
--- a/arch/arm/mach-cns3xxx/core.c
|
||||
+++ b/arch/arm/mach-cns3xxx/core.c
|
||||
@@ -273,13 +273,26 @@ void __init cns3xxx_timer_init(void)
|
||||
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
|
||||
-void __init cns3xxx_l2x0_init(void)
|
||||
+static int cns3xxx_l2x0_enable = 1;
|
||||
+
|
||||
+static int __init cns3xxx_l2x0_disable(char *s)
|
||||
+{
|
||||
+ cns3xxx_l2x0_enable = 0;
|
||||
+ return 1;
|
||||
+}
|
||||
+__setup("nol2x0", cns3xxx_l2x0_disable);
|
||||
+
|
||||
+static int __init cns3xxx_l2x0_init(void)
|
||||
{
|
||||
- void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
|
||||
+ void __iomem *base;
|
||||
u32 val;
|
||||
|
||||
+ if (!cns3xxx_l2x0_enable)
|
||||
+ return 0;
|
||||
+
|
||||
+ base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
|
||||
if (WARN_ON(!base))
|
||||
- return;
|
||||
+ return 0;
|
||||
|
||||
/*
|
||||
* Tag RAM Control register
|
||||
@@ -309,7 +322,10 @@ void __init cns3xxx_l2x0_init(void)
|
||||
|
||||
/* 32 KiB, 8-way, parity disable */
|
||||
l2x0_init(base, 0x00540000, 0xfe000fff);
|
||||
+
|
||||
+ return 0;
|
||||
}
|
||||
+arch_initcall(cns3xxx_l2x0_init);
|
||||
|
||||
#endif /* CONFIG_CACHE_L2X0 */
|
||||
|
||||
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
|
||||
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
|
||||
@@ -239,8 +239,6 @@ static struct platform_device *cns3420_p
|
||||
|
||||
static void __init cns3420_init(void)
|
||||
{
|
||||
- cns3xxx_l2x0_init();
|
||||
-
|
||||
platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
|
||||
|
||||
cns3xxx_ahci_init();
|
||||
@ -1,46 +0,0 @@
|
||||
--- a/arch/arm/mach-cns3xxx/Kconfig
|
||||
+++ b/arch/arm/mach-cns3xxx/Kconfig
|
||||
@@ -27,4 +27,12 @@ config MACH_CNS3420VB
|
||||
This is a platform with an on-board ARM11 MPCore and has support
|
||||
for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, etc.
|
||||
|
||||
+config MACH_GW2388
|
||||
+ bool "Support for Gateworks Laguna Platform"
|
||||
+ help
|
||||
+ Include support for the Gateworks Laguna Platform
|
||||
+
|
||||
+ This is a platform with an on-board ARM11 MPCore and has support
|
||||
+ for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, I2C, GIG, etc.
|
||||
+
|
||||
endmenu
|
||||
--- a/arch/arm/mach-cns3xxx/Makefile
|
||||
+++ b/arch/arm/mach-cns3xxx/Makefile
|
||||
@@ -7,3 +7,5 @@ cns3xxx-$(CONFIG_PCI) += pcie.o
|
||||
cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
|
||||
cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o cns3xxx_fiq.o
|
||||
cns3xxx-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
+cns3xxx-$(CONFIG_MACH_GW2388) += laguna.o
|
||||
+
|
||||
--- a/arch/arm/mach-cns3xxx/devices.c
|
||||
+++ b/arch/arm/mach-cns3xxx/devices.c
|
||||
@@ -16,6 +16,7 @@
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/platform_device.h>
|
||||
+#include <asm/mach-types.h>
|
||||
#include "cns3xxx.h"
|
||||
#include "pm.h"
|
||||
#include "core.h"
|
||||
@@ -101,7 +102,11 @@ void __init cns3xxx_sdhci_init(void)
|
||||
u32 gpioa_pins = __raw_readl(gpioa);
|
||||
|
||||
/* MMC/SD pins share with GPIOA */
|
||||
- gpioa_pins |= 0x1fff0004;
|
||||
+ if (machine_is_gw2388()) {
|
||||
+ gpioa_pins |= 0x1fff0000;
|
||||
+ } else {
|
||||
+ gpioa_pins |= 0x1fff0004;
|
||||
+ }
|
||||
__raw_writel(gpioa_pins, gpioa);
|
||||
|
||||
cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
|
||||
@ -1,16 +0,0 @@
|
||||
--- a/drivers/mmc/host/sdhci-cns3xxx.c
|
||||
+++ b/drivers/mmc/host/sdhci-cns3xxx.c
|
||||
@@ -88,10 +88,11 @@ static const struct sdhci_pltfm_data sdh
|
||||
.ops = &sdhci_cns3xxx_ops,
|
||||
.quirks = SDHCI_QUIRK_BROKEN_DMA |
|
||||
SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
|
||||
- SDHCI_QUIRK_INVERTED_WRITE_PROTECT |
|
||||
+ //SDHCI_QUIRK_INVERTED_WRITE_PROTECT |
|
||||
SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
|
||||
SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
|
||||
- SDHCI_QUIRK_NONSTANDARD_CLOCK,
|
||||
+ SDHCI_QUIRK_NONSTANDARD_CLOCK |
|
||||
+ SDHCI_QUIRK_BROKEN_CARD_DETECTION,
|
||||
};
|
||||
|
||||
static int sdhci_cns3xxx_probe(struct platform_device *pdev)
|
||||
@ -1,193 +0,0 @@
|
||||
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
|
||||
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
|
||||
@@ -274,7 +274,7 @@ static int __init cns3420vb_pcie_init(vo
|
||||
if (!machine_is_cns3420vb())
|
||||
return 0;
|
||||
|
||||
- return cns3xxx_pcie_init();
|
||||
+ return cns3xxx_pcie_init(NULL, NULL);
|
||||
}
|
||||
subsys_initcall(cns3420vb_pcie_init);
|
||||
|
||||
--- a/arch/arm/mach-cns3xxx/core.h
|
||||
+++ b/arch/arm/mach-cns3xxx/core.h
|
||||
@@ -19,7 +19,7 @@ extern void cns3xxx_pcie_iotable_init(vo
|
||||
|
||||
void __init cns3xxx_map_io(void);
|
||||
void __init cns3xxx_init_irq(void);
|
||||
-int __init cns3xxx_pcie_init(void);
|
||||
+int __init cns3xxx_pcie_init(int *pcie0_irqs, int *pcie1_irqs);
|
||||
void cns3xxx_power_off(void);
|
||||
void cns3xxx_restart(enum reboot_mode, const char *);
|
||||
|
||||
--- a/arch/arm/mach-cns3xxx/laguna.c
|
||||
+++ b/arch/arm/mach-cns3xxx/laguna.c
|
||||
@@ -21,6 +21,7 @@
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/io.h>
|
||||
+#include <linux/irq.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/serial_core.h>
|
||||
@@ -873,12 +874,42 @@ static int laguna_register_gpio(struct g
|
||||
return ret;
|
||||
}
|
||||
|
||||
+/* allow disabling of external isolated PCIe IRQs */
|
||||
+static int cns3xxx_pciextirq = 1;
|
||||
+static int __init cns3xxx_pciextirq_disable(char *s)
|
||||
+{
|
||||
+ cns3xxx_pciextirq = 0;
|
||||
+ return 1;
|
||||
+}
|
||||
+__setup("noextirq", cns3xxx_pciextirq_disable);
|
||||
+
|
||||
static int __init laguna_pcie_init(void)
|
||||
{
|
||||
+ u32 __iomem *mem = (void __iomem *)(CNS3XXX_GPIOB_BASE_VIRT + 0x0004);
|
||||
+ u32 reg = (__raw_readl(mem) >> 26) & 0xf;
|
||||
+ int irqs[] = {
|
||||
+ IRQ_CNS3XXX_EXTERNAL_PIN0,
|
||||
+ IRQ_CNS3XXX_EXTERNAL_PIN1,
|
||||
+ IRQ_CNS3XXX_EXTERNAL_PIN2,
|
||||
+ 154,
|
||||
+ };
|
||||
+
|
||||
if (!machine_is_gw2388())
|
||||
return 0;
|
||||
|
||||
- return cns3xxx_pcie_init();
|
||||
+ /* Verify GPIOB[26:29] == 0001b indicating support for ext irqs */
|
||||
+ if (cns3xxx_pciextirq && reg != 1)
|
||||
+ cns3xxx_pciextirq = 0;
|
||||
+
|
||||
+ if (cns3xxx_pciextirq) {
|
||||
+ printk("laguna: using isolated PCI interrupts:"
|
||||
+ " irq%d/irq%d/irq%d/irq%d\n",
|
||||
+ irqs[0], irqs[1], irqs[2], irqs[3]);
|
||||
+ return cns3xxx_pcie_init(irqs, NULL);
|
||||
+ }
|
||||
+ printk("laguna: using shared PCI interrupts: irq%d\n",
|
||||
+ IRQ_CNS3XXX_PCIE0_DEVICE);
|
||||
+ return cns3xxx_pcie_init(NULL, NULL);
|
||||
}
|
||||
subsys_initcall(laguna_pcie_init);
|
||||
|
||||
@@ -893,8 +924,33 @@ static int __init laguna_model_setup(voi
|
||||
printk("Running on Gateworks Laguna %s\n", laguna_info.model);
|
||||
cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
|
||||
NR_IRQS_CNS3XXX);
|
||||
- cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
|
||||
- NR_IRQS_CNS3XXX + 32);
|
||||
+
|
||||
+ /*
|
||||
+ * If pcie external interrupts are supported and desired
|
||||
+ * configure IRQ types and configure pin function.
|
||||
+ * Note that cns3xxx_pciextirq is enabled by default, but can be
|
||||
+ * unset via the 'noextirq' kernel param or by laguna_pcie_init() if
|
||||
+ * the baseboard model does not support this hardware feature.
|
||||
+ */
|
||||
+ if (cns3xxx_pciextirq) {
|
||||
+ mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0018);
|
||||
+ reg = __raw_readl(mem);
|
||||
+ /* GPIO26 is gpio, EXT_INT[0:2] not gpio func */
|
||||
+ reg &= ~0x3c000000;
|
||||
+ reg |= 0x38000000;
|
||||
+ __raw_writel(reg, mem);
|
||||
+
|
||||
+ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT,
|
||||
+ IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32);
|
||||
+
|
||||
+ irq_set_irq_type(154, IRQ_TYPE_LEVEL_LOW);
|
||||
+ irq_set_irq_type(93, IRQ_TYPE_LEVEL_HIGH);
|
||||
+ irq_set_irq_type(94, IRQ_TYPE_LEVEL_HIGH);
|
||||
+ irq_set_irq_type(95, IRQ_TYPE_LEVEL_HIGH);
|
||||
+ } else {
|
||||
+ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT,
|
||||
+ IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32);
|
||||
+ }
|
||||
|
||||
if (strncmp(laguna_info.model, "GW", 2) == 0) {
|
||||
if (laguna_info.config_bitmap & ETH0_LOAD)
|
||||
--- a/arch/arm/mach-cns3xxx/pcie.c
|
||||
+++ b/arch/arm/mach-cns3xxx/pcie.c
|
||||
@@ -18,6 +18,7 @@
|
||||
#include <linux/io.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/interrupt.h>
|
||||
+#include <linux/irq.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include "cns3xxx.h"
|
||||
@@ -32,7 +33,7 @@ enum cns3xxx_access_type {
|
||||
|
||||
struct cns3xxx_pcie {
|
||||
struct map_desc cfg_bases[CNS3XXX_NUM_ACCESS_TYPES];
|
||||
- unsigned int irqs[2];
|
||||
+ unsigned int irqs[6];
|
||||
struct resource res_io;
|
||||
struct resource res_mem;
|
||||
struct hw_pci hw_pci;
|
||||
@@ -255,7 +256,7 @@ static struct pci_ops cns3xxx_pcie_ops =
|
||||
static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
||||
{
|
||||
struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
|
||||
- int irq = cnspci->irqs[slot];
|
||||
+ int irq = cnspci->irqs[slot+pin-1];
|
||||
|
||||
pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
|
||||
pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
|
||||
@@ -298,7 +299,12 @@ static struct cns3xxx_pcie cns3xxx_pcie[
|
||||
.end = CNS3XXX_PCIE0_MEM_BASE + SZ_16M - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
- .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
|
||||
+ .irqs = { IRQ_CNS3XXX_PCIE0_RC,
|
||||
+ IRQ_CNS3XXX_PCIE0_DEVICE,
|
||||
+ IRQ_CNS3XXX_PCIE0_DEVICE,
|
||||
+ IRQ_CNS3XXX_PCIE0_DEVICE,
|
||||
+ IRQ_CNS3XXX_PCIE0_DEVICE,
|
||||
+ },
|
||||
.hw_pci = {
|
||||
.domain = 0,
|
||||
.nr_controllers = 1,
|
||||
@@ -340,7 +346,13 @@ static struct cns3xxx_pcie cns3xxx_pcie[
|
||||
.end = CNS3XXX_PCIE1_MEM_BASE + SZ_16M - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
- .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
|
||||
+ .irqs = {
|
||||
+ IRQ_CNS3XXX_PCIE1_RC,
|
||||
+ IRQ_CNS3XXX_PCIE1_DEVICE,
|
||||
+ IRQ_CNS3XXX_PCIE1_DEVICE,
|
||||
+ IRQ_CNS3XXX_PCIE1_DEVICE,
|
||||
+ IRQ_CNS3XXX_PCIE1_DEVICE,
|
||||
+ },
|
||||
.hw_pci = {
|
||||
.domain = 1,
|
||||
.nr_controllers = 1,
|
||||
@@ -460,13 +472,22 @@ void __init cns3xxx_pcie_iotable_init()
|
||||
}
|
||||
}
|
||||
|
||||
-int __init cns3xxx_pcie_init(void)
|
||||
+int __init cns3xxx_pcie_init(int *pcie0_irqs, int *pcie1_irqs)
|
||||
{
|
||||
int i;
|
||||
|
||||
pcibios_min_io = 0;
|
||||
pcibios_min_mem = 0;
|
||||
|
||||
+ if (pcie0_irqs) {
|
||||
+ for (i = 0; i < 4; i++)
|
||||
+ cns3xxx_pcie[0].irqs[i+1] = pcie0_irqs[i];
|
||||
+ }
|
||||
+ if (pcie1_irqs) {
|
||||
+ for (i = 0; i < 4; i++)
|
||||
+ cns3xxx_pcie[1].irqs[i+1] = pcie1_irqs[i];
|
||||
+ }
|
||||
+
|
||||
hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0,
|
||||
"imprecise external abort");
|
||||
|
||||
@ -1,53 +0,0 @@
|
||||
--- a/arch/arm/mach-cns3xxx/pcie.c
|
||||
+++ b/arch/arm/mach-cns3xxx/pcie.c
|
||||
@@ -71,7 +71,7 @@ static void __iomem *cns3xxx_pci_cfg_bas
|
||||
void __iomem *base;
|
||||
|
||||
/* If there is no link, just show the CNS PCI bridge. */
|
||||
- if (!cnspci->linked && (busno > 0 || slot > 0))
|
||||
+ if (!cnspci->linked && (busno > 0))
|
||||
return NULL;
|
||||
|
||||
/*
|
||||
@@ -80,15 +80,19 @@ static void __iomem *cns3xxx_pci_cfg_bas
|
||||
* the first device on the same bus as the CNS PCI bridge.
|
||||
*/
|
||||
if (busno == 0) {
|
||||
- if (slot > 1)
|
||||
+ type = CNS3XXX_HOST_TYPE;
|
||||
+ if (devfn)
|
||||
+ return NULL;
|
||||
+ } else if (busno == 1) {
|
||||
+ type = CNS3XXX_CFG0_TYPE;
|
||||
+ if (slot)
|
||||
return NULL;
|
||||
- type = slot;
|
||||
} else {
|
||||
type = CNS3XXX_CFG1_TYPE;
|
||||
}
|
||||
|
||||
base = (void __iomem *)cnspci->cfg_bases[type].virtual;
|
||||
- offset = ((busno & 0xf) << 20) | (devfn << 12) | (where & 0xffc);
|
||||
+ offset = (devfn << 12) | (where & 0xffc);
|
||||
|
||||
return base + offset;
|
||||
}
|
||||
@@ -256,7 +260,7 @@ static struct pci_ops cns3xxx_pcie_ops =
|
||||
static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
||||
{
|
||||
struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
|
||||
- int irq = cnspci->irqs[slot+pin-1];
|
||||
+ int irq = cnspci->irqs[!!dev->bus->number+pin-1];
|
||||
|
||||
pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
|
||||
pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
|
||||
@@ -434,7 +438,8 @@ static void __init cns3xxx_pcie_hw_init(
|
||||
return;
|
||||
|
||||
/* Set Device Max_Read_Request_Size to 128 byte */
|
||||
- devfn = PCI_DEVFN(1, 0);
|
||||
+ bus.number = 1;
|
||||
+ devfn = PCI_DEVFN(0, 0);
|
||||
pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP);
|
||||
pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
|
||||
dc &= ~(0x3 << 12); /* Clear Device Control Register [14:12] */
|
||||
@ -1,11 +0,0 @@
|
||||
--- a/arch/arm/mach-cns3xxx/pcie.c
|
||||
+++ b/arch/arm/mach-cns3xxx/pcie.c
|
||||
@@ -93,6 +93,8 @@ static void __iomem *cns3xxx_pci_cfg_bas
|
||||
|
||||
base = (void __iomem *)cnspci->cfg_bases[type].virtual;
|
||||
offset = (devfn << 12) | (where & 0xffc);
|
||||
+ if (busno > 1)
|
||||
+ offset += busno << 20;
|
||||
|
||||
return base + offset;
|
||||
}
|
||||
@ -1,14 +0,0 @@
|
||||
--- a/drivers/net/phy/broadcom.c
|
||||
+++ b/drivers/net/phy/broadcom.c
|
||||
@@ -567,6 +567,11 @@ static int bcm5481_config_aneg(struct ph
|
||||
/* Write bits 14:0. */
|
||||
reg |= (1 << 15);
|
||||
phy_write(phydev, 0x18, reg);
|
||||
+ } else {
|
||||
+ phy_write(phydev, 0x18, 0xf1e7);
|
||||
+ phy_write(phydev, 0x1c, 0x8e00);
|
||||
+
|
||||
+ phy_write(phydev, 0x1c, 0xa41f);
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -1,47 +0,0 @@
|
||||
--- a/drivers/usb/dwc2/platform.c
|
||||
+++ b/drivers/usb/dwc2/platform.c
|
||||
@@ -75,6 +75,34 @@ static const struct dwc2_core_params par
|
||||
.uframe_sched = 0,
|
||||
};
|
||||
|
||||
+static const struct dwc2_core_params params_cns3xxx = {
|
||||
+ .otg_cap = 2, /* non-HNP/non-SRP capable */
|
||||
+ .otg_ver = 0, /* 1.3 */
|
||||
+ .dma_enable = 1,
|
||||
+ .dma_desc_enable = 0,
|
||||
+ .speed = 0, /* High Speed */
|
||||
+ .enable_dynamic_fifo = 1,
|
||||
+ .en_multiple_tx_fifo = 1,
|
||||
+ .host_rx_fifo_size = 658, /* 774 DWORDs */
|
||||
+ .host_nperio_tx_fifo_size = 128, /* 256 DWORDs */
|
||||
+ .host_perio_tx_fifo_size = 658, /* 512 DWORDs */
|
||||
+ .max_transfer_size = 65535,
|
||||
+ .max_packet_count = 511,
|
||||
+ .host_channels = 16,
|
||||
+ .phy_type = 1, /* UTMI */
|
||||
+ .phy_utmi_width = 16, /* 8 bits */
|
||||
+ .phy_ulpi_ddr = 0, /* Single */
|
||||
+ .phy_ulpi_ext_vbus = 0,
|
||||
+ .i2c_enable = 0,
|
||||
+ .ulpi_fs_ls = 0,
|
||||
+ .host_support_fs_ls_low_power = 0,
|
||||
+ .host_ls_low_power_phy_clk = 0, /* 48 MHz */
|
||||
+ .ts_dline = 0,
|
||||
+ .reload_ctl = 0,
|
||||
+ .ahbcfg = 0x10,
|
||||
+ .uframe_sched = 0,
|
||||
+};
|
||||
+
|
||||
/**
|
||||
* dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
|
||||
* DWC_otg driver
|
||||
@@ -134,6 +162,9 @@ static int dwc2_driver_probe(struct plat
|
||||
/* Default all params to autodetect */
|
||||
dwc2_set_all_params(&defparams, -1);
|
||||
params = &defparams;
|
||||
+#ifdef CONFIG_ARCH_CNS3XXX
|
||||
+ params = ¶ms_cns3xxx;
|
||||
+#endif
|
||||
}
|
||||
|
||||
hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL);
|
||||
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Reference in New Issue