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add support for the Simplemachines Sim.One board

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SVN-Revision: 18540
v19.07.3_mercusys_ac12_duma
Florian Fainelli 15 years ago
parent 850fe2320f
commit 4bfa2947ee
16 changed files with 20547 additions and 0 deletions
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21
target/linux/ep93xx/Makefile
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#
# Copyright (C) 2009 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
ARCH:=arm
BOARD:=ep93xx
BOARDNAME:=Cirrus Logic EP93xx SoC
FEATURES:=squashfs jffs2 ext2 tgz
CFLAGS:=-Os -pipe -march=armv4t -funit-at-a-time
LINUX_VERSION:=2.6.30.9
include $(INCLUDE_DIR)/target.mk
KERNELNAME:="uImage"
$(eval $(call BuildTarget))

5
target/linux/ep93xx/base-files/etc/inittab
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::sysinit:/etc/init.d/rcS S boot
::shutdown:/etc/init.d/rcS K stop
tts/0::askfirst:/bin/ash --login
ttyAM0::askfirst:/bin/ash --login
tty1::askfirst:/bin/ash --login

239
target/linux/ep93xx/config-2.6.30
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CONFIG_AEABI=y
CONFIG_ALIGNMENT_TRAP=y
CONFIG_ARCH_EP93XX=y
CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_ARCH_REQUIRE_GPIOLIB=y
# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM=y
CONFIG_ARM_AMBA=y
CONFIG_ARM_THUMB=y
CONFIG_ARM_VIC=y
# CONFIG_ARPD is not set
# CONFIG_BINARY_PRINTF is not set
CONFIG_BITREVERSE=y
# CONFIG_BLK_DEV_INITRD is not set
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_CFG80211=y
# CONFIG_CFG80211_REG_DEBUG is not set
CONFIG_CMDLINE="console=ttyAM0,57600 init=/etc/preinit"
CONFIG_COMMON_CLKDEV=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_CPU_32=y
CONFIG_CPU_32v4T=y
CONFIG_CPU_ABRT_EV4T=y
CONFIG_CPU_ARM920T=y
CONFIG_CPU_CACHE_V4WT=y
CONFIG_CPU_CACHE_VIVT=y
CONFIG_CPU_COPY_V4WB=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
# CONFIG_CPU_ICACHE_DISABLE is not set
CONFIG_CPU_PABRT_NOIFAR=y
CONFIG_CPU_TLB_V4WBI=y
CONFIG_CRC7=y
CONFIG_CRC_ITU_T=y
CONFIG_CRUNCH=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_ARC4=y
CONFIG_CRYPTO_BLKCIPHER=y
CONFIG_CRYPTO_BLKCIPHER2=y
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_ECB=m
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=y
CONFIG_CRYPTO_PCBC=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_WORKQUEUE=y
CONFIG_DEBUG_USER=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_DM9000 is not set
CONFIG_DNOTIFY=y
CONFIG_DUMMY_CONSOLE=y
CONFIG_ELF_CORE=y
# CONFIG_ENABLE_WARN_DEPRECATED is not set
CONFIG_EP93XX_EARLY_UART1=y
# CONFIG_EP93XX_EARLY_UART2 is not set
# CONFIG_EP93XX_EARLY_UART3 is not set
CONFIG_EP93XX_ETH=y
CONFIG_EP93XX_WATCHDOG=y
CONFIG_FB=y
# CONFIG_FB_ARMCLCD is not set
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_EP93XX=y
# CONFIG_FB_EP93XX_MONO is not set
# CONFIG_FIRMWARE_EDID is not set
CONFIG_FONTS=y
# CONFIG_FONT_10x18 is not set
# CONFIG_FONT_6x11 is not set
# CONFIG_FONT_7x14 is not set
CONFIG_FONT_8x16=y
CONFIG_FONT_8x8=y
# CONFIG_FONT_ACORN_8x8 is not set
# CONFIG_FONT_MINI_4x6 is not set
# CONFIG_FONT_PEARL_8x8 is not set
# CONFIG_FONT_SUN12x22 is not set
# CONFIG_FONT_SUN8x16 is not set
# CONFIG_FPE_FASTFPE is not set
CONFIG_FPE_NWFPE=y
CONFIG_FPE_NWFPE_XP=y
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
CONFIG_FRAME_POINTER=y
# CONFIG_FW_LOADER is not set
# CONFIG_GENERIC_CLOCKEVENTS is not set
CONFIG_GENERIC_FIND_LAST_BIT=y
CONFIG_GENERIC_GPIO=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
# CONFIG_GENERIC_TIME is not set
CONFIG_GPIOLIB=y
# CONFIG_HAMRADIO is not set
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAVE_AOUT=y
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_HAVE_IDE=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
CONFIG_HAVE_MLOCK=y
CONFIG_HAVE_OPROFILE=y
CONFIG_HW_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_ALGOBIT=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_EP93XX=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
CONFIG_INPUT=y
# CONFIG_INPUT_MISC is not set
CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_IP_ADVANCED_ROUTER is not set
# CONFIG_IP_MULTICAST is not set
CONFIG_IP_PNP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_IP_PNP_RARP is not set
# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
# CONFIG_JFFS2_SUMMARY is not set
CONFIG_LCD_HD44780=m
CONFIG_LCD_LINUX=m
CONFIG_LIBCRC32C=y
CONFIG_LOCALVERSION_AUTO=y
CONFIG_LOCK_KERNEL=y
CONFIG_LOGO=y
CONFIG_LOGO_LINUX_CLUT224=y
CONFIG_LOGO_LINUX_MONO=y
CONFIG_LOGO_LINUX_VGA16=y
CONFIG_LOG_BUF_SHIFT=16
CONFIG_MAC80211=m
# CONFIG_MAC80211_DEBUGFS is not set
# CONFIG_MAC80211_DEBUG_MENU is not set
# CONFIG_MAC80211_HWSIM is not set
# CONFIG_MAC80211_LEDS is not set
# CONFIG_MAC80211_MESH is not set
CONFIG_MAC80211_RC_DEFAULT="pid"
# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
CONFIG_MAC80211_RC_DEFAULT_PID=y
CONFIG_MAC80211_RC_MINSTREL=y
CONFIG_MAC80211_RC_PID=y
# CONFIG_MACH_ADSSPHERE is not set
# CONFIG_MACH_EDB9302 is not set
# CONFIG_MACH_EDB9302A is not set
# CONFIG_MACH_EDB9307 is not set
# CONFIG_MACH_EDB9307A is not set
# CONFIG_MACH_EDB9312 is not set
# CONFIG_MACH_EDB9315 is not set
# CONFIG_MACH_EDB9315A is not set
# CONFIG_MACH_GESBC9312 is not set
# CONFIG_MACH_MICRO9 is not set
# CONFIG_MACH_MICRO9H is not set
# CONFIG_MACH_MICRO9L is not set
# CONFIG_MACH_MICRO9M is not set
CONFIG_MACH_SIM_ONE=y
# CONFIG_MACH_TS72XX is not set
# CONFIG_MFD_T7L66XB is not set
# CONFIG_MISC_DEVICES is not set
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_SPI=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
# CONFIG_MTD_CFI_GEOMETRY is not set
CONFIG_MTD_CFI_STAA=y
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_RAM=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETFILTER is not set
CONFIG_NET_KEY=y
# CONFIG_NEW_LEDS is not set
CONFIG_NLS=y
# CONFIG_NO_IOPORT is not set
CONFIG_OABI_COMPAT=y
# CONFIG_OUTER_CACHE is not set
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_PAGE_OFFSET=0xC0000000
# CONFIG_PCI_SYSCALL is not set
CONFIG_PREEMPT=y
# CONFIG_ROMFS_BACKED_BY_BLOCK is not set
# CONFIG_ROMFS_BACKED_BY_BOTH is not set
# CONFIG_ROMFS_BACKED_BY_MTD is not set
# CONFIG_SCSI_DMA is not set
# CONFIG_SDIO_UART is not set
# CONFIG_SERIAL_8250 is not set
CONFIG_SERIAL_AMBA_PL010=y
CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
# CONFIG_SERIAL_AMBA_PL011 is not set
# CONFIG_SLOW_WORK is not set
CONFIG_SPI=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_EP93XX=y
# CONFIG_SPI_GPIO is not set
CONFIG_SPI_MASTER=y
# CONFIG_SPI_SPIDEV is not set
CONFIG_SPLIT_PTLOCK_CPUS=4096
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_TOUCHSCREEN_EP93XX=y
CONFIG_TRACING_SUPPORT=y
CONFIG_UID16=y
# CONFIG_USB_ARCH_HAS_EHCI is not set
CONFIG_USB_SUPPORT=y
CONFIG_VECTORS_BASE=0xffff0000
# CONFIG_VGA_CONSOLE is not set
CONFIG_VIDEO_OUTPUT_CONTROL=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZONE_DMA_FLAG=0

35
target/linux/ep93xx/image/Makefile
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#
# Copyright (C) 2009 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/image.mk
define Image/Prepare
cp $(LINUX_DIR)/arch/arm/boot/uImage $(KDIR)/uImage
endef
define Image/BuildKernel
endef
define Image/Build/jffs2-64k
dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/openwrt-$(BOARD)-$(1).img bs=64k conv=sync
endef
define Image/Build/jffs2-128k
dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/openwrt-$(BOARD)-$(1).img bs=128k conv=sync
endef
define Image/Build/squashfs
$(call prepare_generic_squashfs,$(KDIR)/root.squashfs)
dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/openwrt-$(BOARD)-$(1).img bs=128k conv=sync
endef
define Image/Build
cp $(KDIR)/uImage $(BIN_DIR)/uImage-$(board)
$(call Image/Build/$(1),$(1))
endef
$(eval $(call BuildImage))

479
target/linux/ep93xx/patches-2.6.30/001-ep93xx-regs.patch
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--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -57,6 +57,33 @@
#define EP93XX_APB_SIZE 0x00200000
+/* 8081_0000 - 8081_ffff: Timers */
+#define TIMERS_OFFSET 0x010000
+#define TIMERS_BASE (EP93XX_APB_VIRT_BASE|TIMERS_OFFSET)
+
+#define TIMER1LOAD (TIMERS_BASE+0x00)
+#define TIMER1VALUE (TIMERS_BASE+0x04)
+#define TIMER1CONTROL (TIMERS_BASE+0x08)
+#define TIMER1CLEAR (TIMERS_BASE+0x0C)
+#define TIMER1TEST (TIMERS_BASE+0x10)
+
+#define TIMER2LOAD (TIMERS_BASE+0x20)
+#define TIMER2VALUE (TIMERS_BASE+0x24)
+#define TIMER2CONTROL (TIMERS_BASE+0x28)
+#define TIMER2CLEAR (TIMERS_BASE+0x2C)
+#define TIMER2TEST (TIMERS_BASE+0x30)
+
+#define TIMER3LOAD (TIMERS_BASE+0x80)
+#define TIMER3VALUE (TIMERS_BASE+0x84)
+#define TIMER3CONTROL (TIMERS_BASE+0x88)
+#define TIMER3CLEAR (TIMERS_BASE+0x8C)
+#define TIMER3TEST (TIMERS_BASE+0x90)
+
+#define TTIMERBZCONT (TIMERS_BASE+0x40)
+
+#define TIMER4VALUELOW (TIMERS_BASE+0x60)
+#define TIMER4VALUEHIGH (TIMERS_BASE+0x64)
+
/* AHB peripherals */
#define EP93XX_DMA_BASE ((void __iomem *) \
(EP93XX_AHB_VIRT_BASE + 0x00000000))
@@ -105,6 +132,8 @@
#define EP93XX_I2S_BASE (EP93XX_APB_VIRT_BASE + 0x00020000)
#define EP93XX_SECURITY_BASE (EP93XX_APB_VIRT_BASE + 0x00030000)
+#define EP93XX_SECURITY_REG(x) (EP93XX_SECURITY_BASE + (x))
+#define EP93XX_SECURITY_UNIQID EP93XX_SECURITY_REG(0x2440)
#define EP93XX_GPIO_BASE (EP93XX_APB_VIRT_BASE + 0x00040000)
#define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x))
@@ -127,6 +156,7 @@
#define EP93XX_AAC_BASE (EP93XX_APB_VIRT_BASE + 0x00080000)
#define EP93XX_SPI_BASE (EP93XX_APB_VIRT_BASE + 0x000a0000)
+#define EP93XX_SPI_BASE_PHYS (EP93XX_APB_PHYS_BASE + 0x000a0000)
#define EP93XX_IRDA_BASE (EP93XX_APB_VIRT_BASE + 0x000b0000)
@@ -164,8 +194,425 @@
#define EP93XX_SYSCON_DEVICE_CONFIG_U2EN (1<<20)
#define EP93XX_SYSCON_DEVICE_CONFIG_U1EN (1<<18)
#define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0)
+#define EP93XX_SYSCON_CHIP_ID EP93XX_SYSCON_REG(0x94)
+#define EP93XX_SYSCON_BMAR EP93XX_SYSCON_REG(0x54)
+#define EP93XX_SYSCON_I2SDIV EP93XX_SYSCON_REG(0x8C)
+#define EP93XX_SYSCON_DEVCFG_CONFIG_Mong 0x02000000
+#define EP93XX_SYSCON_DEVCFG_CONFIG_Tong 0x04000000
+#define EP93XX_SYSCON_DEVCFG_CONFIG_I2SONSSP 0x00000080
+#define EP93XX_SYSCON_DEVCFG_CONFIG_I2SONAC97 0x00000040
+#define EP93XX_SYSCON_DEVCFG_RasOnP3 0x00000010
+#define EP93XX_SYSCON_DEVCFG_A1onG 0x00200000
+#define EP93XX_SYSCON_DEVCFG_A2onG 0x00400000
+#define EP93XX_SYSCON_DEVCFG_U1EN 0x00040000
+#define EP93XX_SYSCON_DEVCFG_TIN 0x00020000
#define EP93XX_WATCHDOG_BASE (EP93XX_APB_VIRT_BASE + 0x00140000)
+#define SYSCON_PWRCNT (EP93XX_SYSCON_BASE+0x0004)
+#define SYSCON_VIDDIV (EP93XX_SYSCON_BASE+0x0084)
+#define SYSCON_MIRDIV (EP93XX_SYSCON_BASE+0x0088)
+#define SYSCON_KTDIV (EP93XX_SYSCON_BASE+0x0090)
+#define SYSCON_KTDIV_TSEN 0x80000000
+//-----------------------------------------------------------------------------
+// SYSCON_CLKSET1
+//-----------------------------------------------------------------------------
+#define SYSCON_CLKSET1_PLL1_X2IPD_SHIFT 0
+#define SYSCON_CLKSET1_PLL1_X2IPD_MASK 0x0000001f
+#define SYSCON_CLKSET1_PLL1_X2FBD2_SHIFT 5
+#define SYSCON_CLKSET1_PLL1_X2FBD2_MASK 0x000007e0
+#define SYSCON_CLKSET1_PLL1_X1FBD1_SHIFT 11
+#define SYSCON_CLKSET1_PLL1_X1FBD1_MASK 0x0000f800
+#define SYSCON_CLKSET1_PLL1_PS_SHIFT 16
+#define SYSCON_CLKSET1_PLL1_PS_MASK 0x00030000
+#define SYSCON_CLKSET1_PCLKDIV_SHIFT 18
+#define SYSCON_CLKSET1_PCLKDIV_MASK 0x000c0000
+#define SYSCON_CLKSET1_HCLKDIV_SHIFT 20
+#define SYSCON_CLKSET1_HCLKDIV_MASK 0x00700000
+#define SYSCON_CLKSET1_nBYP1 0x00800000
+#define SYSCON_CLKSET1_SMCROM 0x01000000
+#define SYSCON_CLKSET1_FCLKDIV_SHIFT 25
+#define SYSCON_CLKSET1_FCLKDIV_MASK 0x0e000000
+
+#define SYSCON_CLKSET1_HSEL 0x00000001
+#define SYSCON_CLKSET1_PLL1_EXCLKSEL 0x00000002
+
+#define SYSCON_CLKSET1_PLL1_P_MASK 0x0000007C
+#define SYSCON_CLKSET1_PLL1_P_SHIFT 2
+
+#define SYSCON_CLKSET1_PLL1_M1_MASK 0x00000780
+#define SYSCON_CLKSET1_PLL1_M1_SHIFT 7
+#define SYSCON_CLKSET1_PLL1_M2_MASK 0x0000F800
+#define SYSCON_CLKSET1_PLL1_M2_SHIFT 11
+#define SYSCON_CLKSET1_PLL1_PS_MASK 0x00030000
+#define SYSCON_CLKSET1_PLL1_PS_SHIFT 16
+#define SYSCON_CLKSET1_PCLK_DIV_MASK 0x000C0000
+#define SYSCON_CLKSET1_PCLK_DIV_SHIFT 18
+#define SYSCON_CLKSET1_HCLK_DIV_MASK 0x00700000
+#define SYSCON_CLKSET1_HCLK_DIV_SHIFT 20
+#define SYSCON_CLKSET1_SMCROM 0x01000000
+#define SYSCON_CLKSET1_FCLK_DIV_MASK 0x0E000000
+#define SYSCON_CLKSET1_FCLK_DIV_SHIFT 25
+
+#define SYSCON_CLKSET2_PLL2_EN 0x00000001
+#define SYSCON_CLKSET2_PLL2EXCLKSEL 0x00000002
+#define SYSCON_CLKSET2_PLL2_P_MASK 0x0000007C
+#define SYSCON_CLKSET2_PLL2_P_SHIFT 2
+#define SYSCON_CLKSET2_PLL2_M2_MASK 0x00000F80
+#define SYSCON_CLKSET2_PLL2_M2_SHIFT 7
+#define SYSCON_CLKSET2_PLL2_M1_MASK 0x0001F000
+#define SYSCON_CLKSET2_PLL2_M1 12
+#define SYSCON_CLKSET2_PLL2_PS_MASK 0x000C0000
+#define SYSCON_CLKSET2_PLL2_PS_SHIFT 18
+#define SYSCON_CLKSET2_USBDIV_MASK 0xF0000000
+#define SYSCON_CLKSET2_USBDIV_SHIFT 28
+
+//-----------------------------------------------------------------------------
+// I2SDIV Register Defines
+//-----------------------------------------------------------------------------
+#define SYSCON_I2SDIV_MDIV_MASK 0x0000007f
+#define SYSCON_I2SDIV_MDIV_SHIFT 0
+#define SYSCON_I2SDIV_PDIV_MASK 0x00000300
+#define SYSCON_I2SDIV_PDIV_SHIFT 8
+#define SYSCON_I2SDIV_PSEL 0x00002000
+#define SYSCON_I2SDIV_ESEL 0x00004000
+#define SYSCON_I2SDIV_MENA 0x00008000
+#define SYSCON_I2SDIV_SDIV 0x00010000
+#define SYSCON_I2SDIV_LRDIV_MASK 0x00060000
+#define SYSCON_I2SDIV_LRDIV_SHIFT 17
+#define SYSCON_I2SDIV_SPOL 0x00080000
+#define SYSCON_I2SDIV_DROP 0x00100000
+#define SYSCON_I2SDIV_ORIDE 0x20000000
+#define SYSCON_I2SDIV_SLAVE 0x40000000
+#define SYSCON_I2SDIV_SENA 0x80000000
+
+#define SYSCON_I2SDIV_PDIV_OFF 0x00000000
+#define SYSCON_I2SDIV_PDIV_2 0x00000100
+#define SYSCON_I2SDIV_PDIV_25 0x00000200
+#define SYSCON_I2SDIV_PDIV_3 0x00000300
+
+#define SYSCON_I2SDIV_LRDIV_32 0x00000000
+#define SYSCON_I2SDIV_LRDIV_64 0x00020000
+#define SYSCON_I2SDIV_LRDIV_128 0x00040000
+
+//-----------------------------------------------------------------------------
+// VIDDIV Register Defines
+//-----------------------------------------------------------------------------
+#define SYSCON_VIDDIV_VDIV_MASK 0x0000007f
+#define SYSCON_VIDDIV_VDIV_SHIFT 0
+#define SYSCON_VIDDIV_PDIV_MASK 0x00000300
+#define SYSCON_VIDDIV_PDIV_SHIFT 8
+#define SYSCON_VIDDIV_PSEL 0x00002000
+#define SYSCON_VIDDIV_ESEL 0x00004000
+#define SYSCON_VIDDIV_VENA 0x00008000
+
+//-----------------------------------------------------------------------------
+// MIRDIV Register Defines
+//-----------------------------------------------------------------------------
+#define SYSCON_MIRDIV_MDIV_MASK 0x0000003f
+#define SYSCON_MIRDIV_MDIV_SHIFT 0
+#define SYSCON_MIRDIV_PDIV_MASK 0x00000300
+#define SYSCON_MIRDIV_PDIV_SHIFT 8
+#define SYSCON_MIRDIV_PSEL 0x00002000
+#define SYSCON_MIRDIV_ESEL 0x00004000
+#define SYSCON_MIRDIV_MENA 0x00008000
+
+/* 8082_0000 - 8082_ffff: I2S */
+#define I2S_OFFSET 0x020000
+#define I2S_BASE (EP93XX_APB_VIRT_BASE|I2S_OFFSET)
+#define I2S_PHYS_BASE (EP93XX_APB_PHYS_BASE + I2S_OFFSET)
+
+
+
+#define I2STxClkCfg (I2S_BASE+0x00) /* 8082.0000 R/W Transmitter clock config register */
+#define I2SRxClkCfg (I2S_BASE+0x04) /* 8082.0004 R/W Receiver clock config register */
+#define I2SGlSts (I2S_BASE+0x08) /* 8082.0008 R/W SAI Global Status register. */
+#define I2SGlCtrl (I2S_BASE+0x0C) /* 8082.000C R/W SAI Global Control register */
+
+#define I2STX0Lft (I2S_BASE+0x10) /* 8082.0010 R/W Left TX data reg for channel 0 */
+#define I2STX0Rt (I2S_BASE+0x14) /* 8082.0014 R/W Right TX data reg for channel 0 */
+#define I2STX1Lft (I2S_BASE+0x18) /* 8082.0018 R/W Left TX data reg for channel 1 */
+#define I2STX1Rt (I2S_BASE+0x1C) /* 8082.001C R/W Right TX data reg for channel 1 */
+#define I2STX2Lft (I2S_BASE+0x20) /* 8082.0020 R/W Left TX data reg for channel 2 */
+#define I2STX2Rt (I2S_BASE+0x24) /* 8082.0024 R/W Right TX data reg for channel 2 */
+
+#define I2STXLinCtrlData (I2S_BASE+0x28) /* 8082.0028 R/W TX Line Control data register */
+#define I2STXCtrl (I2S_BASE+0x2C) /* 8082.002C R/W TX Control register */
+#define I2STXWrdLen (I2S_BASE+0x30) /* 8082.0030 R/W TX Word Length */
+#define I2STX0En (I2S_BASE+0x34) /* 8082.0034 R/W TX0 Channel Enable */
+#define I2STX1En (I2S_BASE+0x38) /* 8082.0038 R/W TX1 Channel Enable */
+#define I2STX2En (I2S_BASE+0x3C) /* 8082.003C R/W TX2 Channel Enable */
+
+#define I2SRX0Lft (I2S_BASE+0x40) /* 8082.0040 R Left RX data reg for channel 0 */
+#define I2SRX0Rt (I2S_BASE+0x44) /* 8082.0044 R Right RX data reg for channel 0 */
+#define I2SRX1Lft (I2S_BASE+0x48) /* 8082.0048 R Left RX data reg for channel 1 */
+#define I2SRX1Rt (I2S_BASE+0x4C) /* 8082.004c R Right RX data reg for channel 1 */
+#define I2SRX2Lft (I2S_BASE+0x50) /* 8082.0050 R Left RX data reg for channel 2 */
+#define I2SRX2Rt (I2S_BASE+0x54) /* 8082.0054 R Right RX data reg for channel 2 */
+
+#define I2SRXLinCtrlData (I2S_BASE+0x58) /* 8082.0058 R/W RX Line Control data register */
+#define I2SRXCtrl (I2S_BASE+0x5C) /* 8082.005C R/W RX Control register */
+#define I2SRXWrdLen (I2S_BASE+0x60) /* 8082.0060 R/W RX Word Length */
+#define I2SRX0En (I2S_BASE+0x64) /* 8082.0064 R/W RX0 Channel Enable */
+#define I2SRX1En (I2S_BASE+0x68) /* 8082.0068 R/W RX1 Channel Enable */
+#define I2SRX2En (I2S_BASE+0x6C) /* 8082.006C R/W RX2 Channel Enable */
+
+/* 8084_0000 - 8084_ffff: GPIO */
+#define GPIO_OFFSET 0x040000
+#define GPIO_BASE (EP93XX_APB_VIRT_BASE|GPIO_OFFSET)
+#define GPIO_PADR (GPIO_BASE+0x00)
+#define GPIO_PBDR (GPIO_BASE+0x04)
+#define GPIO_PCDR (GPIO_BASE+0x08)
+#define GPIO_PDDR (GPIO_BASE+0x0C)
+#define GPIO_PADDR (GPIO_BASE+0x10)
+#define GPIO_PBDDR (GPIO_BASE+0x14)
+#define GPIO_PCDDR (GPIO_BASE+0x18)
+#define GPIO_PDDDR (GPIO_BASE+0x1C)
+#define GPIO_PEDR (GPIO_BASE+0x20)
+#define GPIO_PEDDR (GPIO_BASE+0x24)
+// #define 0x8084.0028 Reserved
+// #define 0x8084.002C Reserved
+#define GPIO_PFDR (GPIO_BASE+0x30)
+#define GPIO_PFDDR (GPIO_BASE+0x34)
+#define GPIO_PGDR (GPIO_BASE+0x38)
+#define GPIO_PGDDR (GPIO_BASE+0x3C)
+#define GPIO_PHDR (GPIO_BASE+0x40)
+#define GPIO_PHDDR (GPIO_BASE+0x44)
+// #define 0x8084.0048 RAZ RAZ
+#define GPIO_FINTTYPE1 (GPIO_BASE+0x4C)
+#define GPIO_FINTTYPE2 (GPIO_BASE+0x50)
+#define GPIO_FEOI (GPIO_BASE+0x54) /* WRITE ONLY - READ UNDEFINED */
+#define GPIO_FINTEN (GPIO_BASE+0x58)
+#define GPIO_INTSTATUSF (GPIO_BASE+0x5C)
+#define GPIO_RAWINTSTASUSF (GPIO_BASE+0x60)
+#define GPIO_FDB (GPIO_BASE+0x64)
+#define GPIO_PAPINDR (GPIO_BASE+0x68)
+#define GPIO_PBPINDR (GPIO_BASE+0x6C)
+#define GPIO_PCPINDR (GPIO_BASE+0x70)
+#define GPIO_PDPINDR (GPIO_BASE+0x74)
+#define GPIO_PEPINDR (GPIO_BASE+0x78)
+#define GPIO_PFPINDR (GPIO_BASE+0x7C)
+#define GPIO_PGPINDR (GPIO_BASE+0x80)
+#define GPIO_PHPINDR (GPIO_BASE+0x84)
+#define GPIO_AINTTYPE1 (GPIO_BASE+0x90)
+#define GPIO_AINTTYPE2 (GPIO_BASE+0x94)
+#define GPIO_AEOI (GPIO_BASE+0x98) /* WRITE ONLY - READ UNDEFINED */
+#define GPIO_AINTEN (GPIO_BASE+0x9C)
+#define GPIO_INTSTATUSA (GPIO_BASE+0xA0)
+#define GPIO_RAWINTSTSTISA (GPIO_BASE+0xA4)
+#define GPIO_ADB (GPIO_BASE+0xA8)
+#define GPIO_BINTTYPE1 (GPIO_BASE+0xAC)
+#define GPIO_BINTTYPE2 (GPIO_BASE+0xB0)
+#define GPIO_BEOI (GPIO_BASE+0xB4) /* WRITE ONLY - READ UNDEFINED */
+#define GPIO_BINTEN (GPIO_BASE+0xB8)
+#define GPIO_INTSTATUSB (GPIO_BASE+0xBC)
+#define GPIO_RAWINTSTSTISB (GPIO_BASE+0xC0)
+#define GPIO_BDB (GPIO_BASE+0xC4)
+#define GPIO_EEDRIVE (GPIO_BASE+0xC8)
+//#define Reserved (GPIO_BASE+0xCC)
+#define GPIO_TCR (GPIO_BASE+0xD0) /* Test Registers */
+#define GPIO_TISRA (GPIO_BASE+0xD4) /* Test Registers */
+#define GPIO_TISRB (GPIO_BASE+0xD8) /* Test Registers */
+#define GPIO_TISRC (GPIO_BASE+0xDC) /* Test Registers */
+#define GPIO_TISRD (GPIO_BASE+0xE0) /* Test Registers */
+#define GPIO_TISRE (GPIO_BASE+0xE4) /* Test Registers */
+#define GPIO_TISRF (GPIO_BASE+0xE8) /* Test Registers */
+#define GPIO_TISRG (GPIO_BASE+0xEC) /* Test Registers */
+#define GPIO_TISRH (GPIO_BASE+0xF0) /* Test Registers */
+#define GPIO_TCER (GPIO_BASE+0xF4) /* Test Registers */
+
+
+/* 8088_0000 - 8088_ffff: Ac97 Controller (AAC) */
+#define AC97_OFFSET 0x080000
+#define AC97_BASE (EP93XX_APB_VIRT_BASE|AC97_OFFSET)
+#define EP93XX_AC97_PHY_BASE (EP93XX_APB_PHYS_BASE|AC97_OFFSET)
+#define AC97DR1 (AC97_BASE+0x00) /* 8088.0000 R/W Data read or written from/to FIFO1 */
+#define AC97RXCR1 (AC97_BASE+0x04) /* 8088.0004 R/W Control register for receive */
+#define AC97TXCR1 (AC97_BASE+0x08) /* 8088.0008 R/W Control register for transmit */
+#define AC97SR1 (AC97_BASE+0x0C) /* 8088.000C R Status register */
+#define AC97RISR1 (AC97_BASE+0x10) /* 8088.0010 R Raw interrupt status register */
+#define AC97ISR1 (AC97_BASE+0x14) /* 8088.0014 R Interrupt Status */
+#define AC97IE1 (AC97_BASE+0x18) /* 8088.0018 R/W Interrupt Enable */
+ /* 8088.001C Reserved - RAZ */
+#define AC97DR2 (AC97_BASE+0x20) /* 8088.0020 R/W Data read or written from/to FIFO2 */
+#define AC97RXCR2 (AC97_BASE+0x24) /* 8088.0024 R/W Control register for receive */
+#define AC97TXCR2 (AC97_BASE+0x28) /* 8088.0028 R/W Control register for transmit */
+#define AC97SR2 (AC97_BASE+0x2C) /* 8088.002C R Status register */
+#define AC97RISR2 (AC97_BASE+0x30) /* 8088.0030 R Raw interrupt status register */
+#define AC97ISR2 (AC97_BASE+0x34) /* 8088.0034 R Interrupt Status */
+#define AC97IE2 (AC97_BASE+0x38) /* 8088.0038 R/W Interrupt Enable */
+ /* 8088.003C Reserved - RAZ */
+#define AC97DR3 (AC97_BASE+0x40) /* 8088.0040 R/W Data read or written from/to FIFO3. */
+#define AC97RXCR3 (AC97_BASE+0x44) /* 8088.0044 R/W Control register for receive */
+#define AC97TXCR3 (AC97_BASE+0x48) /* 8088.0048 R/W Control register for transmit */
+#define AC97SR3 (AC97_BASE+0x4C) /* 8088.004C R Status register */
+#define AC97RISR3 (AC97_BASE+0x50) /* 8088.0050 R Raw interrupt status register */
+#define AC97ISR3 (AC97_BASE+0x54) /* 8088.0054 R Interrupt Status */
+#define AC97IE3 (AC97_BASE+0x58) /* 8088.0058 R/W Interrupt Enable */
+ /* 8088.005C Reserved - RAZ */
+#define AC97DR2 (AC97_BASE+0x20) /* 8088.0020 R/W Data read or written from/to FIFO2 */
+#define AC97RXCR2 (AC97_BASE+0x24) /* 8088.0024 R/W Control register for receive */
+#define AC97TXCR2 (AC97_BASE+0x28) /* 8088.0028 R/W Control register for transmit */
+#define AC97SR2 (AC97_BASE+0x2C) /* 8088.002C R Status register */
+#define AC97RISR2 (AC97_BASE+0x30) /* 8088.0030 R Raw interrupt status register */
+#define AC97ISR2 (AC97_BASE+0x34) /* 8088.0034 R Interrupt Status */
+#define AC97IE2 (AC97_BASE+0x38) /* 8088.0038 R/W Interrupt Enable */
+ /* 8088.003C Reserved - RAZ */
+#define AC97DR3 (AC97_BASE+0x40) /* 8088.0040 R/W Data read or written from/to FIFO3. */
+#define AC97RXCR3 (AC97_BASE+0x44) /* 8088.0044 R/W Control register for receive */
+#define AC97TXCR3 (AC97_BASE+0x48) /* 8088.0048 R/W Control register for transmit */
+#define AC97SR3 (AC97_BASE+0x4C) /* 8088.004C R Status register */
+#define AC97RISR3 (AC97_BASE+0x50) /* 8088.0050 R Raw interrupt status register */
+#define AC97ISR3 (AC97_BASE+0x54) /* 8088.0054 R Interrupt Status */
+#define AC97IE3 (AC97_BASE+0x58) /* 8088.0058 R/W Interrupt Enable */
+ /* 8088.005C Reserved - RAZ */
+#define AC97DR4 (AC97_BASE+0x60) /* 8088.0060 R/W Data read or written from/to FIFO4. */
+#define AC97RXCR4 (AC97_BASE+0x64) /* 8088.0064 R/W Control register for receive */
+#define AC97TXCR4 (AC97_BASE+0x68) /* 8088.0068 R/W Control register for transmit */
+#define AC97SR4 (AC97_BASE+0x6C) /* 8088.006C R Status register */
+#define AC97RISR4 (AC97_BASE+0x70) /* 8088.0070 R Raw interrupt status register */
+#define AC97ISR4 (AC97_BASE+0x74) /* 8088.0074 R Interrupt Status */
+#define AC97IE4 (AC97_BASE+0x78) /* 8088.0078 R/W Interrupt Enable */
+ /* 8088.007C Reserved - RAZ */
+#define AC97S1DATA (AC97_BASE+0x80) /* 8088.0080 R/W Data received/transmitted on SLOT1 */
+#define AC97S2DATA (AC97_BASE+0x84) /* 8088.0084 R/W Data received/transmitted on SLOT2 */
+#define AC97S12DATA (AC97_BASE+0x88) /* 8088.0088 R/W Data received/transmitted on SLOT12 */
+#define AC97RGIS (AC97_BASE+0x8C) /* 8088.008C R/W Raw Global interrupt status register*/
+#define AC97GIS (AC97_BASE+0x90) /* 8088.0090 R Global interrupt status register */
+#define AC97IM (AC97_BASE+0x94) /* 8088.0094 R/W Interrupt mask register */
+#define AC97EOI (AC97_BASE+0x98) /* 8088.0098 W Interrupt clear register */
+#define AC97GCR (AC97_BASE+0x9C) /* 8088.009C R/W Main Control register */
+#define AC97RESET (AC97_BASE+0xA0) /* 8088.00A0 R/W RESET control register. */
+#define AC97SYNC (AC97_BASE+0xA4) /* 8088.00A4 R/W SYNC control register. */
+#define AC97GCIS (AC97_BASE+0xA8) /* 8088.00A8 R Global chan FIFO int status register */
+
+
+/* 800B_0000 - 800B_FFFF: VIC 0 */
+#define VIC0_OFFSET 0x0B0000
+#define VIC0_BASE (EP93XX_AHB_VIRT_BASE|VIC0_OFFSET)
+#define VIC0 (VIC0_BASE+0x000)
+#define VIC0IRQSTATUS (VIC0_BASE+0x000) /* R IRQ status register */
+#define VIC0FIQSTATUS (VIC0_BASE+0x004) /* R FIQ status register */
+#define VIC0RAWINTR (VIC0_BASE+0x008) /* R Raw interrupt status register */
+#define VIC0INTSELECT (VIC0_BASE+0x00C) /* R/W Interrupt select register */
+#define VIC0INTENABLE (VIC0_BASE+0x010) /* R/W Interrupt enable register */
+#define VIC0INTENCLEAR (VIC0_BASE+0x014) /* W Interrupt enable clear register */
+
+/* 8003_0000 - 8003_ffff: Raster */
+#define RASTER_OFFSET 0x030000
+#define RASTER_BASE (EP93XX_AHB_VIRT_BASE|RASTER_OFFSET)
+#define VLINESTOTAL (RASTER_BASE+0x00)
+#define VSYNCSTRTSTOP (RASTER_BASE+0x04)
+#define VACTIVESTRTSTOP (RASTER_BASE+0x08)
+#define VCLKSTRTSTOP (RASTER_BASE+0x0C)
+#define HCLKSTOTAL (RASTER_BASE+0x10)
+#define HSYNCSTRTSTOP (RASTER_BASE+0x14)
+#define HACTIVESTRTSTOP (RASTER_BASE+0x18)
+#define HCLKSTRTSTOP (RASTER_BASE+0x1C)
+#define BRIGHTNESS (RASTER_BASE+0x20)
+#define VIDEOATTRIBS (RASTER_BASE+0x24)
+#define VIDSCRNPAGE (RASTER_BASE+0x28)
+#define VIDSCRNHPG (RASTER_BASE+0x2C)
+#define SCRNLINES (RASTER_BASE+0x30)
+#define LINELENGTH (RASTER_BASE+0x34)
+#define VLINESTEP (RASTER_BASE+0x38)
+#define LINECARRY (RASTER_BASE+0x3C)
+#define BLINKRATE (RASTER_BASE+0x40)
+#define BLINKMASK (RASTER_BASE+0x44)
+#define BLINKPATTRN (RASTER_BASE+0x48)
+#define PATTRNMASK (RASTER_BASE+0x4C)
+#define BG_OFFSET (RASTER_BASE+0x50)
+#define PIXELMODE (RASTER_BASE+0x54)
+#define PARLLIFOUT (RASTER_BASE+0x58)
+#define PARLLIFIN (RASTER_BASE+0x5C)
+#define CURSOR_ADR_START (RASTER_BASE+0x60)
+#define CURSOR_ADR_RESET (RASTER_BASE+0x64)
+#define CURSORSIZE (RASTER_BASE+0x68)
+#define CURSORCOLOR1 (RASTER_BASE+0x6C)
+#define CURSORCOLOR2 (RASTER_BASE+0x70)
+#define CURSORXYLOC (RASTER_BASE+0x74)
+#define CURSOR_DHSCAN_LH_YLOC (RASTER_BASE+0x78)
+#define RASTER_SWLOCK (RASTER_BASE+0x7C)
+#define GS_LUT (RASTER_BASE+0x80)
+#define RASTER_TCR (RASTER_BASE+0x100)
+#define RASTER_TISRA (RASTER_BASE+0x104)
+#define RASTER_TISRB (RASTER_BASE+0x108)
+#define CURSOR_TISR (RASTER_BASE+0x10C)
+#define RASTER_TOCRA (RASTER_BASE+0x110)
+#define RASTER_TOCRB (RASTER_BASE+0x114)
+#define FIFO_TOCRA (RASTER_BASE+0x118)
+#define FIFO_TOCRB (RASTER_BASE+0x11C)
+#define BLINK_TISR (RASTER_BASE+0x120)
+#define DAC_TISRA (RASTER_BASE+0x124)
+#define DAC_TISRB (RASTER_BASE+0x128)
+#define SHIFT_TISR (RASTER_BASE+0x12C)
+#define DACMUX_TOCRA (RASTER_BASE+0x130)
+#define DACMUX_TOCRB (RASTER_BASE+0x134)
+#define PELMUX_TOCR (RASTER_BASE+0x138)
+#define VIDEO_TOCRA (RASTER_BASE+0x13C)
+#define VIDEO_TOCRB (RASTER_BASE+0x140)
+#define YCRCB_TOCR (RASTER_BASE+0x144)
+#define CURSOR_TOCR (RASTER_BASE+0x148)
+#define VIDEO_TOCRC (RASTER_BASE+0x14C)
+#define SHIFT_TOCR (RASTER_BASE+0x150)
+#define BLINK_TOCR (RASTER_BASE+0x154)
+#define RASTER_TCER (RASTER_BASE+0x180)
+#define SIGVAL (RASTER_BASE+0x200)
+#define SIGCTL (RASTER_BASE+0x204)
+#define VSIGSTRTSTOP (RASTER_BASE+0x208)
+#define HSIGSTRTSTOP (RASTER_BASE+0x20C)
+#define SIGCLR (RASTER_BASE+0x210)
+#define ACRATE (RASTER_BASE+0x214)
+#define LUTCONT (RASTER_BASE+0x218)
+#define VBLANKSTRTSTOP (RASTER_BASE+0x228)
+#define HBLANKSTRTSTOP (RASTER_BASE+0x22C)
+#define LUT (RASTER_BASE+0x400)
+#define CURSORBLINK1 (RASTER_BASE+0x21C)
+#define CURSORBLINK2 (RASTER_BASE+0x220)
+#define CURSORBLINK (RASTER_BASE+0x224)
+#define EOLOFFSET (RASTER_BASE+0x230)
+#define FIFOLEVEL (RASTER_BASE+0x234)
+#define GS_LUT2 (RASTER_BASE+0x280)
+#define GS_LUT3 (RASTER_BASE+0x300)
+#define COLOR_LUT (RASTER_BASE+0x400)
+
+/* 8004_0000 - 8004_ffff: Graphics */
+#define GRAPHICS_OFFSET 0x040000
+#define GRAPHICS_BASE (EP93XX_AHB_VIRT_BASE|GRAPHICS_OFFSET)
+#define SRCPIXELSTRT (GRAPHICS_BASE+0x00)
+#define DESTPIXELSTRT (GRAPHICS_BASE+0x04)
+#define BLKSRCSTRT (GRAPHICS_BASE+0x08)
+#define BLKDSTSTRT (GRAPHICS_BASE+0x0C)
+#define BLKSRCWIDTH (GRAPHICS_BASE+0x10)
+#define SRCLINELENGTH (GRAPHICS_BASE+0x14)
+#define BLKDESTWIDTH (GRAPHICS_BASE+0x18)
+#define BLKDESTHEIGHT (GRAPHICS_BASE+0x1C)
+#define DESTLINELENGTH (GRAPHICS_BASE+0x20)
+#define BLOCKCTRL (GRAPHICS_BASE+0x24)
+#define TRANSPATTRN (GRAPHICS_BASE+0x28)
+#define BLOCKMASK (GRAPHICS_BASE+0x2C)
+#define BACKGROUND (GRAPHICS_BASE+0x30)
+#define LINEINC (GRAPHICS_BASE+0x34)
+#define LINEINIT (GRAPHICS_BASE+0x38)
+#define LINEPATTRN (GRAPHICS_BASE+0x3C)
+
+#define EP93XX_RASTER_BASE (EP93XX_AHB_VIRT_BASE + 0x00030000)
+#define EP93XX_RASTER_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00030000)
+
+#define EP93XX_GRAPHICS_ACCEL_BASE (EP93XX_AHB_VIRT_BASE + 0x00040000)
+#define EP93XX_GRAPHICS_ACCEL_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00040000)
+
+#ifndef __ASSEMBLY__
+
+#define SysconSetLocked(registername,value) \
+ { \
+ local_irq_disable(); \
+ outl( 0xAA, EP93XX_SYSCON_SWLOCK); \
+ outl( value, registername); \
+ local_irq_enable(); \
+ }
+
+#endif /* Not __ASSEMBLY__ */
+
#endif

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target/linux/ep93xx/patches-2.6.30/002-lcd-linux-hd44780.patch
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target/linux/ep93xx/patches-2.6.30/003-ep93xx-i2c.patch
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@ -0,0 +1,225 @@
Index: linux-2.6.30.9/drivers/i2c/busses/Kconfig
===================================================================
--- linux-2.6.30.9.orig/drivers/i2c/busses/Kconfig 2009-11-24 21:00:21.000000000 +0100
+++ linux-2.6.30.9/drivers/i2c/busses/Kconfig 2009-11-24 21:00:23.000000000 +0100
@@ -326,6 +326,10 @@
devices such as DaVinci NIC.
For details please see http://www.ti.com/davinci
+config I2C_EP93XX
+ tristate "EP93XX I2C"
+ depends on I2C && ARCH_EP93XX
+
config I2C_GPIO
tristate "GPIO-based bitbanging I2C"
depends on GENERIC_GPIO
Index: linux-2.6.30.9/drivers/i2c/busses/Makefile
===================================================================
--- linux-2.6.30.9.orig/drivers/i2c/busses/Makefile 2009-11-24 21:00:21.000000000 +0100
+++ linux-2.6.30.9/drivers/i2c/busses/Makefile 2009-11-24 21:00:23.000000000 +0100
@@ -30,6 +30,7 @@
obj-$(CONFIG_I2C_BLACKFIN_TWI) += i2c-bfin-twi.o
obj-$(CONFIG_I2C_CPM) += i2c-cpm.o
obj-$(CONFIG_I2C_DAVINCI) += i2c-davinci.o
+obj-$(CONFIG_I2C_EP93XX) += i2c-ep93xx.o
obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o
obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o
obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o
Index: linux-2.6.30.9/drivers/i2c/busses/i2c-ep93xx.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-2.6.30.9/drivers/i2c/busses/i2c-ep93xx.c 2009-11-24 21:00:38.000000000 +0100
@@ -0,0 +1,193 @@
+/* ------------------------------------------------------------------------ *
+ * i2c-ep933xx.c I2C bus glue for Cirrus EP93xx *
+ * ------------------------------------------------------------------------ *
+
+ Copyright (C) 2004 Michael Burian
+
+ Based on i2c-parport-light.c
+ Copyright (C) 2003-2004 Jean Delvare <khali@linux-fr.org>
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * ------------------------------------------------------------------------ */
+
+
+//#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/i2c-algo-bit.h>
+#include <asm/io.h>
+#include <mach/hardware.h>
+
+//1/(2*clockfrequency)
+#define EE_DELAY_USEC 50
+#define GPIOG_EECLK 1
+#define GPIOG_EEDAT 2
+
+/* ----- I2C algorithm call-back functions and structures ----------------- */
+
+// TODO: optimize
+static void ep93xx_setscl(void *data, int state)
+{
+ unsigned int uiPGDR, uiPGDDR;
+
+ uiPGDR = inl(GPIO_PGDR);
+ uiPGDDR = inl(GPIO_PGDDR);
+
+ /* Configure the clock line as output. */
+ uiPGDDR |= GPIOG_EECLK;
+ outl(uiPGDDR, GPIO_PGDDR);
+
+ /* Set clock line to state */
+ if(state)
+ uiPGDR |= GPIOG_EECLK;
+ else
+ uiPGDR &= ~GPIOG_EECLK;
+
+ outl(uiPGDR, GPIO_PGDR);
+}
+
+static void ep93xx_setsda(void *data, int state)
+{
+ unsigned int uiPGDR, uiPGDDR;
+
+ uiPGDR = inl(GPIO_PGDR);
+ uiPGDDR = inl(GPIO_PGDDR);
+
+ /* Configure the data line as output. */
+ uiPGDDR |= GPIOG_EEDAT;
+ outl(uiPGDDR, GPIO_PGDDR);
+
+ /* Set data line to state */
+ if(state)
+ uiPGDR |= GPIOG_EEDAT;
+ else
+ uiPGDR &= ~GPIOG_EEDAT;
+
+ outl(uiPGDR, GPIO_PGDR);
+}
+
+static int ep93xx_getscl(void *data)
+{
+ unsigned int uiPGDR, uiPGDDR;
+
+ uiPGDR = inl(GPIO_PGDR);
+ uiPGDDR = inl(GPIO_PGDDR);
+
+ /* Configure the clock line as input */
+ uiPGDDR &= ~GPIOG_EECLK;
+ outl(uiPGDDR, GPIO_PGDDR);
+
+ /* Return state of the clock line */
+ return (inl(GPIO_PGDR) & GPIOG_EECLK) ? 1 : 0;
+}
+
+static int ep93xx_getsda(void *data)
+{
+ unsigned int uiPGDR, uiPGDDR;
+ uiPGDR = inl(GPIO_PGDR);
+ uiPGDDR = inl(GPIO_PGDDR);
+
+ /* Configure the data line as input */
+ uiPGDDR &= ~GPIOG_EEDAT;
+ outl(uiPGDDR, GPIO_PGDDR);
+
+ /* Return state of the data line */
+ return (inl(GPIO_PGDR) & GPIOG_EEDAT) ? 1 : 0;
+}
+
+/* ------------------------------------------------------------------------
+ * Encapsulate the above functions in the correct operations structure.
+ * This is only done when more than one hardware adapter is supported.
+ */
+
+/* last line (us, ms, timeout)
+ * us dominates the bit rate: 10us means: 100Kbit/sec(25 means 40kbps)
+ * 10ms not known
+ * 100ms timeout
+ */
+static struct i2c_algo_bit_data ep93xx_data = {
+ .setsda = ep93xx_setsda,
+ .setscl = ep93xx_setscl,
+ .getsda = ep93xx_getsda,
+ .getscl = ep93xx_getscl,
+ .udelay = 10,
+ //.mdelay = 10,
+ .timeout = HZ,
+};
+
+/* ----- I2c structure ---------------------------------------------------- */
+static struct i2c_adapter ep93xx_adapter = {
+ .owner = THIS_MODULE,
+ .class = I2C_CLASS_HWMON,
+ .algo_data = &ep93xx_data,
+ .name = "EP93XX I2C bit-bang interface",
+};
+
+/* ----- Module loading, unloading and information ------------------------ */
+
+static int __init i2c_ep93xx_init(void)
+{
+ unsigned long uiPGDR, uiPGDDR;
+
+ /* Read the current value of the GPIO data and data direction registers. */
+ uiPGDR = inl(GPIO_PGDR);
+ uiPGDDR = inl(GPIO_PGDDR);
+
+ /* If the GPIO pins have not been configured since reset, the data
+ * and clock lines will be set as inputs and with data value of 0.
+ * External pullup resisters are pulling them high.
+ * Set them both high before configuring them as outputs. */
+ uiPGDR |= (GPIOG_EEDAT | GPIOG_EECLK);
+ outl(uiPGDR, GPIO_PGDR);
+
+ /* Delay to meet the EE Interface timing specification. */
+ udelay(EE_DELAY_USEC);
+
+
+ /* Configure the EE data and clock lines as outputs. */
+ uiPGDDR |= (GPIOG_EEDAT | GPIOG_EECLK);
+ outl(uiPGDDR, GPIO_PGDDR);
+
+ /* Delay to meet the EE Interface timing specification. */
+ udelay(EE_DELAY_USEC);
+
+ /* Reset hardware to a sane state (SCL and SDA high) */
+ ep93xx_setsda(NULL, 1);
+ ep93xx_setscl(NULL, 1);
+
+ if (i2c_bit_add_bus(&ep93xx_adapter) > 0) {
+ printk(KERN_ERR "i2c-ep93xx: Unable to register with I2C\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static void __exit i2c_ep93xx_exit(void)
+{
+ //i2c_bit_del_bus(&ep93xx_adapter);
+ i2c_del_adapter(&ep93xx_adapter);
+}
+
+MODULE_AUTHOR("Michael Burian");
+MODULE_DESCRIPTION("I2C bus glue for Cirrus EP93xx processors");
+MODULE_LICENSE("GPL");
+
+module_init(i2c_ep93xx_init);
+module_exit(i2c_ep93xx_exit);

78
target/linux/ep93xx/patches-2.6.30/004-simone-rtc.patch
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@ -0,0 +1,78 @@
--- a/drivers/rtc/rtc-ds1307.c
+++ b/drivers/rtc/rtc-ds1307.c
@@ -661,6 +661,13 @@ static int __devinit ds1307_probe(struct
goto exit_free;
}
+#if (defined(CONFIG_MACH_SIM_ONE))
+ /* SIM.ONE board needs 32khz clock on SQW/INTB pin */
+ i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL,
+ ds1307->regs[0] & ~DS1337_BIT_INTCN);
+ i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL,
+ ds1307->regs[0] | (DS1337_BIT_RS1 | DS1337_BIT_RS2));
+#endif
/* oscillator off? turn it on, so clock can tick. */
if (ds1307->regs[0] & DS1337_BIT_nEOSC)
ds1307->regs[0] &= ~DS1337_BIT_nEOSC;
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -570,6 +570,14 @@ config RTC_DRV_EP93XX
This driver can also be built as a module. If so, the module
will be called rtc-ep93xx.
+config RTC_DRV_EP93XX_DS1337
+ bool "Cirrus Logic EP93XX using DS1337 chip"
+ depends on RTC_DRV_EP93XX && I2C && MACH_SIM_ONE
+ help
+ If you say yes here, the EP93XX driver will use the
+ battery-backed-up DS1337 RTC chip on the SIM.ONE board.
+ You almost certainly want this.
+
config RTC_DRV_SA1100
tristate "SA11x0/PXA2xx"
depends on ARCH_SA1100 || ARCH_PXA
--- a/drivers/rtc/rtc-ep93xx.c
+++ b/drivers/rtc/rtc-ep93xx.c
@@ -13,6 +13,13 @@
#include <linux/rtc.h>
#include <linux/platform_device.h>
#include <mach/hardware.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_RTC_DRV_EP93XX_DS1337)
+extern int ds1337_do_command(int id, int cmd, void *arg);
+#define DS1337_GET_DATE 0
+#define DS1337_SET_DATE 1
+#endif
#define EP93XX_RTC_REG(x) (EP93XX_RTC_BASE + (x))
#define EP93XX_RTC_DATA EP93XX_RTC_REG(0x0000)
@@ -37,16 +44,28 @@ static int ep93xx_get_swcomp(struct devi
static int ep93xx_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
+#if defined(CONFIG_RTC_DRV_EP93XX_DS1337)
+ /* Reroute the internal device to the DS1337 */
+ return ds1337_do_command(0, DS1337_GET_DATE, (void *)tm);
+#else
unsigned long time = __raw_readl(EP93XX_RTC_DATA);
rtc_time_to_tm(time, tm);
return 0;
+#endif
}
static int ep93xx_rtc_set_mmss(struct device *dev, unsigned long secs)
{
+#if defined(CONFIG_RTC_DRV_EP93XX_DS1337)
+ struct rtc_time tm;
+
+ rtc_time_to_tm(secs, &tm);
+ return ds1337_do_command(0, DS1337_SET_DATE, (void *)&tm);
+#else
__raw_writel(secs + 1, EP93XX_RTC_LOAD);
return 0;
+#endif
}
static int ep93xx_rtc_proc(struct device *dev, struct seq_file *seq)

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target/linux/ep93xx/patches-2.6.30/005-ep93xx-dma.patch
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target/linux/ep93xx/patches-2.6.30/006-ep93xx-touchscreen.patch
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target/linux/ep93xx/patches-2.6.30/007-ep93xx-eth.patch
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@ -0,0 +1,405 @@
--- /dev/null
+++ b/drivers/net/arm/ep93xx_eth.h
@@ -0,0 +1,402 @@
+/*------------------------------------------------------------------------
+ * ep93xx_eth.h
+ * : header file of Ethernet Device Driver for Cirrus Logic EP93xx.
+ *
+ * Copyright (C) 2003 by Cirrus Logic www.cirrus.com
+ * This software may be used and distributed according to the terms
+ * of the GNU Public License.
+ *
+ * This file contains device related information like register info
+ * and register access method macros for the Ethernet device
+ * embedded within Cirrus Logic's EP93xx SOC chip.
+ *
+ * Information contained in this file was obtained from
+ * the EP9312 Manual Revision 0.12 and 0.14 from Cirrus Logic.
+ *
+ * History
+ * 05/18/01 Sungwook Kim Initial release
+ * 03/25/2003 Melody Modified for EP92xx
+ *--------------------------------------------------------------------------*/
+
+
+#ifndef _EP9213_ETH_H_
+#define _EP9213_ETH_H_
+
+
+/*---------------------------------------------------------------
+ * Definition of H/W Defects and Their Workarounds
+ *-------------------------------------------------------------*/
+
+
+
+/*---------------------------------------------------------------
+ * Data types used in this driver
+ *-------------------------------------------------------------*/
+typedef unsigned char U8;
+typedef unsigned short U16;
+typedef unsigned long U32;
+typedef unsigned int UINT;
+
+
+
+/*---------------------------------------------------------------
+ * Definition of the registers.
+ * For details, refer to the datasheet .
+ *
+ * Basically, most registers are 32 bits width register.
+ * But some are 16 bits and some are 6 or 8 bytes long.
+ *-------------------------------------------------------------*/
+
+#define REG_RxCTL 0x0000 /*offset to Receiver Control Reg*/
+#define RxCTL_PauseA (1<<20)
+#define RxCTL_RxFCE1 (1<<19)
+#define RxCTL_RxFCE0 (1<<18)
+#define RxCTL_BCRC (1<<17)
+#define RxCTL_SRxON (1<<16)
+#define RxCTL_RCRCA (1<<13)
+#define RxCTL_RA (1<<12)
+#define RxCTL_PA (1<<11)
+#define RxCTL_BA (1<<10)
+#define RxCTL_MA (1<<9)
+#define RxCTL_IAHA (1<<8)
+#define RxCTL_IA3 (1<<3)
+#define RxCTL_IA2 (1<<2)
+#define RxCTL_IA1 (1<<1)
+#define RxCTL_IA0 (1<<0)
+
+#define REG_TxCTL 0x0004 /*offset to Transmit Control Reg*/
+#define TxCTL_DefDis (1<<7)
+#define TxCTL_MBE (1<<6)
+#define TxCTL_ICRC (1<<5)
+#define TxCTL_TxPD (1<<5)
+#define TxCTL_OColl (1<<3)
+#define TxCTL_SP (1<<2)
+#define TxCTL_PB (1<<1)
+#define TxCTL_STxON (1<<0)
+
+#define REG_TestCTL 0x0008 /*Test Control Reg, R/W*/
+#define TestCTL_MACF (1<<7)
+#define TestCTL_MFDX (1<<6)
+#define TestCTL_DB (1<<5)
+#define TestCTL_MIIF (1<<4)
+
+#define REG_MIICmd 0x0010 /*offset to MII Command Reg, R/W*/
+#define MIICmd_OP (0x03<<14)
+#define MIICmd_OP_RD (2<<14)
+#define MIICmd_OP_WR (1<<14)
+#define MIICmd_PHYAD (0x1f<<5)
+#define MIICmd_REGAD (0x1f<<0)
+
+#define REG_MIIData 0x0014 /*offset to MII Data Reg, R/W*/
+#define MIIData_MIIData (0xffff<<0)
+
+#define REG_MIISts 0x0018 /*offset to MII Status Reg, R*/
+#define MIISts_Busy (1<<0)
+
+#define REG_SelfCTL 0x0020 /*offset to Self Control Reg*/
+#define SelfCTL_RWP (1<<7) /*Remote Wake Pin*/
+#define SelfCTL_GPO0 (1<<5)
+#define SelfCTL_PUWE (1<<4)
+#define SelfCTL_PDWE (1<<3)
+#define SelfCTL_MIIL (1<<2)
+#define SelfCTL_RESET (1<<0)
+
+#define REG_IntEn 0x0024 /*Interrupt Enable Reg, R/W*/
+#define IntEn_RWIE (1<<30)
+#define IntEn_RxMIE (1<<29)
+#define IntEn_RxBIE (1<<28)
+#define IntEn_RxSQIE (1<<27)
+#define IntEn_TxLEIE (1<<26)
+#define IntEn_ECIE (1<<25)
+#define IntEn_TxUHIE (1<<24)
+#define IntEn_MOIE (1<<18)
+#define IntEn_TxCOIE (1<<17)
+#define IntEn_RxROIE (1<<16)
+#define IntEn_MIIIE (1<<12)
+#define IntEn_PHYSIE (1<<11)
+#define IntEn_TIE (1<<10)
+#define IntEn_SWIE (1<<8)
+#define IntEn_TxSQIE (1<<3)
+#define IntEn_RxEOFIE (1<<2)
+#define IntEn_RxEOBIE (1<<1)
+#define IntEn_RxHDRIE (1<<0)
+
+#define REG_IntStsP 0x0028 /*offset to Interrupt Status Preserve Reg, R/W*/
+#define REG_IntStsC 0x002c /*offset to Interrupt Status Clear Reg, R*/
+#define IntSts_RWI (1<<30)
+#define IntSts_RxMI (1<<29)
+#define IntSts_RxBI (1<<28)
+#define IntSts_RxSQI (1<<27)
+#define IntSts_TxLEI (1<<26)
+#define IntSts_ECI (1<<25)
+#define IntSts_TxUHI (1<<24)
+#define IntSts_MOI (1<<18)
+#define IntSts_TxCOI (1<<17)
+#define IntSts_RxROI (1<<16)
+#define IntSts_MIII (1<<12)
+#define IntSts_PHYSI (1<<11)
+#define IntSts_TI (1<<10)
+#define IntSts_AHBE (1<<9)
+#define IntSts_SWI (1<<8)
+#define IntSts_OTHER (1<<4)
+#define IntSts_TxSQ (1<<3)
+#define IntSts_RxSQ (1<<2)
+
+#define REG_GT 0x0040 /*offset to General Timer Reg*/
+#define GT_GTC (0xffff<<16)
+#define GT_GTP (0xffff<<0)
+
+#define REG_FCT 0x0044 /*offset to Flow Control Timer Reg*/
+#define FCT_FCT (0x00ffffff<<0)
+
+#define REG_FCF 0x0048 /*offset to Flow Control Format Reg*/
+#define FCF_MACCT (0xffff<<16)
+#define FCF_TPT (0xffff<<0)
+
+#define REG_AFP 0x004c /*offset to Address Filter Pointer Reg*/
+#define AFP_AFP (0x07<<0) /*Address Filter Pointer (bank control for REG_IndAD)*/
+#define AFP_AFP_IA0 0 /*Primary Individual Address (MAC Addr)*/
+#define AFP_AFP_IA1 1 /*Individual Address 1*/
+#define AFP_AFP_IA2 2 /*Individual Address 2*/
+#define AFP_AFP_IA3 3 /*Individual Address 3*/
+#define AFP_AFP_DTxP 6 /*Destination Address of Tx Pause Frame*/
+#define AFP_AFP_HASH 7 /*Hash Table*/
+
+#define REG_IndAD 0x0050 /*offset to Individual Address Reg, n bytes, R/W*/
+
+#define REG_GIntSts 0x0060 /*offset to Global Interrupt Status Reg (writing 1 will clear)*/
+#define REG_GIntROS 0x0068 /*offset to Global Interrupt Status Read Only Reg*/
+#define GIntSts_INT (1<<15) /*Global Interrupt Request Status*/
+
+#define REG_GIntMsk 0x0064 /*offset to Global Interrupt Mask Reg*/
+#define GIntMsk_IntEn (1<<15) /*Global Interrupt Enable*/
+
+#define REG_GIntFrc 0x006c /*offset to Global Interrupt Force Reg*/
+#define GIntFrc_INT (1<<15) /*Force to set GIntSts*/
+
+#define REG_TxCollCnt 0x0070 /*Transmit Collision Count Reg, R*/
+#define REG_RxMissCnt 0x0074 /*Receive Miss Count Reg, R*/
+#define REG_RxRntCnt 0x0078 /*Receive Runt Count Reg, R*/
+
+#define REG_BMCtl 0x0080 /*offset to Bus Master Control Reg, R/W*/
+#define BMCtl_MT (1<<13)
+#define BMCtl_TT (1<<12)
+#define BMCtl_UnH (1<<11)
+#define BMCtl_TxChR (1<<10)
+#define BMCtl_TxDis (1<<9)
+#define BMCtl_TxEn (1<<8)
+#define BMCtl_EH2 (1<<6)
+#define BMCtl_EH1 (1<<5)
+#define BMCtl_EEOB (1<<4)
+#define BMCtl_RxChR (1<<2)
+#define BMCtl_RxDis (1<<1)
+#define BMCtl_RxEn (1<<0)
+
+#define REG_BMSts 0x0084 /*offset to Bus Master Status Reg, R*/
+#define BMSts_TxAct (1<<7)
+#define BMSts_TP (1<<4)
+#define BMSts_RxAct (1<<3)
+#define BMSts_QID (0x07<<0)
+#define BMSts_QID_RxDt (0<<0)
+#define BMSts_QID_TxDt (1<<0)
+#define BMSts_QID_RxSts (2<<0)
+#define BMSts_QID_TxSts (3<<0)
+#define BMSts_QID_RxDesc (4<<0)
+#define BMSts_QID_TxDesc (5<<0)
+
+#define REG_RBCA 0x0088 /*offset to Receive Buffer Current Address Reg, R*/
+#define REG_TBCA 0x008c /*offset to Transmit Buffer Current Address Reg, R*/
+
+#define REG_RxDBA 0x0090 /*offset to Receive Descriptor Queue Base Address Reg, R/W*/
+#define REG_RxDBL 0x0094 /*offset to Receive Descriptor Queue Base Length Reg, R/W, 16bits*/
+#define REG_RxDCL 0x0096 /*offset to Receive Descriptor Queue Current Length Reg, R/W, 16bits*/
+#define REG_RxDCA 0x0098 /*offset to Receive Descriptor Queue Current Address Reg, R/W*/
+
+#define REG_RxDEQ 0x009c /*offset to Receive Descriptor Enqueue Reg, R/W*/
+#define RxDEQ_RDV (0xffff<<16) /*R 16bit; Receive Descriptor Value*/
+#define RxDEQ_RDI (0xff<<0) /*W 8bit; Receive Descriptor Increment*/
+
+#define REG_RxSBA 0x00a0 /*offset to Receive Status Queue Base Address Reg, R/W*/
+#define REG_RxSBL 0x00a4 /*offset to Receive Status Queue Base Length Reg, R/W, 16bits*/
+#define REG_RxSCL 0x00a6 /*offset to Receive Status Queue Current Length Reg, R/W, 16bits*/
+#define REG_RxSCA 0x00a8 /*offset to Receive Status Queue Current Address Reg, R/W*/
+
+#define REG_RxSEQ 0x00ac /*offset to Receive Status Queue Current Address Reg, R/W*/
+#define RxSEQ_RSV (0xffff<<16)
+#define RxSEQ_RSI (0xff<<0)
+
+#define REG_TxDBA 0x00b0 /*offset to Transmit Descriptor Queue Base Address Reg, R/W*/
+#define REG_TxDBL 0x00b4 /*offset to Transmit Descriptor Queue Base Length Reg, R/W, 16bits*/
+#define REG_TxDCL 0x00b6 /*offset to Transmit Descriptor Queue Current Length Reg, R/W, 16bits*/
+#define REG_TxDCA 0x00b8 /*offset to Transmit Descriptor Queue Current Address Reg, R/W*/
+
+#define REG_TxDEQ 0x00bc /*offset to Transmit Descriptor Queue Current Address Reg, R/W*/
+#define TxDEQ_TDV (0xffff<<16)
+#define TxDEQ_TDI (0xff<<0)
+
+#define REG_TxSBA 0x00c0 /*offset to Transmit Status Queue Base Address Reg, R/W*/
+#define REG_TxSBL 0x00c4 /*offset to Transmit Status Queue Base Length Reg, R/W, 16bits*/
+#define REG_TxSCL 0x00c6 /*offset to Transmit Status Queue Current Length Reg, R/W, 16bits*/
+#define REG_TxSCA 0x00c8 /*offset to Transmit Status Queue Current Address Reg, R/W*/
+
+#define REG_RxBTH 0x00d0 /*offset to Receive Buffer Threshold Reg, R/W*/
+#define RxBTH_RDHT (0x03ff<<16)
+#define RxBTH_RDST (0x03ff<<0)
+
+#define REG_TxBTH 0x00d4 /*offset to Transmit Buffer Threshold Reg, R/W*/
+#define TxBTH_TDHT (0x03ff<<16)
+#define TxBTH_TDST (0x03ff<<0)
+
+#define REG_RxSTH 0x00d8 /*offset to Receive Status Threshold Reg, R/W*/
+#define RxSTH_RSHT (0x003f<<16)
+#define RxSTH_RSST (0x003f<<0)
+
+#define REG_TxSTH 0x00dc /*offset to Transmit Status Threshold Reg, R/W*/
+#define TxSTH_TSHT (0x003f<<16)
+#define TxSTH_TSST (0x003f<<0)
+
+#define REG_RxDTH 0x00e0 /*offset to Receive Descriptor Threshold Reg, R/W*/
+#define RxDTH_RDHT (0x003f<<16)
+#define RxDTH_RDST (0x003f<<0)
+
+#define REG_TxDTH 0x00e4 /*offset to Transmit Descriptor Threshold Reg, R/W*/
+#define TxDTH_TDHT (0x003f<<16)
+#define TxDTH_TDST (0x003f<<0)
+
+#define REG_MaxFL 0x00e8 /*offset to Max Frame Length Reg, R/W*/
+#define MaxFL_MFL (0x07ff<<16)
+#define MaxFL_TST (0x07ff<<0)
+
+#define REG_RxHL 0x00ec /*offset to Receive Header Length Reg, R/W*/
+#define RxHL_RHL2 (0x07ff<<16)
+#define RxHL_RHL1 (0x03ff<<0)
+
+#define REG_MACCFG0 0x0100 /*offset to Test Reg #0, R/W*/
+#define MACCFG0_DbgSel (1<<7)
+#define MACCFG0_LCKEN (1<<6)
+#define MACCFG0_LRATE (1<<5)
+#define MACCFG0_RXERR (1<<4)
+#define MACCFG0_BIT33 (1<<2)
+#define MACCFG0_PMEEN (1<<1)
+#define MACCFG0_PMEST (1<<0)
+
+#define REG_MACCFG1 0x0104 /*offset to Test Reg #1, R/W*/
+#define REG_MACCFG2 0x0108 /*offset to Test Reg #2, R*/
+#define REG_MACCFG3 0x010c /*offset to Test Reg #3, R*/
+
+
+
+/*---------------------------------------------------------------
+ * Definition of Descriptor/Status Queue Entry
+ *-------------------------------------------------------------*/
+
+typedef union receiveDescriptor { /*data structure of Receive Descriptor Queue Entry*/
+ struct { /*whole value*/
+ U32 e0, /*1st dword entry*/
+ e1; /*2nd dword entry*/
+ } w;
+ struct { /*bit field definitions*/
+ U32 ba:32, /*Buffer Address (keep in mind this is physical address)*/
+ bl:16, /*b15-0; Buffer Length*/
+ bi:15, /*b30-16; Buffer Index*/
+ nsof:1; /*b31; Not Start Of Frame*/
+ } f;
+} receiveDescriptor;
+
+
+typedef union receiveStatus { /*data structure of Receive Status Queue Entry*/
+ struct { /*whole word*/
+ U32 e0, /*1st dword entry*/
+ e1; /*2nd dword entry*/
+ } w;
+ struct { /*bit field*/
+ U32 rsrv1:8, /*b7-0: reserved*/
+ hti:6, /*b13-8: Hash Table Index*/
+ rsrv2:1, /*b14: reserved*/
+ crci:1, /*b15: CRC Included*/
+ crce:1, /*b16: CRC Error*/
+ edata:1, /*b17: Extra Data*/
+ runt:1, /*b18: Runt Frame*/
+ fe:1, /*b19: Framing Error*/
+ oe:1, /*b20: Overrun Error*/
+ rxerr:1, /*b21: Rx Error*/
+ am:2, /*b23-22: Address Match*/
+ rsrv3:4, /*b27-24: reserved*/
+ eob:1, /*b28: End Of Buffer*/
+ eof:1, /*b29: End Of Frame*/
+ rwe:1, /*b30: Received Without Error*/
+ rfp:1, /*b31: Receive Frame Processed*/
+ fl:16, /*b15-0: frame length*/
+ bi:15, /*b30-16: Buffer Index*/
+ rfp2:1; /*b31: Receive Frame Processed at 2nd word*/
+ } f;
+} receiveStatus;
+
+
+typedef union transmitDescriptor { /*data structure of Transmit Descriptor Queue Entry*/
+ struct { /*whole value*/
+ U32 e0, /*1st dword entry*/
+ e1; /*2nd dword entry*/
+ } w;
+ struct { /*bit field*/
+ U32 ba:32, /*b31-0: Buffer Address (keep in mind this is physical address)*/
+ bl:12, /*b11-0: Buffer Length*/
+ rsrv1:3, /*b14-12: reserved*/
+ af:1, /*b15: Abort Frame*/
+ bi:15, /*b30-16: Buffer Index*/
+ eof:1; /*b31: End Of Frame*/
+
+ } f;
+} transmitDescriptor;
+
+
+typedef union transmitStatus { /*data structure of Transmit Status Queue Entry*/
+ struct { /*whole word*/
+ U32 e0; /*1st dword entry*/
+ } w;
+ struct { /*bit field*/
+ U32 bi:15, /*b14-0: Buffer Index*/
+ rsrv3:1, /*b15: reserved*/
+ ncoll:5, /*b20-16: Number of Collisions*/
+ rsrv2:3, /*b23-21: reserved*/
+ ecoll:1, /*b24: Excess Collisions*/
+ txu:1, /*b25: Tx Underrun*/
+ ow:1, /*b26: Out of Window*/
+ rsrv1:1, /*b27: reserved*/
+ lcrs:1, /*b28: Loss of CRS*/
+ fa:1, /*b29: Frame Abort*/
+ txwe:1, /*b30: Transmitted Without Error*/
+ txfp:1; /*b31: Transmit Frame Processed*/
+ } f;
+} transmitStatus;
+
+
+
+/*---------------------------------------------------------------
+ * Size of device registers occupied in memory/IO address map
+ *-------------------------------------------------------------*/
+#define DEV_REG_SPACE 0x00010000
+
+/*
+#define U8 unsigned char
+#define U16 unsigned short
+#define U32 unsigned long
+*/
+
+/*---------------------------------------------------------------
+ * A definition of register access macros
+ *-------------------------------------------------------------*/
+#define _RegRd(type,ofs) (*(volatile type*)(ofs))
+#define _RegWr(type,ofs,dt) *(volatile type*)(ofs)=((type)(dt))
+
+#define RegRd8(ofs) _RegRd(U8,(char*)pD->base_addr+(ofs))
+#define RegRd16(ofs) _RegRd(U16,(char*)pD->base_addr+(ofs))
+#define RegRd32(ofs) _RegRd(U32,(char*)pD->base_addr+(ofs))
+#define RegWr8(ofs,dt) _RegWr(U8,(char*)pD->base_addr+(ofs),(dt))
+#define RegWr16(ofs,dt) _RegWr(U16,(char*)pD->base_addr+(ofs),(dt))
+#define RegWr32(ofs,dt) _RegWr(U32,(char*)pD->base_addr+(ofs),(dt))
+
+
+
+#endif /* _EP9213_ETH_H_ */
+

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target/linux/ep93xx/patches-2.6.30/008-ep93xx-spi.patch
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Index: linux-2.6.30.9/drivers/spi/Kconfig
===================================================================
--- linux-2.6.30.9.orig/drivers/spi/Kconfig 2009-11-24 21:09:23.000000000 +0100
+++ linux-2.6.30.9/drivers/spi/Kconfig 2009-11-24 21:09:53.000000000 +0100
@@ -125,6 +125,12 @@
If unsure, say N.
+config SPI_EP93XX
+ tristate "EP93xx SSP SPI master"
+ depends on SPI_MASTER && ARCH_EP93XX && EXPERIMENTAL
+ help
+ This enables the EP93xx SPI master controller.
+
config SPI_IMX
tristate "Freescale iMX SPI controller"
depends on ARCH_IMX && EXPERIMENTAL
Index: linux-2.6.30.9/drivers/spi/Makefile
===================================================================
--- linux-2.6.30.9.orig/drivers/spi/Makefile 2009-11-24 21:09:23.000000000 +0100
+++ linux-2.6.30.9/drivers/spi/Makefile 2009-11-24 21:09:53.000000000 +0100
@@ -16,6 +16,7 @@
obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o
obj-$(CONFIG_SPI_AU1550) += au1550_spi.o
obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o
+obj-$(CONFIG_SPI_EP93XX) += spi_ep93xx.o
obj-$(CONFIG_SPI_GPIO) += spi_gpio.o
obj-$(CONFIG_SPI_GPIO_OLD) += spi_gpio_old.o
obj-$(CONFIG_SPI_IMX) += spi_imx.o
Index: linux-2.6.30.9/drivers/spi/spi_ep93xx.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-2.6.30.9/drivers/spi/spi_ep93xx.c 2009-11-24 21:21:25.000000000 +0100
@@ -0,0 +1,680 @@
+/*
+ * linux/drivers/spi/spi_ep93xx.c
+ *
+ * Copyright (C) 2007 Manfred Gruber <m.gruber@tirol.com>
+ * Small changes by Peter Ivanov <ivanovp@gmail.com> to support MMC over SPI, 2008
+ * SIM.ONE changes by Nuccio Raciti Simplemachine <nuccio.raciti@gmail.com>
+ *
+ * Based on pxa2xx_spi.c/spi_imx.c and bitbang.c driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/blkdev.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/workqueue.h>
+
+#include <linux/spi/spi.h>
+
+#include <mach/hardware.h>
+#include <mach/ep93xx-regs.h>
+#include <asm/gpio.h>
+
+/* #define SPI_EP93XX_DEBUG */
+
+#define DEFINE_SSP_REG(reg, off) \
+ static inline u32 read_##reg(void *p) \
+ { return __raw_readl(p + (off)); } \
+ static inline void write_##reg(u32 v, void *p) \
+ { __raw_writel(v, p + (off)); }
+
+DEFINE_SSP_REG(SSPCR0, 0x00)
+DEFINE_SSP_REG(SSPCR1, 0x04)
+DEFINE_SSP_REG(SSPDR, 0x08)
+DEFINE_SSP_REG(SSPSR, 0x0c)
+DEFINE_SSP_REG(SSPCPSR, 0x10)
+DEFINE_SSP_REG(SSPIIR, 0x14)
+DEFINE_SSP_REG(SSPICR, 0x14)
+
+/* Bits in SSPCR0 */
+#define SSPCR0_DSS_MASK 0x0000000f
+#define SSPCR0_FRF_MASK 0x00000030
+#define SSPCR0_FRF_SHIFT 4
+#define SSPCR0_FRF_MOTOROLA (0 << SSPCR0_FRF_SHIFT)
+#define SSPCR0_FRF_TI (1 << SSPCR0_FRF_SHIFT)
+#define SSPCR0_FRF_NI (2 << SSPCR0_FRF_SHIFT)
+#define SSPCR0_SPO 0x00000040
+#define SSPCR0_SPH 0x00000080
+#define SSPCR0_SCR_MASK 0x0000ff00
+#define SSPCR0_SCR_SHIFT 8
+
+/* Bits in SSPCR1 */
+#define SSPC1_RIE 0x00000001
+#define SSPC1_TIE 0x00000002
+#define SSPC1_RORIE 0x00000004
+#define SSPC1_LBM 0x00000008
+#define SSPC1_SSE 0x00000010
+#define SSPC1_MS 0x00000020
+#define SSPC1_SOD 0x00000040
+
+/* Bits in SSPSR */
+#define SSPSR_TFE 0x00000001 /* TX FIFO is empty */
+#define SSPSR_TNF 0x00000002 /* TX FIFO is not full */
+#define SSPSR_RNE 0x00000004 /* RX FIFO is not empty */
+#define SSPSR_RFF 0x00000008 /* RX FIFO is full */
+#define SSPSR_BSY 0x00000010 /* SSP is busy */
+#define SSPSR_MASK 0x0000001F /* SSP is busy */
+
+/* Bits in SSPCPSR */
+#define SSPCPSR_SCR_MASK 0x000000ff
+
+/* Bits in SSPIIR */
+#define SSPIIR_RIS 0x00000001 /* RX FIFO IRQ status */
+#define SSPIIR_TIS 0x00000002 /* TX FIFO is not full */
+#define SSPIIR_RORIS 0x00000004 /* RX FIFO is full */
+
+#define SPI_SSPCLK 7.4e6
+#define SPI_SSPCLK_REV_E2 14.8e6 /* only for chip Rev E2 */
+#define SPI_MAX_SPEED 3.7e6
+#define SPI_MAX_SPEED_REV_E2 7.4e6 /* only for chip Rev E2 */
+#define SPI_CPSDVR_DIV_MIN 2
+#define SPI_CPSDVR_DIV_MAX 254
+#define SPI_SCR_DIV_MIN 0
+#define SPI_SCR_DIV_MAX 255
+#define SPI_DATARATE_OK 0
+#define SPI_DATARATE_NOK -1
+
+struct driver_data {
+ /* Driver model hookup */
+ struct platform_device *pdev;
+
+ /* SPI framework hookup */
+ struct spi_master *master;
+
+ /* SSP register addresses */
+ void *ioaddr;
+
+ /* SSP irq */
+ int irq;
+
+ struct list_head queue;
+
+ /* SSP spinlock */
+ spinlock_t lock;
+
+ struct workqueue_struct *workqueue;
+ struct work_struct work;
+
+ u8 busy;
+ u8 use_dma;
+};
+
+static unsigned ep93xx_txrx_8(struct spi_device *spi, struct spi_transfer *t)
+{
+ struct driver_data *drv_data;
+ const u8 *tx = t->tx_buf;
+ u8 *rx = t->rx_buf;
+ unsigned count = t->len;
+ u8 byte;
+ int busy;
+
+ drv_data = spi_master_get_devdata(spi->master);
+
+#ifdef SPI_EP93XX_DEBUG
+ dev_info(&spi->dev,
+ "ep93xx_txrx_8: t->len %u \n", t->len);
+#endif
+
+ while (likely(count > 0)) {
+ byte = 0;
+ if (tx) {
+ byte = *tx++;
+#ifdef SPI_EP93XX_DEBUG
+ dev_info(&spi->dev,
+ "ep93xx_txrx_8: write 0x%x \n", byte);
+#endif
+ }
+
+ write_SSPDR(byte, drv_data->ioaddr);
+ busy = read_SSPSR(drv_data->ioaddr);
+ while (busy & SSPSR_BSY) {
+ cpu_relax();
+ busy = read_SSPSR(drv_data->ioaddr);
+#ifdef SPI_EP93XX_DEBUG
+ dev_info(&spi->dev,
+ "ep93xx_txrx_8: delay. SSPSR: 0x%X\n", busy);
+#endif
+ }
+ byte = read_SSPDR(drv_data->ioaddr);
+
+ if (rx) {
+ *rx++ = byte;
+#ifdef SPI_EP93XX_DEBUG
+ dev_info(&spi->dev,
+ "ep93xx_txrx_8: read 0x%x \n", byte);
+#endif
+ }
+ count -= 1;
+ }
+ return t->len - count;
+}
+
+
+static unsigned ep93xx_txrx_16(struct spi_device *spi, struct spi_transfer *t)
+{
+
+ struct driver_data *drv_data;
+ const u16 *tx = t->tx_buf;
+ u16 *rx = t->rx_buf;
+ unsigned count = t->len;
+ u16 word;
+ int busy;
+
+ drv_data = spi_master_get_devdata(spi->master);
+
+#ifdef SPI_EP93XX_DEBUG
+ dev_info(&spi->dev,
+ "ep93xx_txrx_16: t->len %u \n", t->len);
+#endif
+ while (likely(count > 0)) {
+ word = 0;
+ if (tx) {
+ word = *tx++;
+#ifdef SPI_EP93XX_DEBUG
+ dev_info(&spi->dev,
+ "ep93xx_txrx_16: write 0x%x \n", word);
+#endif
+ }
+
+ write_SSPDR(word, drv_data->ioaddr);
+ busy = read_SSPSR(drv_data->ioaddr);
+ while (busy & SSPSR_BSY) {
+ cpu_relax();
+ busy = read_SSPSR(drv_data->ioaddr);
+#ifdef SPI_EP93XX_DEBUG
+ dev_info(&spi->dev,
+ "ep93xx_txrx_8: delay.\n");
+#endif
+ }
+
+ word = read_SSPDR(drv_data->ioaddr);
+
+ if (rx) {
+ *rx++ = word;
+#ifdef SPI_EP93XX_DEBUG
+ dev_info(&spi->dev,
+ "ep93xx_txrx_16: read 0x%x \n", word);
+#endif
+ }
+ count -= 2;
+ }
+ return t->len - count;
+}
+
+static u32 spi_data_rate(u32 speed_hz, u32 *div_cpsdvr, u32 *div_scr,
+ struct driver_data *drv_data, struct spi_device *spi)
+{
+ unsigned int spi_sspclk = SPI_SSPCLK;
+ unsigned int bus_speed_max = SPI_MAX_SPEED;
+ unsigned int bus_hz_tmp = 0;
+ u32 div_cpsdvr_tmp;
+ u32 div_scr_tmp;
+ u32 rv = SPI_DATARATE_NOK;
+ int chip_rev;
+
+ /* Checking CHIP_ID */
+ chip_rev = (__raw_readl (EP93XX_SYSCON_CHIP_ID) >> 28) & 0xF;
+ if (chip_rev == 7)
+ {
+ /* Chip version: Rev E2 */
+ /* This device has double speed SSP clock */
+ spi_sspclk = SPI_SSPCLK_REV_E2;
+ bus_speed_max = SPI_MAX_SPEED_REV_E2;
+#ifdef SPI_EP93XX_DEBUG
+ dev_info(&spi->dev,
+ "Chip Rev E2 detected! This device has double speed SSP clock.\n");
+#endif
+ }
+
+ *div_cpsdvr = SPI_CPSDVR_DIV_MAX;
+ *div_scr = SPI_SCR_DIV_MAX;
+
+ for (div_cpsdvr_tmp = SPI_CPSDVR_DIV_MIN;
+ div_cpsdvr_tmp <= SPI_CPSDVR_DIV_MAX && rv; div_cpsdvr_tmp++) {
+ for (div_scr_tmp = SPI_SCR_DIV_MIN;
+ div_scr_tmp <= SPI_SCR_DIV_MAX && rv; div_scr_tmp++) {
+ bus_hz_tmp = spi_sspclk / (div_cpsdvr_tmp * (1 + div_scr_tmp));
+ if (bus_hz_tmp <= speed_hz && bus_hz_tmp <= bus_speed_max) {
+ *div_cpsdvr = div_cpsdvr_tmp;
+ *div_scr = div_scr_tmp;
+ rv = SPI_DATARATE_OK;
+ }
+ }
+ }
+#ifdef SPI_EP93XX_DEBUG
+ dev_info(&spi->dev,
+ "Needed SPI bus frequency: %i Hz\n", speed_hz);
+ dev_info(&spi->dev,
+ "Actual SPI bus frequency: %i Hz\n", bus_hz_tmp);
+#endif
+ return rv;
+}
+
+/* Supported modes (returns -EINVAL if not supported mode requested) */
+#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
+
+static int ep93xx_spi_setup(struct spi_device *spi)
+{
+ struct driver_data *drv_data;
+ u16 val;
+ u32 div_scr;
+ u32 div_cpsdvr;
+ unsigned int bits = spi->bits_per_word;
+ unsigned long speed_hz = spi->max_speed_hz;
+
+ drv_data = spi_master_get_devdata(spi->master);
+
+ /* enable SSP */
+ write_SSPCR1(SSPC1_SSE, drv_data->ioaddr);
+ /* Enable SSP and loopback mode (only for testing!) */
+ /* write_SSPCR1(SSPC1_SSE | SSPC1_LBM, drv_data->ioaddr); */
+
+ if (bits == 0)
+ bits = 8;
+ if (bits < 4 || bits > 16) {
+ dev_err(&spi->dev,
+ "setup invalid bits_per_word %u (4 to 16)\n", bits);
+ return -EINVAL;
+ } else {
+ val = read_SSPCR0(drv_data->ioaddr);
+ val = val & ~SSPCR0_DSS_MASK ;
+ val = val | (bits-1);
+ write_SSPCR0(val, drv_data->ioaddr);
+#ifdef SPI_EP93XX_DEBUG
+ dev_info (&spi->dev, "Bits per word: %i\n", bits);
+#endif
+ }
+
+ if (spi->mode & ~MODEBITS) {
+ dev_err(&spi->dev, "unsupported mode bits: %x\n",
+ spi->mode & ~MODEBITS);
+ return -EINVAL;
+ } else {
+ val = read_SSPCR0(drv_data->ioaddr);
+ val = val & ~SSPCR0_SPO;
+ val = val & ~SSPCR0_SPH;
+ if (spi->mode & SPI_CPOL)
+ {
+ val = val | SSPCR0_SPO;
+ }
+#ifdef SPI_EP93XX_DEBUG
+ dev_info (&spi->dev, "Clock polarity (CPOL): %s\n", (spi->mode & SPI_CPHA) ? "1" : "0");
+#endif
+ if (spi->mode & SPI_CPHA)
+ {
+ val = val | SSPCR0_SPH;
+ }
+#ifdef SPI_EP93XX_DEBUG
+ dev_info (&spi->dev, "Clock phase (CPHA): %s\n", (spi->mode & SPI_CPHA) ? "1" : "0");
+#endif
+ write_SSPCR0(val, drv_data->ioaddr);
+ }
+
+ if (SPI_DATARATE_OK == (spi_data_rate(speed_hz, &div_cpsdvr,
+ &div_scr, drv_data, spi))) {
+
+ val = read_SSPCPSR(drv_data->ioaddr);
+ val = val & ~SSPCPSR_SCR_MASK;
+ val = val | div_cpsdvr;
+#ifdef SPI_EP93XX_DEBUG
+ dev_info (&spi->dev, "SSPCPSR: 0x%X\n", val);
+#endif
+ write_SSPCPSR(val, drv_data->ioaddr);
+
+ val = read_SSPCR0(drv_data->ioaddr);
+ val = val & ~SSPCR0_SCR_MASK;
+ val = val | (div_scr << SSPCR0_SCR_SHIFT);
+#ifdef SPI_EP93XX_DEBUG
+ dev_info (&spi->dev, "SSPCR0: 0x%X (div_scr: 0x%X)\n", val, div_scr);
+#endif
+ write_SSPCR0(val, drv_data->ioaddr);
+ } else
+ return -EINVAL;
+
+ /* reenable */
+ val = read_SSPCR1(drv_data->ioaddr);
+ val = val & ~SSPC1_SSE;
+ write_SSPCR1(val, drv_data->ioaddr);
+ val = read_SSPCR1(drv_data->ioaddr);
+ val = val | SSPC1_SSE;
+ write_SSPCR1(val, drv_data->ioaddr);
+#ifdef SPI_EP93XX_DEBUG
+ dev_info (&spi->dev, "Loopback mode: %s\n", (val & SSPC1_LBM) ? "On" : "Off");
+#endif
+
+ return 0;
+}
+
+static int ep93xx_spi_transfer(struct spi_device *spi, struct spi_message *m)
+{
+ struct driver_data *drv_data;
+ unsigned long flags;
+ int status = 0;
+
+ m->actual_length = 0;
+ m->status = -EINPROGRESS;
+
+ drv_data = spi_master_get_devdata(spi->master);
+
+ spin_lock_irqsave(&drv_data->lock, flags);
+ if (!spi->max_speed_hz)
+ status = -ENETDOWN;
+ else {
+ list_add_tail(&m->queue, &drv_data->queue);
+ queue_work(drv_data->workqueue, &drv_data->work);
+ }
+ spin_unlock_irqrestore(&drv_data->lock, flags);
+ return status;
+}
+
+static void ep93xx_work(struct work_struct *work)
+{
+ struct driver_data *drv_data =
+ container_of(work, struct driver_data, work);
+ unsigned long flags;
+
+ spin_lock_irqsave(&drv_data->lock, flags);
+ drv_data->busy = 1;
+
+ while (!list_empty(&drv_data->queue)) {
+ struct spi_message *m;
+ struct spi_device *spi;
+ struct spi_transfer *t = NULL;
+ int status;
+
+ m = container_of(drv_data->queue.next, struct spi_message,
+ queue);
+ list_del_init(&m->queue);
+ spin_unlock_irqrestore(&drv_data->lock, flags);
+
+ spi = m->spi;
+ status = 0;
+
+ list_for_each_entry(t, &m->transfers, transfer_list) {
+
+ if (!t->tx_buf && !t->rx_buf && t->len) {
+ status = -EINVAL;
+ break;
+ }
+
+ if (t->len) {
+ if (!m->is_dma_mapped) {
+ t->rx_dma = 0;
+ t->tx_dma = 0;
+ }
+ if (t->bits_per_word <= 8)
+ status = ep93xx_txrx_8(spi, t);
+ else
+ status = ep93xx_txrx_16(spi, t);
+ }
+
+ if (status != t->len) {
+ if (status > 0)
+ status = -EMSGSIZE;
+ break;
+ }
+ m->actual_length += status;
+ status = 0;
+
+ /* protocol tweaks before next transfer */
+ if (t->delay_usecs)
+ udelay(t->delay_usecs);
+
+ if (t->transfer_list.next == &m->transfers)
+ break;
+ }
+
+ m->status = status;
+ m->complete(m->context);
+
+ spin_lock_irqsave(&drv_data->lock, flags);
+ }
+ drv_data->busy = 0;
+ spin_unlock_irqrestore(&drv_data->lock, flags);
+}
+
+static irqreturn_t ssp_int(int irq, void *dev_id)
+{
+ struct driver_data *drv_data = dev_id;
+ u8 status;
+ status = read_SSPIIR(drv_data->ioaddr);
+
+ if (status & SSPIIR_RORIS) {
+ dev_err(&drv_data->pdev->dev, "SPI rx overrun.\n");
+
+ /* We clear the overrun here ! */
+ write_SSPICR(0, drv_data->ioaddr);
+ }
+
+ /* RX interrupt */
+ if (status & SSPIIR_RIS)
+ dev_info(&drv_data->pdev->dev, "SPI RX interrupt\n");
+
+ /* TX interrupt */
+ if (status & SSPIIR_TIS)
+ dev_info(&drv_data->pdev->dev, "SPI TX interrupt\n");
+
+ write_SSPICR(0, drv_data->ioaddr);
+ return IRQ_HANDLED;
+}
+
+static int __init ep93xx_spi_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct spi_master *master;
+ struct driver_data *drv_data = 0;
+ struct resource *memory_resource;
+ int status = 0;
+ u16 val;
+
+ /* Allocate master with space for drv_data and null dma buffer */
+ master = spi_alloc_master(dev, sizeof(struct driver_data));
+ if (!master) {
+ dev_err(&pdev->dev, "cannot alloc spi_master\n");
+ return -ENOMEM;
+ }
+ drv_data = spi_master_get_devdata(master);
+ drv_data->master = master;
+ drv_data->pdev = pdev;
+
+ master->num_chipselect = EP93XX_GPIO_LINE_H(7) + 1;
+ master->bus_num = pdev->id;
+ master->setup = ep93xx_spi_setup;
+ master->transfer = ep93xx_spi_transfer;
+
+ spin_lock_init(&drv_data->lock);
+ INIT_LIST_HEAD(&drv_data->queue);
+
+ /* Setup register addresses */
+ memory_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!memory_resource) {
+ dev_err(&pdev->dev, "memory resources not defined\n");
+ status = -EIO;
+ goto out_error_master_alloc;
+ } else {
+ drv_data->ioaddr = ioremap(memory_resource->start,
+ memory_resource->end - memory_resource->start);
+ if (drv_data->ioaddr == NULL) {
+ dev_err(&pdev->dev, "ioremap failed\n");
+ status = -EIO;
+ goto out_error_master_alloc;
+ }
+ }
+
+ /* Attach to IRQ */
+ drv_data->irq = platform_get_irq(pdev, 0);
+ if (drv_data->irq < 0)
+ return drv_data->irq;
+
+ if (drv_data->irq <= 0) {
+ dev_err(&pdev->dev, "IRQ resource not defined\n");
+ status = -ENODEV;
+ goto out_error_master_alloc;
+ }
+
+ status = request_irq(drv_data->irq, ssp_int, 0, "ep93xx-spi", drv_data);
+ if (status < 0) {
+ dev_err(&pdev->dev, "cannot get SPI IRQ 0\n");
+ goto out_error_master_alloc;
+ }
+
+ /* SSP default configuration, enable */
+ write_SSPCR1(SSPC1_SSE, drv_data->ioaddr);
+
+ /* run as master */
+ val = read_SSPCR1(drv_data->ioaddr);
+ val = val & ~SSPC1_MS;
+ write_SSPCR1(val, drv_data->ioaddr);
+
+ /* frame format to Motorola SPI Format */
+ val = read_SSPCR0(drv_data->ioaddr);
+ val = val & ~SSPCR0_FRF_MASK ;
+ val = val | SSPCR0_FRF_MOTOROLA;
+ write_SSPCR0(val, drv_data->ioaddr);
+
+ /* enable interrupts */
+ val = read_SSPCR1(drv_data->ioaddr);
+ /* for now only overrun is handled */
+ /* val = val | SSPC1_RIE | SSPC1_TIE | SSPC1_RORIE; */
+ val = val | SSPC1_RORIE;
+ write_SSPCR1(val, drv_data->ioaddr);
+
+ /* SSP default configuration, re enable */
+ val = read_SSPCR1(drv_data->ioaddr);
+ val = val & ~SSPC1_SSE;
+ write_SSPCR1(val, drv_data->ioaddr);
+ val = read_SSPCR1(drv_data->ioaddr);
+ val = val | SSPC1_SSE;
+ write_SSPCR1(val, drv_data->ioaddr);
+
+ /* Register with the SPI framework */
+ platform_set_drvdata(pdev, drv_data);
+ status = spi_register_master(master);
+ if (status != 0) {
+ dev_err(&pdev->dev, "cannot register SPI master\n");
+ goto out_error_master_alloc;
+ } else
+ dev_info(&pdev->dev, "SPI Controller initalized\n");
+
+ INIT_WORK(&drv_data->work, ep93xx_work);
+ spin_lock_init(&drv_data->lock);
+ INIT_LIST_HEAD(&drv_data->queue);
+
+ /* this task is the only thing to touch the SPI bits */
+ drv_data->busy = 0;
+ drv_data->workqueue = create_singlethread_workqueue(
+ dev_name(drv_data->master->dev.parent));
+/* drv_data->master->cdev.dev->bus_id); */
+ if (drv_data->workqueue == NULL) {
+ status = -EBUSY;
+ goto out_error_free_irq;
+ }
+
+ return status;
+
+out_error_free_irq:
+ free_irq(drv_data->irq, master);
+out_error_master_alloc:
+ if (drv_data->ioaddr != NULL)
+ iounmap(drv_data->ioaddr);
+ spi_master_put(master);
+ return status;
+}
+
+static int __exit ep93xx_spi_remove(struct platform_device *pdev)
+{
+ struct driver_data *drv_data = platform_get_drvdata(pdev);
+ u8 val;
+
+ WARN_ON(!list_empty(&drv_data->queue));
+
+ destroy_workqueue(drv_data->workqueue);
+
+ /* switch off SSP*/
+ val = read_SSPCR1(drv_data->ioaddr);
+ val = val & ~SSPC1_SSE;
+ write_SSPCR1(val, drv_data->ioaddr);
+
+ /* release irqs */
+ if (drv_data->irq > 0)
+ free_irq(drv_data->irq, drv_data);
+
+ /* Disconnect from the SPI framework */
+ spi_unregister_master(drv_data->master);
+ spi_master_put(drv_data->master);
+
+ if (drv_data->ioaddr != NULL)
+ iounmap(drv_data->ioaddr);
+
+ /* Prevent double remove */
+ platform_set_drvdata(pdev, NULL);
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int ep93xx_spi_suspend(struct platform_device *pdev, pm_message_t msg)
+{
+ return 0;
+}
+
+static int ep93xx_spi_resume(struct platform_device *pdev)
+{
+ return 0;
+}
+
+#else
+#define ep93xx_spi_suspend NULL
+#define ep93xx_spi_resume NULL
+#endif
+
+struct platform_driver ep93xx_spi_device = {
+ .remove = __exit_p(ep93xx_spi_remove),
+#ifdef CONFIG_PM
+ .suspend = ep93xx_spi_suspend,
+ .resume = ep93xx_spi_resume,
+#endif
+ .driver = {
+ .name = "ep93xx-spi",
+ .bus = &spi_bus_type,
+ .owner = THIS_MODULE,
+ },
+};
+
+int __init ep93xx_spi_init(void)
+{
+ return platform_driver_probe(&ep93xx_spi_device, ep93xx_spi_probe);
+}
+
+void __exit ep93xx_spi_exit(void)
+{
+ platform_driver_unregister(&ep93xx_spi_device);
+}
+
+module_init(ep93xx_spi_init);
+module_exit(ep93xx_spi_exit);
+
+MODULE_DESCRIPTION("EP93XX SPI Driver");
+MODULE_AUTHOR("Manfred Gruber, <m.gruber@tirol.com>");
+MODULE_LICENSE("GPL");

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target/linux/ep93xx/patches-2.6.30/009-ep93xx-fb.patch
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target/linux/ep93xx/patches-2.6.30/010-ep93xx-snd-ac97.patch
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target/linux/ep93xx/patches-2.6.30/011-simone-board-def.patch
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target/linux/ep93xx/patches-2.6.30/012-ep93xx-cpuinfo.patch
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@ -0,0 +1,32 @@
Index: linux-2.6.30.9/arch/arm/kernel/setup.c
===================================================================
--- linux-2.6.30.9.orig/arch/arm/kernel/setup.c 2009-11-24 21:00:10.000000000 +0100
+++ linux-2.6.30.9/arch/arm/kernel/setup.c 2009-11-24 21:00:46.000000000 +0100
@@ -42,6 +42,10 @@
#include <asm/traps.h>
#include <asm/unwind.h>
+#if defined(CONFIG_ARCH_EP93XX)
+#include <mach/ep93xx-regs.h>
+#endif
+
#include "compat.h"
#include "atags.h"
@@ -844,9 +848,16 @@
seq_puts(m, "\n");
seq_printf(m, "Hardware\t: %s\n", machine_name);
+#if defined(CONFIG_ARCH_EP93XX)
+ seq_printf(m, "Revision\t: %04x\n",
+ *((unsigned int *)EP93XX_SYSCON_CHIP_ID) >> 28);
+ seq_printf(m, "Serial\t\t: %016x\n",
+ *((unsigned int *)EP93XX_SECURITY_UNIQID));
+#else
seq_printf(m, "Revision\t: %04x\n", system_rev);
seq_printf(m, "Serial\t\t: %08x%08x\n",
system_serial_high, system_serial_low);
+#endif
return 0;
}
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