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ar8216: Fix problem with AR8337 MAC swap handling

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AR8337 supports a configuration bit to swap MAC0 and MAC6.
Currently this is set in general if an AR8337 is detected and causes
issues with devices using an AR8334 (internally an AR8337, just
less chip pins).
And it might even cause issues with AR8337-based devices with
different board designs.

Swapping the MAC's however isn't needed for AR8337 in general.
It's just needed in case of certain board designs (affected devices
seem to be based on Atheros reference board AP135/136-010).
Therefore this configuration bit should be moved to platform data.

The patch includes the needed changes to the device initialization
code of affected devices. Hopefully I didn't miss any ..

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>

SVN-Revision: 45970
v19.07.3_mercusys_ac12_duma
Felix Fietkau 9 years ago
parent b98fb76646
commit 4a9d726200
6 changed files with 10 additions and 4 deletions
Show Stats Download Patch File Download Diff File

1
target/linux/ar71xx/files/arch/mips/ath79/mach-esr1750.c
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@ -97,6 +97,7 @@ static struct ar8327_pad_cfg esr1750_ar8327_pad0_cfg = {
.rxclk_delay_en = true,
.txclk_delay_sel = AR8327_CLK_DELAY_SEL2,
.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
.mac06_exchange_en = true,
};
static struct ar8327_platform_data esr1750_ar8327_data = {

1
target/linux/ar71xx/files/arch/mips/ath79/mach-f9k1115v2.c
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@ -98,6 +98,7 @@ static struct ar8327_pad_cfg f9k1115v2_ar8327_pad0_cfg = {
.rxclk_delay_en = true,
.txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
.mac06_exchange_en = true,
};
static struct ar8327_pad_cfg f9k1115v2_ar8327_pad6_cfg = {

1
target/linux/ar71xx/files/arch/mips/ath79/mach-nbg6716.c
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@ -251,6 +251,7 @@ static void __init nbg6716_010_setup(void)
nbg6716_ar8327_pad0_cfg.rxclk_delay_en = true;
nbg6716_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
nbg6716_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
nbg6716_ar8327_pad0_cfg.mac06_exchange_en = true;
/* GMAC6 of the AR8337 switch is connected to GMAC1 via SGMII */
nbg6716_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII;

1
target/linux/ar71xx/files/arch/mips/ath79/mach-wlr8100.c
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@ -186,6 +186,7 @@ static void __init wlr8100_010_setup(void)
wlr8100_ar8327_pad0_cfg.rxclk_delay_en = true;
wlr8100_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
wlr8100_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
wlr8100_ar8327_pad0_cfg.mac06_exchange_en = true;
/* GMAC6 of the AR8337 switch is connected to GMAC1 via SGMII */
wlr8100_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII;

6
target/linux/generic/files/drivers/net/phy/ar8327.c
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@ -124,6 +124,9 @@ ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
break;
}
if (cfg->mac06_exchange_en)
t |= AR8337_PAD_MAC06_EXCHANGE_EN;
return t;
}
@ -508,9 +511,6 @@ ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
t = ar8327_get_pad_cfg(pdata->pad0_cfg);
if (chip_is_ar8337(priv))
t |= AR8337_PAD_MAC06_EXCHANGE_EN;
ar8xxx_write(priv, AR8327_REG_PAD0_MODE, t);
t = ar8327_get_pad_cfg(pdata->pad5_cfg);
ar8xxx_write(priv, AR8327_REG_PAD5_MODE, t);

4
target/linux/generic/files/include/linux/ar8216_platform.h
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@ -47,6 +47,7 @@ struct ar8327_pad_cfg {
bool sgmii_delay_en;
enum ar8327_clk_delay_sel txclk_delay_sel;
enum ar8327_clk_delay_sel rxclk_delay_sel;
bool mac06_exchange_en;
};
enum ar8327_port_speed {
@ -128,4 +129,5 @@ struct ar8327_platform_data {
const struct ar8327_led_info *leds;
};
#endif /* AR8216_PLATFORM_H */
#endif /* AR8216_PLATFORM_H */

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