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@ -15,59 +15,59 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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@@ -35,6 +35,24 @@
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bias-disable;
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};
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+ pcie0_pins: pcie0_pinmux {
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+ mux {
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+ pins = "gpio3";
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+ function = "pcie1_rst";
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+ drive-strength = <12>;
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+ bias-disable;
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+ };
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+ };
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+
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+ pcie1_pins: pcie1_pinmux {
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+ mux {
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+ pins = "gpio48";
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+ function = "pcie2_rst";
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+ drive-strength = <12>;
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+ bias-disable;
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+ };
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+ };
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+
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spi_pins: spi_pins {
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mux {
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pins = "gpio18", "gpio19", "gpio21";
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@@ -91,5 +109,21 @@
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@@ -91,5 +91,15 @@
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sata@29000000 {
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status = "ok";
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};
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+
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+ pcie0: pci@1b500000 {
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+ status = "ok";
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+ reset-gpio = <&qcom_pinmux 3 0>;
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+ pinctrl-0 = <&pcie0_pins>;
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+ pinctrl-names = "default";
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+ phy-tx0-term-offset = <7>;
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+ };
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+
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+ pcie1: pci@1b700000 {
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+ status = "ok";
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+ reset-gpio = <&qcom_pinmux 48 0>;
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+ pinctrl-0 = <&pcie1_pins>;
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+ pinctrl-names = "default";
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+ phy-tx0-term-offset = <7>;
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+ };
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};
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};
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--- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
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@@ -30,6 +30,33 @@
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bias-disable;
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};
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@@ -128,5 +128,17 @@
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usb30@1 {
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status = "ok";
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};
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+
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+ pcie0: pci@1b500000 {
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+ status = "ok";
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+ };
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+
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+ pcie1: pci@1b700000 {
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+ status = "ok";
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+ };
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+
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+ pcie2: pci@1b900000 {
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+ status = "ok";
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+ };
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};
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};
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -4,6 +4,9 @@
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#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
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#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
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#include <dt-bindings/soc/qcom,gsbi.h>
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+#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Qualcomm IPQ8064";
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@@ -99,6 +102,33 @@
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 16 0x4>;
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+
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+ pcie0_pins: pcie0_pinmux {
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+ mux {
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+ pins = "gpio3";
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@ -94,49 +94,10 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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+ bias-disable;
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+ };
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+ };
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+
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spi_pins: spi_pins {
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mux {
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pins = "gpio18", "gpio19", "gpio21";
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@@ -128,5 +155,26 @@
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usb30@1 {
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status = "ok";
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};
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+
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+ pcie0: pci@1b500000 {
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+ status = "ok";
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+ reset-gpio = <&qcom_pinmux 3 0>;
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+ pinctrl-0 = <&pcie0_pins>;
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+ pinctrl-names = "default";
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+ };
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+
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+ pcie1: pci@1b700000 {
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+ status = "ok";
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+ reset-gpio = <&qcom_pinmux 48 0>;
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+ pinctrl-0 = <&pcie1_pins>;
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+ pinctrl-names = "default";
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+ };
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+
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+ pcie2: pci@1b900000 {
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+ status = "ok";
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+ reset-gpio = <&qcom_pinmux 63 0>;
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+ pinctrl-0 = <&pcie2_pins>;
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+ pinctrl-names = "default";
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+ };
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};
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};
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -4,6 +4,8 @@
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#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
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#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
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#include <dt-bindings/soc/qcom,gsbi.h>
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+#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Qualcomm IPQ8064";
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@@ -333,6 +335,129 @@
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intc: interrupt-controller@2000000 {
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@@ -333,6 +363,144 @@
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compatible = "syscon";
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reg = <0x01200600 0x100>;
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};
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@ -179,6 +140,11 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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+ <&gcc PCIE_PHY_RESET>;
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+ reset-names = "axi", "ahb", "por", "pci", "phy";
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+
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+ pinctrl-0 = <&pcie0_pins>;
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+ pinctrl-names = "default";
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+
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+ perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
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+
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+ status = "disabled";
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+ };
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+
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@ -220,6 +186,11 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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+ <&gcc PCIE_1_PHY_RESET>;
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+ reset-names = "axi", "ahb", "por", "pci", "phy";
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+
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+ pinctrl-0 = <&pcie1_pins>;
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+ pinctrl-names = "default";
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+
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+ perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
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+
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+ status = "disabled";
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+ };
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+
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@ -261,6 +232,11 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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+ <&gcc PCIE_2_PHY_RESET>;
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+ reset-names = "axi", "ahb", "por", "pci", "phy";
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+
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+ pinctrl-0 = <&pcie2_pins>;
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+ pinctrl-names = "default";
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+
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+ perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
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+
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+ status = "disabled";
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+ };
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};
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Felix Fietkau
9 years ago