ipq806x: drop old cpufreq patch
Drop old cpufreq as now we have new driver that can use normal kernel opp definition Tested-by: Stefan Lippers-Hollmann <s.l-h@gmx.de> [nbg6817/ipq8065] Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>master
Ansuel Smith
4 years ago
committed by
Petr Štetiar
parent
e9a982e1d9
commit
4165f2340e
@ -1,307 +0,0 @@
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From patchwork Fri Dec 8 09:42:29 2017
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [v4,11/12] cpufreq: Add module to register cpufreq on Krait CPUs
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From: Sricharan R <sricharan@codeaurora.org>
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X-Patchwork-Id: 10102075
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Message-Id: <1512726150-7204-12-git-send-email-sricharan@codeaurora.org>
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To: mturquette@baylibre.com, sboyd@codeaurora.org,
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devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
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linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
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viresh.kumar@linaro.org, linux-arm-kernel@lists.infradead.org
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Cc: sricharan@codeaurora.org
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Date: Fri, 8 Dec 2017 15:12:29 +0530
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From: Stephen Boyd <sboyd@codeaurora.org>
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Register a cpufreq-generic device whenever we detect that a
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"qcom,krait" compatible CPU is present in DT.
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Cc: <devicetree@vger.kernel.org>
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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---
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.../devicetree/bindings/arm/msm/qcom,pvs.txt | 38 ++++
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drivers/cpufreq/Kconfig.arm | 9 +
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drivers/cpufreq/Makefile | 1 +
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drivers/cpufreq/qcom-cpufreq.c | 204 +++++++++++++++++++++
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4 files changed, 252 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,pvs.txt
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create mode 100644 drivers/cpufreq/qcom-cpufreq.c
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/arm/msm/qcom,pvs.txt
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@@ -0,0 +1,38 @@
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+Qualcomm Process Voltage Scaling Tables
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+
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+The node name is required to be "qcom,pvs". There shall only be one
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+such node present in the root of the tree.
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+
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+PROPERTIES
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+
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+- qcom,pvs-format-a or qcom,pvs-format-b:
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+ Usage: required
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+ Value type: <empty>
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+ Definition: Indicates the format of qcom,speedX-pvsY-bin-vZ properties.
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+ If qcom,pvs-format-a is used the table is two columns
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+ (frequency and voltage in that order). If qcom,pvs-format-b is used the table is three columns (frequency, voltage,
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+ and current in that order).
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+
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+- qcom,speedX-pvsY-bin-vZ:
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+ Usage: required
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+ Value type: <prop-encoded-array>
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+ Definition: The PVS table corresponding to the speed bin X, pvs bin Y,
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+ and version Z.
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+Example:
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+
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+ qcom,pvs {
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+ qcom,pvs-format-a;
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+ qcom,speed0-pvs0-bin-v0 =
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+ < 384000000 950000 >,
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+ < 486000000 975000 >,
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+ < 594000000 1000000 >,
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+ < 702000000 1025000 >,
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+ < 810000000 1075000 >,
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+ < 918000000 1100000 >,
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+ < 1026000000 1125000 >,
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+ < 1134000000 1175000 >,
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+ < 1242000000 1200000 >,
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+ < 1350000000 1225000 >,
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+ < 1458000000 1237500 >,
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+ < 1512000000 1250000 >;
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+ };
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--- a/drivers/cpufreq/Kconfig.arm
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+++ b/drivers/cpufreq/Kconfig.arm
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@@ -121,6 +121,15 @@ config ARM_QCOM_CPUFREQ_KRYO
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If in doubt, say N.
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+config ARM_QCOM_CPUFREQ
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+ tristate "Qualcomm based"
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+ depends on ARCH_QCOM
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+ select PM_OPP
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+ help
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+ This adds the CPUFreq driver for Qualcomm SoC based boards.
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+
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+ If in doubt, say N.
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+
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config ARM_S3C_CPUFREQ
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bool
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help
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--- a/drivers/cpufreq/Makefile
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+++ b/drivers/cpufreq/Makefile
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@@ -64,6 +64,7 @@ obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cp
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obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o
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obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o
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obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o
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+obj-$(CONFIG_ARM_QCOM_CPUFREQ) += qcom-cpufreq.o
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obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRYO) += qcom-cpufreq-kryo.o
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obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o
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obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o
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--- /dev/null
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+++ b/drivers/cpufreq/qcom-cpufreq.c
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@@ -0,0 +1,204 @@
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+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 and
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+ * only version 2 as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <linux/cpu.h>
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+#include <linux/err.h>
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+#include <linux/init.h>
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+#include <linux/io.h>
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/of.h>
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+#include <linux/platform_device.h>
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+#include <linux/pm_opp.h>
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+#include <linux/slab.h>
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+#include "cpufreq-dt.h"
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+
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+static void __init get_krait_bin_format_a(int *speed, int *pvs, int *pvs_ver)
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+{
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+ void __iomem *base;
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+ u32 pte_efuse;
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+
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+ *speed = *pvs = *pvs_ver = 0;
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+
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+ base = ioremap(0x007000c0, 4);
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+ if (!base) {
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+ pr_warn("Unable to read efuse data. Defaulting to 0!\n");
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+ return;
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+ }
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+
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+ pte_efuse = readl_relaxed(base);
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+ iounmap(base);
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+
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+ *speed = pte_efuse & 0xf;
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+ if (*speed == 0xf)
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+ *speed = (pte_efuse >> 4) & 0xf;
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+
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+ if (*speed == 0xf) {
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+ *speed = 0;
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+ pr_warn("Speed bin: Defaulting to %d\n", *speed);
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+ } else {
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+ pr_info("Speed bin: %d\n", *speed);
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+ }
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+
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+ *pvs = (pte_efuse >> 10) & 0x7;
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+ if (*pvs == 0x7)
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+ *pvs = (pte_efuse >> 13) & 0x7;
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+
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+ if (*pvs == 0x7) {
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+ *pvs = 0;
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+ pr_warn("PVS bin: Defaulting to %d\n", *pvs);
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+ } else {
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+ pr_info("PVS bin: %d\n", *pvs);
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+ }
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+}
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+
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+static void __init get_krait_bin_format_b(int *speed, int *pvs, int *pvs_ver)
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+{
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+ u32 pte_efuse, redundant_sel;
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+ void __iomem *base;
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+
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+ *speed = 0;
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+ *pvs = 0;
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+ *pvs_ver = 0;
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+
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+ base = ioremap(0xfc4b80b0, 8);
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+ if (!base) {
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+ pr_warn("Unable to read efuse data. Defaulting to 0!\n");
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+ return;
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+ }
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+
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+ pte_efuse = readl_relaxed(base);
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+ redundant_sel = (pte_efuse >> 24) & 0x7;
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+ *speed = pte_efuse & 0x7;
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+ /* 4 bits of PVS are in efuse register bits 31, 8-6. */
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+ *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
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+ *pvs_ver = (pte_efuse >> 4) & 0x3;
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+
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+ switch (redundant_sel) {
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+ case 1:
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+ *speed = (pte_efuse >> 27) & 0xf;
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+ break;
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+ case 2:
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+ *pvs = (pte_efuse >> 27) & 0xf;
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+ break;
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+ }
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+
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+ /* Check SPEED_BIN_BLOW_STATUS */
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+ if (pte_efuse & BIT(3)) {
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+ pr_info("Speed bin: %d\n", *speed);
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+ } else {
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+ pr_warn("Speed bin not set. Defaulting to 0!\n");
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+ *speed = 0;
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+ }
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+
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+ /* Check PVS_BLOW_STATUS */
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+ pte_efuse = readl_relaxed(base + 0x4) & BIT(21);
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+ if (pte_efuse) {
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+ pr_info("PVS bin: %d\n", *pvs);
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+ } else {
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+ pr_warn("PVS bin not set. Defaulting to 0!\n");
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+ *pvs = 0;
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+ }
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+
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+ pr_info("PVS version: %d\n", *pvs_ver);
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+ iounmap(base);
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+}
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+
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+static int __init qcom_cpufreq_populate_opps(void)
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+{
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+ int len, rows, cols, i, k, speed, pvs, pvs_ver;
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+ char table_name[] = "qcom,speedXX-pvsXX-bin-vXX";
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+ struct device_node *np;
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+ struct device *dev;
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+ int cpu = 0;
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+
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+ np = of_find_node_by_name(NULL, "qcom,pvs");
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+ if (!np)
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+ return -ENODEV;
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+
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+ if (of_property_read_bool(np, "qcom,pvs-format-a")) {
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+ get_krait_bin_format_a(&speed, &pvs, &pvs_ver);
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+ cols = 2;
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+ } else if (of_property_read_bool(np, "qcom,pvs-format-b")) {
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+ get_krait_bin_format_b(&speed, &pvs, &pvs_ver);
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+ cols = 3;
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+ } else {
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+ return -ENODEV;
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+ }
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+
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+ snprintf(table_name, sizeof(table_name),
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+ "qcom,speed%d-pvs%d-bin-v%d", speed, pvs, pvs_ver);
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+
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+ if (!of_find_property(np, table_name, &len))
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+ return -EINVAL;
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+
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+ len /= sizeof(u32);
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+ if (len % cols || len == 0)
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+ return -EINVAL;
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+
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+ rows = len / cols;
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+
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+ for (i = 0, k = 0; i < rows; i++) {
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+ u32 freq, volt;
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+
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+ of_property_read_u32_index(np, table_name, k++, &freq);
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+ of_property_read_u32_index(np, table_name, k++, &volt);
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+ while (k % cols)
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+ k++; /* Skip uA entries if present */
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+ for (cpu = 0; cpu < num_possible_cpus(); cpu++) {
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+ dev = get_cpu_device(cpu);
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+ if (!dev)
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+ return -ENODEV;
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+ if (dev_pm_opp_add(dev, freq, volt))
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+ pr_warn("failed to add OPP %u\n", freq);
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+ }
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+ }
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+
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+ return 0;
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+}
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+
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+static int __init qcom_cpufreq_driver_init(void)
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+{
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+ struct cpufreq_dt_platform_data pdata = { .independent_clocks = true };
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+ struct platform_device_info devinfo = {
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+ .name = "cpufreq-dt",
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+ .data = &pdata,
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+ .size_data = sizeof(pdata),
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+ };
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+ struct device *cpu_dev;
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+ struct device_node *np;
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+ int ret;
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+
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+ cpu_dev = get_cpu_device(0);
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+ if (!cpu_dev)
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+ return -ENODEV;
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+
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+ np = of_node_get(cpu_dev->of_node);
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+ if (!np)
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+ return -ENOENT;
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+
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+ if (!of_device_is_compatible(np, "qcom,krait")) {
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+ of_node_put(np);
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+ return -ENODEV;
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+ }
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+ of_node_put(np);
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+
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+ ret = qcom_cpufreq_populate_opps();
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+ if (ret)
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+ return ret;
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+
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+ return PTR_ERR_OR_ZERO(platform_device_register_full(&devinfo));
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+}
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+module_init(qcom_cpufreq_driver_init);
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+
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+MODULE_DESCRIPTION("Qualcomm CPUfreq driver");
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+MODULE_LICENSE("GPL v2");
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@ -1,66 +0,0 @@
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From patchwork Fri Dec 8 09:42:30 2017
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [v4,12/12] cpufreq: dt: Reintroduce independent_clocks platform data
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From: Sricharan R <sricharan@codeaurora.org>
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X-Patchwork-Id: 10102073
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Message-Id: <1512726150-7204-13-git-send-email-sricharan@codeaurora.org>
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To: mturquette@baylibre.com, sboyd@codeaurora.org,
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devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
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linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
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viresh.kumar@linaro.org, linux-arm-kernel@lists.infradead.org
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Cc: sricharan@codeaurora.org
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Date: Fri, 8 Dec 2017 15:12:30 +0530
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The Platform data was removed earlier by,
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'commit eb96924acddc ("cpufreq: dt: Kill platform-data")'
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since there were no users at that time.
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Now this is required when the each of the cpu clocks
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can be scaled independently, which is the case
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for krait cores. So reintroduce it.
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Signed-off-by: Sricharan R <sricharan@codeaurora.org>
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---
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drivers/cpufreq/cpufreq-dt.c | 7 ++++++-
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drivers/cpufreq/cpufreq-dt.h | 6 ++++++
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2 files changed, 12 insertions(+), 1 deletion(-)
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--- a/drivers/cpufreq/cpufreq-dt.c
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+++ b/drivers/cpufreq/cpufreq-dt.c
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@@ -239,7 +239,10 @@ static int cpufreq_init(struct cpufreq_p
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}
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if (fallback) {
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- cpumask_setall(policy->cpus);
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+ struct cpufreq_dt_platform_data *pd = cpufreq_get_driver_data();
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+
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+ if (!pd || !pd->independent_clocks)
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+ cpumask_setall(policy->cpus);
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/*
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* OPP tables are initialized only for policy->cpu, do it for
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@@ -359,6 +362,8 @@ static int dt_cpufreq_probe(struct platf
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dt_cpufreq_driver.suspend = data->suspend;
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}
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+ dt_cpufreq_driver.driver_data = data;
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+
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ret = cpufreq_register_driver(&dt_cpufreq_driver);
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if (ret)
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dev_err(&pdev->dev, "failed register driver: %d\n", ret);
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--- a/drivers/cpufreq/cpufreq-dt.h
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+++ b/drivers/cpufreq/cpufreq-dt.h
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@@ -15,6 +15,12 @@
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struct cpufreq_policy;
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struct cpufreq_dt_platform_data {
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+ /*
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+ * True when each CPU has its own clock to control its
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+ * frequency, false when all CPUs are controlled by a single
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+ * clock.
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+ */
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+ bool independent_clocks;
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bool have_governor_per_policy;
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int (*suspend)(struct cpufreq_policy *policy);
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@ -1,26 +0,0 @@
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From 5c294df1715d673f94f3b0a6e1ea3a426ca35e6e Mon Sep 17 00:00:00 2001
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From: Georgi Djakov <georgi.djakov@linaro.org>
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Date: Thu, 28 Apr 2016 16:20:12 +0300
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Subject: [PATCH 48/69] PM / OPP: HACK: Allow to set regulator without opp_list
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Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
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---
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drivers/base/power/opp/core.c | 3 ++-
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1 file changed, 2 insertions(+), 1 deletion(-)
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--- a/drivers/opp/core.c
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+++ b/drivers/opp/core.c
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@@ -1317,11 +1317,13 @@ struct opp_table *dev_pm_opp_set_regulat
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if (!opp_table)
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return ERR_PTR(-ENOMEM);
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+#if 0
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/* This should be called before OPPs are initialized */
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if (WARN_ON(!list_empty(&opp_table->opp_list))) {
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ret = -EBUSY;
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goto err;
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}
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+#endif
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/* Another CPU that shares the OPP table has set the regulators ? */
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if (opp_table->regulators)
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