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ipq806x: fix PCIe reset gpio handling - the core already handles the active-low flag

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Signed-off-by: Felix Fietkau <nbd@openwrt.org>

SVN-Revision: 47547
v19.07.3_mercusys_ac12_duma
Felix Fietkau 9 years ago
parent 155469b1f9
commit 4018f15e21
2 changed files with 60 additions and 16 deletions
Show Stats Download Patch File Download Diff File

38
target/linux/ipq806x/patches-3.18/114-pcie-add-ctlr-init.patch
Unescape Escape View File

@ -83,7 +83,29 @@
};
struct qcom_pcie_resources_v1 {
@@ -156,10 +202,13 @@ static void qcom_pcie_disable_resources_
@@ -106,20 +152,10 @@ writel_masked(void __iomem *addr, u32 cl
static void qcom_ep_reset_assert_deassert(struct qcom_pcie *pcie, int assert)
{
- int val, active_low;
-
if (IS_ERR_OR_NULL(pcie->reset))
return;
- active_low = gpiod_is_active_low(pcie->reset);
-
- if (assert)
- val = !!active_low;
- else
- val = !active_low;
-
- gpiod_set_value(pcie->reset, val);
-
+ gpiod_set_value(pcie->reset, assert);
usleep_range(PERST_DELAY_MIN_US, PERST_DELAY_MAX_US);
}
@@ -156,10 +192,13 @@ static void qcom_pcie_disable_resources_
reset_control_assert(res->axi_reset);
reset_control_assert(res->ahb_reset);
reset_control_assert(res->por_reset);
@ -98,7 +120,7 @@
regulator_disable(res->vdda);
regulator_disable(res->vdda_phy);
regulator_disable(res->vdda_refclk);
@@ -201,6 +250,12 @@ static int qcom_pcie_enable_resources_v0
@@ -201,6 +240,12 @@ static int qcom_pcie_enable_resources_v0
goto err_vdda_phy;
}
@ -111,7 +133,7 @@
ret = clk_prepare_enable(res->iface_clk);
if (ret) {
dev_err(dev, "cannot prepare/enable iface clock\n");
@@ -219,21 +274,40 @@ static int qcom_pcie_enable_resources_v0
@@ -219,21 +264,40 @@ static int qcom_pcie_enable_resources_v0
goto err_clk_phy;
}
@ -152,7 +174,7 @@
regulator_disable(res->vdda_phy);
err_vdda_phy:
regulator_disable(res->vdda_refclk);
@@ -329,6 +403,14 @@ static int qcom_pcie_get_resources_v0(st
@@ -329,6 +393,14 @@ static int qcom_pcie_get_resources_v0(st
if (IS_ERR(res->phy_clk))
return PTR_ERR(res->phy_clk);
@ -167,7 +189,7 @@
res->pci_reset = devm_reset_control_get(dev, "pci");
if (IS_ERR(res->pci_reset))
return PTR_ERR(res->pci_reset);
@@ -349,6 +431,14 @@ static int qcom_pcie_get_resources_v0(st
@@ -349,6 +421,14 @@ static int qcom_pcie_get_resources_v0(st
if (IS_ERR(res->phy_reset))
return PTR_ERR(res->phy_reset);
@ -182,7 +204,7 @@
return 0;
}
@@ -461,6 +551,57 @@ err_res:
@@ -461,6 +541,57 @@ err_res:
qcom_pcie_disable_resources_v1(pcie);
}
@ -240,7 +262,7 @@
static void qcom_pcie_host_init_v0(struct pcie_port *pp)
{
struct qcom_pcie *pcie = to_qcom_pcie(pp);
@@ -470,15 +611,34 @@ static void qcom_pcie_host_init_v0(struc
@@ -470,15 +601,34 @@ static void qcom_pcie_host_init_v0(struc
qcom_ep_reset_assert(pcie);
@ -277,7 +299,7 @@
ret = reset_control_deassert(res->phy_reset);
if (ret) {
dev_err(dev, "cannot deassert phy reset\n");
@@ -517,6 +677,9 @@ static void qcom_pcie_host_init_v0(struc
@@ -517,6 +667,9 @@ static void qcom_pcie_host_init_v0(struc
if (ret)
goto err;

38
target/linux/ipq806x/patches-4.1/114-pcie-add-ctlr-init.patch
Unescape Escape View File

@ -83,7 +83,29 @@
};
struct qcom_pcie_resources_v1 {
@@ -156,10 +202,13 @@ static void qcom_pcie_disable_resources_
@@ -106,20 +152,10 @@ writel_masked(void __iomem *addr, u32 cl
static void qcom_ep_reset_assert_deassert(struct qcom_pcie *pcie, int assert)
{
- int val, active_low;
-
if (IS_ERR_OR_NULL(pcie->reset))
return;
- active_low = gpiod_is_active_low(pcie->reset);
-
- if (assert)
- val = !!active_low;
- else
- val = !active_low;
-
- gpiod_set_value(pcie->reset, val);
-
+ gpiod_set_value(pcie->reset, assert);
usleep_range(PERST_DELAY_MIN_US, PERST_DELAY_MAX_US);
}
@@ -156,10 +192,13 @@ static void qcom_pcie_disable_resources_
reset_control_assert(res->axi_reset);
reset_control_assert(res->ahb_reset);
reset_control_assert(res->por_reset);
@ -98,7 +120,7 @@
regulator_disable(res->vdda);
regulator_disable(res->vdda_phy);
regulator_disable(res->vdda_refclk);
@@ -201,6 +250,12 @@ static int qcom_pcie_enable_resources_v0
@@ -201,6 +240,12 @@ static int qcom_pcie_enable_resources_v0
goto err_vdda_phy;
}
@ -111,7 +133,7 @@
ret = clk_prepare_enable(res->iface_clk);
if (ret) {
dev_err(dev, "cannot prepare/enable iface clock\n");
@@ -219,21 +274,40 @@ static int qcom_pcie_enable_resources_v0
@@ -219,21 +264,40 @@ static int qcom_pcie_enable_resources_v0
goto err_clk_phy;
}
@ -152,7 +174,7 @@
regulator_disable(res->vdda_phy);
err_vdda_phy:
regulator_disable(res->vdda_refclk);
@@ -329,6 +403,14 @@ static int qcom_pcie_get_resources_v0(st
@@ -329,6 +393,14 @@ static int qcom_pcie_get_resources_v0(st
if (IS_ERR(res->phy_clk))
return PTR_ERR(res->phy_clk);
@ -167,7 +189,7 @@
res->pci_reset = devm_reset_control_get(dev, "pci");
if (IS_ERR(res->pci_reset))
return PTR_ERR(res->pci_reset);
@@ -349,6 +431,14 @@ static int qcom_pcie_get_resources_v0(st
@@ -349,6 +421,14 @@ static int qcom_pcie_get_resources_v0(st
if (IS_ERR(res->phy_reset))
return PTR_ERR(res->phy_reset);
@ -182,7 +204,7 @@
return 0;
}
@@ -461,6 +551,57 @@ err_res:
@@ -461,6 +541,57 @@ err_res:
qcom_pcie_disable_resources_v1(pcie);
}
@ -240,7 +262,7 @@
static void qcom_pcie_host_init_v0(struct pcie_port *pp)
{
struct qcom_pcie *pcie = to_qcom_pcie(pp);
@@ -470,15 +611,34 @@ static void qcom_pcie_host_init_v0(struc
@@ -470,15 +601,34 @@ static void qcom_pcie_host_init_v0(struc
qcom_ep_reset_assert(pcie);
@ -277,7 +299,7 @@
ret = reset_control_deassert(res->phy_reset);
if (ret) {
dev_err(dev, "cannot deassert phy reset\n");
@@ -517,6 +677,9 @@ static void qcom_pcie_host_init_v0(struc
@@ -517,6 +667,9 @@ static void qcom_pcie_host_init_v0(struc
if (ret)
goto err;

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