combine all avr32 patches into a single one
SVN-Revision: 25566v19.07.3_mercusys_ac12_duma
Imre Kaloz
14 years ago
parent
f57170e7c7
commit
3e974e67b2
@ -1,25 +0,0 @@
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--- a/gcc/config.gcc
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+++ b/gcc/config.gcc
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@@ -836,7 +836,7 @@ avr-*-*)
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;;
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avr32*-*-linux*)
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tm_file="dbxelf.h elfos.h linux.h avr32/linux-elf.h avr32/avr32.h "
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- tmake_file="t-linux avr32/t-avr32 avr32/t-elf"
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+ tmake_file="t-linux avr32/t-avr32-linux"
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extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o"
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extra_modes=avr32/avr32-modes.def
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gnu_ld=yes
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--- a/libgcc/config.host
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+++ b/libgcc/config.host
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@@ -240,6 +240,11 @@ arm-*-pe*)
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;;
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arm*-*-kaos*)
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;;
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+avr32-*-linux*)
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+ # No need to build crtbeginT.o on uClibc systems. Should probably be
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+ # moved to the OS specific section above.
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+ extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o"
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+ ;;
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avr32-*-*)
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;;
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avr-*-rtems*)
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@ -1,10 +0,0 @@
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--- a/gcc/config/avr32/lib1funcs.S
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+++ b/gcc/config/avr32/lib1funcs.S
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@@ -2800,6 +2800,7 @@ __extendsfdf_return_op1:
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lsl r11,8 /* check mantissa */
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movne r11, -1 /* Return NaN */
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moveq r11, r10 /* Return inf */
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+ mov r10, 0
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rjmp __extendsfdf_return_op1
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#endif
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@ -1,10 +0,0 @@
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--- a/gcc/config/avr32/lib1funcs.S
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+++ b/gcc/config/avr32/lib1funcs.S
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@@ -1036,6 +1036,7 @@ __avr32_f64_add_opL_nan_or_inf:
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brne __avr32_f64_add_return_nan
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mov r10, 0 /* Generate Inf in r11, r10 */
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mov_imm r11, 0x7ff00000
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+ or r11, r12 /* Put sign bit back */
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ldm sp++, r5, r6, r7, pc/* opL Inf, return Inf */
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__avr32_f64_add_return_nan:
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mov r10, -1 /* Generate NaN in r11, r10 */
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@ -1,34 +0,0 @@
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--- a/gcc/config/avr32/lib1funcs.S
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+++ b/gcc/config/avr32/lib1funcs.S
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@@ -2257,10 +2257,13 @@ __avr32_f32_div:
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/* Unpack */
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lsl r12,1
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- reteq 0 /* Return zero if op1 is zero */
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lsl r11,1
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breq 4f /* Check op2 for zero */
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-
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+
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+ tst r12, r12
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+ moveq r9, 0
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+ breq 12
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+
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/* Unpack op1*/
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/* exp: r9 */
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/* sf: r12 */
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@@ -2279,9 +2282,14 @@ __avr32_f32_div:
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breq 13f /*If number is subnormal*/
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cp r10, 0xff
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brhs 3f /* Check op2 for NaN or Inf */
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-
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lsl r11,7
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sbr r11, 31 /*Implicit bit*/
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+
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+ cp.w r9, 0
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+ subfeq r12, 0
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+ reteq 0 /* op1 is zero and op2 is not zero */
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+ /* or NaN so return zero */
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+
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14:
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/* For UC3, store with predecrement is faster than stm */
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@ -1,66 +0,0 @@
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--- a/gcc/config/avr32/lib1funcs.S
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+++ b/gcc/config/avr32/lib1funcs.S
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@@ -1389,25 +1389,30 @@ __avr32_f64_cmp_lt:
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#endif
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/* compare magnitude of op1 and op2 */
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+ st.w --sp, lr
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+ st.w --sp, r7
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lsl r11,1 /* Remove sign bit of op1 */
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srcs r12 /* Sign op1 to lsb of r12*/
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- subfeq r10, 0
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- breq 3f /* op1 zero */
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lsl r9,1 /* Remove sign bit of op2 */
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+ srcs r7
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rol r12 /* Sign op2 to lsb of lr, sign bit op1 bit 1 of r12*/
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/* Check for Nan */
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- pushm lr
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- mov_imm lr, 0xffe00000
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+ mov_imm lr, 0xffe00000
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cp.w r10,0
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cpc r11,lr
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brhi 0f /* We have NaN */
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cp.w r8,0
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cpc r9,lr
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brhi 0f /* We have NaN */
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- popm lr
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-
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+
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+ cp.w r11, 0
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+ subfeq r10, 0
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+ breq 3f /* op1 zero */
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+ ld.w r7, sp++
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+ ld.w lr, sp++
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+
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cp.w r12,3 /* both operands negative ?*/
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breq 1f
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@@ -1453,18 +1458,22 @@ __avr32_f64_cmp_lt:
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#endif
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0:
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+ ld.w r7, sp++
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popm pc, r12=0
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#endif
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3:
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- lsl r9,1 /* Remove sign bit of op1 */
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+ cp.w r7, 1 /* Check sign bit from r9 */
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#ifdef L_avr32_f64_cmp_ge
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- srcs r12 /* If op2 is negative then op1 >= op2. */
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+ sreq r12 /* If op2 is negative then op1 >= op2. */
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#endif
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#ifdef L_avr32_f64_cmp_lt
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- srcc r12 /* If op2 is positve then op1 <= op2. */
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+ srne r12 /* If op2 is positve then op1 <= op2. */
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#endif
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- subfeq r8, 0
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+ cp.w r9, 0
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+ subfeq r8, 0
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+ ld.w r7, sp++
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+ ld.w lr, sp++
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#ifdef L_avr32_f64_cmp_ge
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reteq 1 /* Both operands are zero. Return true. */
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#endif
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@ -1,20 +0,0 @@
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--- a/gcc/config/avr32/lib1funcs.S
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+++ b/gcc/config/avr32/lib1funcs.S
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@@ -1733,7 +1733,7 @@ __avr32_f64_div_round_subnormal:
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brne 16f /* Return NaN if op1 is NaN */
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/* Op1 is inf check op2 */
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lsr r6, r9, 20 /* Extract exponent */
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- cbr r6, 8 /* Clear sign bit */
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+ cbr r6, 11 /* Clear sign bit */
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cp r6, 0x7ff
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brne 17f /* Inf/number gives inf, return inf */
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rjmp 16f /* The rest gives NaN*/
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@@ -1849,7 +1849,7 @@ __avr32_f64_div_res_subnormal:/* Divide
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16: /* Return NaN. */
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mov r11, -1
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- mov r10, -1
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+ mov r10, 0
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ldm sp++, r0, r1, r2, r3, r4, r5, r6, r7,pc
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17: /* Return INF. */
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@ -1,11 +0,0 @@
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--- a/gcc/config/avr32/lib1funcs.S
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+++ b/gcc/config/avr32/lib1funcs.S
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@@ -2866,7 +2866,7 @@ __truncdfsf_return_op1:
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/* NaN or inf */
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cbr r12,31 /* clear implicit bit */
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retne -1 /* Return NaN if mantissa not zero */
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- mov_imm r12, 0xff000000
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+ mov_imm r12, 0x7f800000
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ret r12 /* Return inf */
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3: /* Result is subnormal. Adjust it.*/
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@ -1,27 +0,0 @@
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--- a/gcc/config/avr32/lib1funcs.S
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+++ b/gcc/config/avr32/lib1funcs.S
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@@ -2271,7 +2271,7 @@ __avr32_f32_div:
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tst r12, r12
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moveq r9, 0
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- breq 12
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+ breq 12f
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/* Unpack op1*/
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/* exp: r9 */
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@@ -2467,9 +2467,14 @@ __divsf_return_op1:
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reteq 0 /* Return zero if number/inf*/
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ret -1 /* Return NaN*/
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4:
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- /* Op2 is zero ? */
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+ /* Op1 is zero ? */
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tst r12,r12
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reteq -1 /* 0.0/0.0 is NaN */
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+ /* Op1 is Nan? */
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+ lsr r9, r12, 24
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+ breq 11f /*If number is subnormal*/
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+ cp r9, 0xff
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+ brhs 2b /* Check op1 for NaN or Inf */
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/* Nonzero/0.0 is Inf. Sign bit will be shifted in before returning*/
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mov_imm r12, 0xff000000
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rjmp __divsf_return_op1
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@ -1,32 +0,0 @@
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--- a/gcc/config/avr32/avr32.c
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+++ b/gcc/config/avr32/avr32.c
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@@ -6501,12 +6501,23 @@ avr32_reorg_optimization (void)
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continue;
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set = single_set (scan);
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- if (set && rtx_equal_p (src_reg, SET_DEST (set)))
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- {
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- link = scan;
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- break;
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- }
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-
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+ // Fix for bug #11763 : the following if condition
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+ // has been modified and else part is included to
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+ // set the link to NULL_RTX.
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+ // if (set && rtx_equal_p (src_reg, SET_DEST (set)))
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+ if (set && (REGNO(src_reg) == REGNO(SET_DEST(set))))
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+ {
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+ if (rtx_equal_p (src_reg, SET_DEST (set)))
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+ {
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+ link = scan;
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+ break;
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+ }
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+ else
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+ {
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+ link = NULL_RTX;
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+ break;
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+ }
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+ }
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}
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@ -1,15 +0,0 @@
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--- a/gcc/config/avr32/lib1funcs.S
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+++ b/gcc/config/avr32/lib1funcs.S
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@@ -1852,7 +1852,11 @@ __avr32_f64_div_res_subnormal:/* Divide
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mov r10, 0
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ldm sp++, r0, r1, r2, r3, r4, r5, r6, r7,pc
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-17: /* Return INF. */
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+17:
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+ /* Check if op1 is zero. */
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+ or r4, r10, r11
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+ breq __avr32_f64_div_op1_zero
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+ /* Return INF. */
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mov r11, lr /*Get correct sign*/
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andh r11, 0x8000, COH
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orh r11, 0x7ff0
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