cns3xxx: update to linux 3.10
Signed-off-by: Felix Fietkau <nbd@openwrt.org> SVN-Revision: 41917v19.07.3_mercusys_ac12_duma
parent
6944689e96
commit
3c7cd63b72
@ -0,0 +1,8 @@
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--- a/arch/arm/mach-cns3xxx/Makefile
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+++ b/arch/arm/mach-cns3xxx/Makefile
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@@ -1,3 +1,5 @@
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+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
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+
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obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o
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cns3xxx-y += core.o pm.o
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cns3xxx-$(CONFIG_ATAGS) += devices.o
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@ -0,0 +1,11 @@
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--- a/arch/arm/mach-cns3xxx/core.c
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+++ b/arch/arm/mach-cns3xxx/core.c
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@@ -307,7 +307,7 @@ static struct usb_ohci_pdata cns3xxx_usb
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.power_off = csn3xxx_usb_power_off,
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};
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-static struct of_dev_auxdata cns3xxx_auxdata[] __initconst = {
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+static const struct of_dev_auxdata cns3xxx_auxdata[] __initconst = {
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{ "intel,usb-ehci", CNS3XXX_USB_BASE, "ehci-platform", &cns3xxx_usb_ehci_pdata },
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{ "intel,usb-ohci", CNS3XXX_USB_OHCI_BASE, "ohci-platform", &cns3xxx_usb_ohci_pdata },
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{ "cavium,cns3420-ahci", CNS3XXX_SATA2_BASE, "ahci", NULL },
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@ -0,0 +1,56 @@
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--- a/arch/arm/include/asm/glue-cache.h
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+++ b/arch/arm/include/asm/glue-cache.h
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@@ -129,11 +129,19 @@
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#define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range)
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#define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range)
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#define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range)
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+#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST
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#define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area)
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#define dmac_map_area __glue(_CACHE,_dma_map_area)
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#define dmac_unmap_area __glue(_CACHE,_dma_unmap_area)
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#define dmac_flush_range __glue(_CACHE,_dma_flush_range)
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+#else
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+#define __cpuc_flush_dcache_area __glue(fiq,_flush_kern_dcache_area)
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+
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+#define dmac_map_area __glue(fiq,_dma_map_area)
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+#define dmac_unmap_area __glue(fiq,_dma_unmap_area)
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+#define dmac_flush_range __glue(fiq,_dma_flush_range)
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+#endif /* CONFIG_DMA_CACHE_FIQ_BROADCAST */
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#endif
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#endif
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--- a/arch/arm/mm/Kconfig
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+++ b/arch/arm/mm/Kconfig
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@@ -823,6 +823,17 @@ config DMA_CACHE_RWFO
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in hardware, other workarounds are needed (e.g. cache
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maintenance broadcasting in software via FIQ).
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+config DMA_CACHE_FIQ_BROADCAST
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+ bool "Enable fiq broadcast DMA cache maintenance"
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+ depends on CPU_V6K && SMP
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+ select FIQ
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+ help
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+ The Snoop Control Unit on ARM11MPCore does not detect the
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+ cache maintenance operations and the dma_{map,unmap}_area()
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+ functions may leave stale cache entries on other CPUs. By
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+ enabling this option, fiq broadcast in the ARMv6
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+ DMA cache maintenance functions is performed.
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+
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config OUTER_CACHE
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bool
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--- a/arch/arm/mm/flush.c
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+++ b/arch/arm/mm/flush.c
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@@ -286,7 +286,10 @@ void flush_dcache_page(struct page *page
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mapping = page_mapping(page);
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- if (!cache_ops_need_broadcast() &&
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+ if (
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+#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST
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+ !cache_ops_need_broadcast() &&
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+#endif
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mapping && !mapping_mapped(mapping))
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clear_bit(PG_dcache_clean, &page->flags);
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else {
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@ -0,0 +1,30 @@
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--- a/arch/arm/mach-cns3xxx/Makefile
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+++ b/arch/arm/mach-cns3xxx/Makefile
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@@ -5,3 +5,5 @@ cns3xxx-y += core.o pm.o
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cns3xxx-$(CONFIG_ATAGS) += devices.o
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cns3xxx-$(CONFIG_PCI) += pcie.o
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cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
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+cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o
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+cns3xxx-$(CONFIG_HOTPLUG_CPU) += hotplug.o
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--- a/arch/arm/mach-cns3xxx/Kconfig
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+++ b/arch/arm/mach-cns3xxx/Kconfig
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@@ -6,6 +6,9 @@ config ARCH_CNS3XXX
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select MIGHT_HAVE_CACHE_L2X0
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select MIGHT_HAVE_PCI
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select PCI_DOMAINS if PCI
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+ select HAVE_ARM_SCU if SMP
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+ select HAVE_ARM_TWD if LOCAL_TIMERS
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+ select HAVE_SMP
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help
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Support for Cavium Networks CNS3XXX platform.
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--- a/arch/arm/mach-cns3xxx/core.h
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+++ b/arch/arm/mach-cns3xxx/core.h
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@@ -11,6 +11,7 @@
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#ifndef __CNS3XXX_CORE_H
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#define __CNS3XXX_CORE_H
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+extern struct smp_operations cns3xxx_smp_ops;
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extern void cns3xxx_timer_init(void);
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#ifdef CONFIG_CACHE_L2X0
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@ -0,0 +1,40 @@
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--- a/arch/arm/mach-cns3xxx/Kconfig
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+++ b/arch/arm/mach-cns3xxx/Kconfig
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@@ -9,6 +9,7 @@ config ARCH_CNS3XXX
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select HAVE_ARM_SCU if SMP
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select HAVE_ARM_TWD if LOCAL_TIMERS
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select HAVE_SMP
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+ select FIQ
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help
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Support for Cavium Networks CNS3XXX platform.
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--- a/arch/arm/mach-cns3xxx/Makefile
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+++ b/arch/arm/mach-cns3xxx/Makefile
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@@ -5,5 +5,5 @@ cns3xxx-y += core.o pm.o
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cns3xxx-$(CONFIG_ATAGS) += devices.o
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cns3xxx-$(CONFIG_PCI) += pcie.o
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cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
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-cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o
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+cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o cns3xxx_fiq.o
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cns3xxx-$(CONFIG_HOTPLUG_CPU) += hotplug.o
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--- a/arch/arm/mach-cns3xxx/cns3xxx.h
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+++ b/arch/arm/mach-cns3xxx/cns3xxx.h
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@@ -267,6 +267,7 @@
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#define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100)
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#define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100)
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+#define MISC_FIQ_CPU(x) MISC_MEM_MAP(0xA58 - (x) * 0x4)
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/*
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* Power management and clock control
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*/
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--- a/arch/arm/mm/Kconfig
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+++ b/arch/arm/mm/Kconfig
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@@ -806,7 +806,7 @@ config KUSER_HELPERS
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config DMA_CACHE_RWFO
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bool "Enable read/write for ownership DMA cache maintenance"
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- depends on CPU_V6K && SMP
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+ depends on CPU_V6K && SMP && !ARCH_CNS3XXX
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default y
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help
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The Snoop Control Unit on ARM11MPCore does not detect the
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@ -1,7 +1,7 @@
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--- a/arch/arm/mach-cns3xxx/core.c
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+++ b/arch/arm/mach-cns3xxx/core.c
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@@ -69,6 +69,16 @@ static struct map_desc cns3xxx_io_desc[]
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.pfn = __phys_to_pfn(CNS3XXX_SSP_BASE),
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@@ -50,6 +50,16 @@ static struct map_desc cns3xxx_io_desc[]
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.pfn = __phys_to_pfn(CNS3XXX_PM_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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+ }, {
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@ -1,6 +1,6 @@
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--- a/arch/arm/mach-cns3xxx/devices.c
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+++ b/arch/arm/mach-cns3xxx/devices.c
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@@ -41,7 +41,7 @@ static struct resource cns3xxx_ahci_reso
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@@ -40,7 +40,7 @@ static struct resource cns3xxx_ahci_reso
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static u64 cns3xxx_ahci_dmamask = DMA_BIT_MASK(32);
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static struct platform_device cns3xxx_ahci_pdev = {
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@ -0,0 +1,82 @@
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--- a/arch/arm/mach-cns3xxx/cns3420vb.c
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+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
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@@ -245,6 +245,10 @@ static void __init cns3420_init(void)
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cns3xxx_ahci_init();
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cns3xxx_sdhci_init();
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+ cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
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+ NR_IRQS_CNS3XXX);
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+ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
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+ NR_IRQS_CNS3XXX + 32);
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pm_power_off = cns3xxx_power_off;
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}
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--- a/arch/arm/mach-cns3xxx/core.h
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+++ b/arch/arm/mach-cns3xxx/core.h
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@@ -15,12 +15,6 @@ extern struct smp_operations cns3xxx_smp
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extern void cns3xxx_timer_init(void);
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extern void cns3xxx_pcie_iotable_init(void);
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-#ifdef CONFIG_CACHE_L2X0
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-void __init cns3xxx_l2x0_init(void);
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-#else
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-static inline void cns3xxx_l2x0_init(void) {}
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-#endif /* CONFIG_CACHE_L2X0 */
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-
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void __init cns3xxx_map_io(void);
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void __init cns3xxx_init_irq(void);
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int __init cns3xxx_pcie_init(void);
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--- a/arch/arm/mach-cns3xxx/Kconfig
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+++ b/arch/arm/mach-cns3xxx/Kconfig
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@@ -2,6 +2,8 @@ config ARCH_CNS3XXX
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bool "Cavium Networks CNS3XXX family" if ARCH_MULTI_V6
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select ARM_GIC
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select CPU_V6K
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+ select ARCH_REQUIRE_GPIOLIB
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+ select GENERIC_IRQ_CHIP
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select GENERIC_CLOCKEVENTS
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select MIGHT_HAVE_CACHE_L2X0
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select MIGHT_HAVE_PCI
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--- a/arch/arm/mach-cns3xxx/Makefile
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+++ b/arch/arm/mach-cns3xxx/Makefile
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@@ -1,7 +1,7 @@
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ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
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obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o
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-cns3xxx-y += core.o pm.o
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+cns3xxx-y += core.o pm.o gpio.o
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cns3xxx-$(CONFIG_ATAGS) += devices.o
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cns3xxx-$(CONFIG_PCI) += pcie.o
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cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
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--- a/arch/arm/mach-cns3xxx/cns3xxx.h
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+++ b/arch/arm/mach-cns3xxx/cns3xxx.h
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@@ -68,8 +68,10 @@
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#define SMC_PCELL_ID_3_OFFSET 0xFFC
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#define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */
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+#define CNS3XXX_GPIOA_BASE_VIRT 0xFB006000
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#define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */
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+#define CNS3XXX_GPIOB_BASE_VIRT 0xFB007000
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#define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */
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--- a/arch/arm/mach-cns3xxx/core.c
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+++ b/arch/arm/mach-cns3xxx/core.c
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@@ -60,6 +60,16 @@ static struct map_desc cns3xxx_io_desc[]
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.pfn = __phys_to_pfn(CNS3XXX_PCIE1_IO_BASE),
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.length = SZ_16M,
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.type = MT_DEVICE,
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+ }, {
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+ .virtual = CNS3XXX_GPIOA_BASE_VIRT,
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+ .pfn = __phys_to_pfn(CNS3XXX_GPIOA_BASE),
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+ .length = SZ_4K,
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+ .type = MT_DEVICE,
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+ }, {
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+ .virtual = CNS3XXX_GPIOB_BASE_VIRT,
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+ .pfn = __phys_to_pfn(CNS3XXX_GPIOB_BASE),
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+ .length = SZ_4K,
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+ .type = MT_DEVICE,
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},
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};
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@ -1,6 +1,6 @@
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--- a/drivers/mmc/host/sdhci-cns3xxx.c
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+++ b/drivers/mmc/host/sdhci-cns3xxx.c
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@@ -89,10 +89,11 @@ static struct sdhci_pltfm_data sdhci_cns
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@@ -88,10 +88,11 @@ static const struct sdhci_pltfm_data sdh
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.ops = &sdhci_cns3xxx_ops,
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.quirks = SDHCI_QUIRK_BROKEN_DMA |
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SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
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@ -1,170 +0,0 @@
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--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
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+++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
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@@ -20,22 +20,22 @@
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#define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */
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#define CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */
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-#define CNS3XXX_SWITCH_BASE_VIRT 0xFFF00000
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+#define CNS3XXX_SWITCH_BASE_VIRT 0xFEF00000
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#define CNS3XXX_PPE_BASE 0x70001000 /* HANT */
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-#define CNS3XXX_PPE_BASE_VIRT 0xFFF50000
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+#define CNS3XXX_PPE_BASE_VIRT 0xFEF50000
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#define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */
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-#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT 0xFFF60000
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+#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT 0xFEF60000
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#define CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */
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-#define CNS3XXX_SSP_BASE_VIRT 0xFFF01000
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+#define CNS3XXX_SSP_BASE_VIRT 0xFEF01000
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#define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */
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-#define CNS3XXX_DMC_BASE_VIRT 0xFFF02000
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+#define CNS3XXX_DMC_BASE_VIRT 0xFEF02000
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#define CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */
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-#define CNS3XXX_SMC_BASE_VIRT 0xFFF03000
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+#define CNS3XXX_SMC_BASE_VIRT 0xFEF03000
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#define SMC_MEMC_STATUS_OFFSET 0x000
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#define SMC_MEMIF_CFG_OFFSET 0x004
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@@ -74,13 +74,13 @@
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#define SMC_PCELL_ID_3_OFFSET 0xFFC
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#define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */
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-#define CNS3XXX_GPIOA_BASE_VIRT 0xFFF04000
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+#define CNS3XXX_GPIOA_BASE_VIRT 0xFEF04000
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#define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */
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-#define CNS3XXX_GPIOB_BASE_VIRT 0xFFF05000
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+#define CNS3XXX_GPIOB_BASE_VIRT 0xFEF05000
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#define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */
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-#define CNS3XXX_RTC_BASE_VIRT 0xFFF06000
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+#define CNS3XXX_RTC_BASE_VIRT 0xFEF06000
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#define RTC_SEC_OFFSET 0x00
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#define RTC_MIN_OFFSET 0x04
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@@ -94,10 +94,10 @@
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#define RTC_INTR_STS_OFFSET 0x34
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#define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */
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-#define CNS3XXX_MISC_BASE_VIRT 0xFB000000 /* Misc Control */
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+#define CNS3XXX_MISC_BASE_VIRT 0xFEF07000 /* Misc Control */
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#define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */
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-#define CNS3XXX_PM_BASE_VIRT 0xFB001000
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+#define CNS3XXX_PM_BASE_VIRT 0xFEF08000
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#define PM_CLK_GATE_OFFSET 0x00
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#define PM_SOFT_RST_OFFSET 0x04
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@@ -109,28 +109,28 @@
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#define PM_PLL_HM_PD_OFFSET 0x1C
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#define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */
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-#define CNS3XXX_UART0_BASE_VIRT 0xFB002000
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+#define CNS3XXX_UART0_BASE_VIRT 0xFEF09000
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#define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */
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-#define CNS3XXX_UART1_BASE_VIRT 0xFFF0A000
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+#define CNS3XXX_UART1_BASE_VIRT 0xFEF0A000
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#define CNS3XXX_UART2_BASE 0x78800000 /* UART 2 */
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-#define CNS3XXX_UART2_BASE_VIRT 0xFFF0B000
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+#define CNS3XXX_UART2_BASE_VIRT 0xFEF0B000
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#define CNS3XXX_DMAC_BASE 0x79000000 /* Generic DMA Control */
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-#define CNS3XXX_DMAC_BASE_VIRT 0xFFF0D000
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+#define CNS3XXX_DMAC_BASE_VIRT 0xFEF0D000
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#define CNS3XXX_CORESIGHT_BASE 0x7A000000 /* CoreSight */
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-#define CNS3XXX_CORESIGHT_BASE_VIRT 0xFFF0E000
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+#define CNS3XXX_CORESIGHT_BASE_VIRT 0xFEF0E000
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#define CNS3XXX_CRYPTO_BASE 0x7B000000 /* Crypto */
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-#define CNS3XXX_CRYPTO_BASE_VIRT 0xFFF0F000
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+#define CNS3XXX_CRYPTO_BASE_VIRT 0xFEF0F000
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#define CNS3XXX_I2S_BASE 0x7C000000 /* I2S */
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-#define CNS3XXX_I2S_BASE_VIRT 0xFFF10000
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+#define CNS3XXX_I2S_BASE_VIRT 0xFEF10000
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#define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */
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-#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFB003000
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+#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFEF10800
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#define TIMER1_COUNTER_OFFSET 0x00
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#define TIMER1_AUTO_RELOAD_OFFSET 0x04
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||||
@@ -150,42 +150,42 @@
|
||||
#define TIMER_FREERUN_CONTROL_OFFSET 0x44
|
||||
|
||||
#define CNS3XXX_HCIE_BASE 0x7D000000 /* HCIE Control */
|
||||
-#define CNS3XXX_HCIE_BASE_VIRT 0xFFF30000
|
||||
+#define CNS3XXX_HCIE_BASE_VIRT 0xFEF30000
|
||||
|
||||
#define CNS3XXX_RAID_BASE 0x7E000000 /* RAID Control */
|
||||
-#define CNS3XXX_RAID_BASE_VIRT 0xFFF12000
|
||||
+#define CNS3XXX_RAID_BASE_VIRT 0xFEF12000
|
||||
|
||||
#define CNS3XXX_AXI_IXC_BASE 0x7F000000 /* AXI IXC */
|
||||
-#define CNS3XXX_AXI_IXC_BASE_VIRT 0xFFF13000
|
||||
+#define CNS3XXX_AXI_IXC_BASE_VIRT 0xFEF13000
|
||||
|
||||
#define CNS3XXX_CLCD_BASE 0x80000000 /* LCD Control */
|
||||
-#define CNS3XXX_CLCD_BASE_VIRT 0xFFF14000
|
||||
+#define CNS3XXX_CLCD_BASE_VIRT 0xFEF14000
|
||||
|
||||
#define CNS3XXX_USBOTG_BASE 0x81000000 /* USB OTG Control */
|
||||
-#define CNS3XXX_USBOTG_BASE_VIRT 0xFFF15000
|
||||
+#define CNS3XXX_USBOTG_BASE_VIRT 0xFEF15000
|
||||
|
||||
#define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */
|
||||
|
||||
#define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */
|
||||
#define CNS3XXX_SATA2_SIZE SZ_16M
|
||||
-#define CNS3XXX_SATA2_BASE_VIRT 0xFFF17000
|
||||
+#define CNS3XXX_SATA2_BASE_VIRT 0xFEF17000
|
||||
|
||||
#define CNS3XXX_CAMERA_BASE 0x84000000 /* Camera Interface */
|
||||
-#define CNS3XXX_CAMERA_BASE_VIRT 0xFFF18000
|
||||
+#define CNS3XXX_CAMERA_BASE_VIRT 0xFEF18000
|
||||
|
||||
#define CNS3XXX_SDIO_BASE 0x85000000 /* SDIO */
|
||||
-#define CNS3XXX_SDIO_BASE_VIRT 0xFFF19000
|
||||
+#define CNS3XXX_SDIO_BASE_VIRT 0xFEF19000
|
||||
|
||||
#define CNS3XXX_I2S_TDM_BASE 0x86000000 /* I2S TDM */
|
||||
-#define CNS3XXX_I2S_TDM_BASE_VIRT 0xFFF1A000
|
||||
+#define CNS3XXX_I2S_TDM_BASE_VIRT 0xFEF1A000
|
||||
|
||||
#define CNS3XXX_2DG_BASE 0x87000000 /* 2D Graphic Control */
|
||||
-#define CNS3XXX_2DG_BASE_VIRT 0xFFF1B000
|
||||
+#define CNS3XXX_2DG_BASE_VIRT 0xFEF1B000
|
||||
|
||||
#define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */
|
||||
|
||||
#define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */
|
||||
-#define CNS3XXX_L2C_BASE_VIRT 0xFFF27000
|
||||
+#define CNS3XXX_L2C_BASE_VIRT 0xFEF27000
|
||||
|
||||
#define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */
|
||||
#define CNS3XXX_PCIE0_MEM_BASE_VIRT 0xE0000000
|
||||
@@ -227,7 +227,7 @@
|
||||
* Testchip peripheral and fpga gic regions
|
||||
*/
|
||||
#define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */
|
||||
-#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFB004000
|
||||
+#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFEE00000
|
||||
|
||||
#define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */
|
||||
#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x100)
|
||||
@@ -239,7 +239,7 @@
|
||||
#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000)
|
||||
|
||||
#define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */
|
||||
-#define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000
|
||||
+#define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFEE02000
|
||||
|
||||
/*
|
||||
* Misc block
|
@ -1,69 +0,0 @@
|
||||
--- a/arch/arm/Kconfig
|
||||
+++ b/arch/arm/Kconfig
|
||||
@@ -365,6 +365,7 @@ config ARCH_CNS3XXX
|
||||
select MIGHT_HAVE_CACHE_L2X0
|
||||
select MIGHT_HAVE_PCI
|
||||
select PCI_DOMAINS if PCI
|
||||
+ select CLKDEV_LOOKUP
|
||||
help
|
||||
Support for Cavium Networks CNS3XXX platform.
|
||||
|
||||
--- a/arch/arm/mach-cns3xxx/core.c
|
||||
+++ b/arch/arm/mach-cns3xxx/core.c
|
||||
@@ -9,8 +9,11 @@
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
+#include <linux/export.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/clockchips.h>
|
||||
+#include <linux/clk.h>
|
||||
+#include <linux/clkdev.h>
|
||||
#include <linux/io.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/time.h>
|
||||
@@ -20,6 +23,10 @@
|
||||
#include <mach/cns3xxx.h>
|
||||
#include "core.h"
|
||||
|
||||
+struct clk {
|
||||
+ unsigned long rate;
|
||||
+};
|
||||
+
|
||||
static struct map_desc cns3xxx_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = CNS3XXX_TC11MP_SCU_BASE_VIRT,
|
||||
@@ -277,3 +284,33 @@ void __init cns3xxx_l2x0_init(void)
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CACHE_L2X0 */
|
||||
+
|
||||
+int clk_enable(struct clk *clk)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+EXPORT_SYMBOL(clk_enable);
|
||||
+
|
||||
+void clk_disable(struct clk *clk)
|
||||
+{
|
||||
+}
|
||||
+EXPORT_SYMBOL(clk_disable);
|
||||
+
|
||||
+unsigned long clk_get_rate(struct clk *clk)
|
||||
+{
|
||||
+ return clk->rate;
|
||||
+}
|
||||
+EXPORT_SYMBOL(clk_get_rate);
|
||||
+
|
||||
+static struct clk_lookup cns3xxx_clocks[] = {
|
||||
+ {
|
||||
+ /* TODO */
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+int __init cns3xxx_clocks_init(void)
|
||||
+{
|
||||
+ clkdev_add_table(cns3xxx_clocks, ARRAY_SIZE(cns3xxx_clocks));
|
||||
+ return 0;
|
||||
+}
|
||||
+postcore_initcall(cns3xxx_clocks_init);
|
@ -1,35 +0,0 @@
|
||||
--- a/arch/arm/Kconfig
|
||||
+++ b/arch/arm/Kconfig
|
||||
@@ -366,6 +366,7 @@ config ARCH_CNS3XXX
|
||||
select MIGHT_HAVE_PCI
|
||||
select PCI_DOMAINS if PCI
|
||||
select CLKDEV_LOOKUP
|
||||
+ select CPU_CACHE_FORCE_MULTI
|
||||
help
|
||||
Support for Cavium Networks CNS3XXX platform.
|
||||
|
||||
--- a/arch/arm/mm/Kconfig
|
||||
+++ b/arch/arm/mm/Kconfig
|
||||
@@ -496,6 +496,9 @@ config CPU_CACHE_VIPT
|
||||
config CPU_CACHE_FA
|
||||
bool
|
||||
|
||||
+config CPU_CACHE_FORCE_MULTI
|
||||
+ bool
|
||||
+
|
||||
if MMU
|
||||
# The copy-page model
|
||||
config CPU_COPY_V4WT
|
||||
--- a/arch/arm/include/asm/glue-cache.h
|
||||
+++ b/arch/arm/include/asm/glue-cache.h
|
||||
@@ -129,6 +129,10 @@
|
||||
#error Unknown cache maintenance model
|
||||
#endif
|
||||
|
||||
+#if defined(CONFIG_CPU_CACHE_FORCE_MULTI) && !defined(MULTI_CACHE)
|
||||
+#define MULTI_CACHE 1
|
||||
+#endif
|
||||
+
|
||||
#ifndef MULTI_CACHE
|
||||
#define __cpuc_flush_icache_all __glue(_CACHE,_flush_icache_all)
|
||||
#define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all)
|
@ -1,38 +0,0 @@
|
||||
--- a/arch/arm/mach-cns3xxx/Makefile
|
||||
+++ b/arch/arm/mach-cns3xxx/Makefile
|
||||
@@ -1,3 +1,5 @@
|
||||
obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o devices.o
|
||||
obj-$(CONFIG_PCI) += pcie.o
|
||||
obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
|
||||
+obj-$(CONFIG_SMP) += platsmp.o headsmp.o
|
||||
+obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
--- a/arch/arm/Kconfig
|
||||
+++ b/arch/arm/Kconfig
|
||||
@@ -367,6 +367,7 @@ config ARCH_CNS3XXX
|
||||
select PCI_DOMAINS if PCI
|
||||
select CLKDEV_LOOKUP
|
||||
select CPU_CACHE_FORCE_MULTI
|
||||
+ select HAVE_SMP
|
||||
help
|
||||
Support for Cavium Networks CNS3XXX platform.
|
||||
|
||||
--- a/arch/arm/mach-cns3xxx/core.h
|
||||
+++ b/arch/arm/mach-cns3xxx/core.h
|
||||
@@ -11,6 +11,7 @@
|
||||
#ifndef __CNS3XXX_CORE_H
|
||||
#define __CNS3XXX_CORE_H
|
||||
|
||||
+extern struct smp_operations cns3xxx_smp_ops;
|
||||
extern struct sys_timer cns3xxx_timer;
|
||||
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
--- a/arch/arm/mach-cns3xxx/laguna.c
|
||||
+++ b/arch/arm/mach-cns3xxx/laguna.c
|
||||
@@ -989,6 +989,7 @@ static int __init laguna_model_setup(voi
|
||||
late_initcall(laguna_model_setup);
|
||||
|
||||
MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform")
|
||||
+ .smp = smp_ops(cns3xxx_smp_ops),
|
||||
.atag_offset = 0x100,
|
||||
.map_io = laguna_map_io,
|
||||
.init_irq = cns3xxx_init_irq,
|
@ -1,19 +0,0 @@
|
||||
--- a/arch/arm/mach-cns3xxx/core.c
|
||||
+++ b/arch/arm/mach-cns3xxx/core.c
|
||||
@@ -58,6 +58,16 @@ static struct map_desc cns3xxx_io_desc[]
|
||||
.pfn = __phys_to_pfn(CNS3XXX_PM_BASE),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
+ }, {
|
||||
+ .virtual = CNS3XXX_SWITCH_BASE_VIRT,
|
||||
+ .pfn = __phys_to_pfn(CNS3XXX_SWITCH_BASE),
|
||||
+ .length = SZ_4K,
|
||||
+ .type = MT_DEVICE,
|
||||
+ }, {
|
||||
+ .virtual = CNS3XXX_SSP_BASE_VIRT,
|
||||
+ .pfn = __phys_to_pfn(CNS3XXX_SSP_BASE),
|
||||
+ .length = SZ_4K,
|
||||
+ .type = MT_DEVICE,
|
||||
},
|
||||
};
|
||||
|
@ -1,77 +0,0 @@
|
||||
--- a/arch/arm/Kconfig
|
||||
+++ b/arch/arm/Kconfig
|
||||
@@ -368,6 +368,7 @@ config ARCH_CNS3XXX
|
||||
select CLKDEV_LOOKUP
|
||||
select CPU_CACHE_FORCE_MULTI
|
||||
select HAVE_SMP
|
||||
+ select FIQ
|
||||
help
|
||||
Support for Cavium Networks CNS3XXX platform.
|
||||
|
||||
--- a/arch/arm/kernel/fiq.c
|
||||
+++ b/arch/arm/kernel/fiq.c
|
||||
@@ -49,6 +49,8 @@
|
||||
|
||||
static unsigned long no_fiq_insn;
|
||||
|
||||
+unsigned int fiq_number[2] = {0, 0};
|
||||
+
|
||||
/* Default reacquire function
|
||||
* - we always relinquish FIQ control
|
||||
* - we always reacquire FIQ control
|
||||
@@ -70,9 +72,12 @@ static struct fiq_handler *current_fiq =
|
||||
|
||||
int show_fiq_list(struct seq_file *p, int prec)
|
||||
{
|
||||
- if (current_fiq != &default_owner)
|
||||
- seq_printf(p, "%*s: %s\n", prec, "FIQ",
|
||||
- current_fiq->name);
|
||||
+ if (current_fiq != &default_owner) {
|
||||
+ seq_printf(p, "%*s: ", prec, "FIQ");
|
||||
+ seq_printf(p, "%10u ", fiq_number[0]);
|
||||
+ seq_printf(p, "%10u ", fiq_number[1]);
|
||||
+ seq_printf(p, " %s\n", current_fiq->name);
|
||||
+ }
|
||||
|
||||
return 0;
|
||||
}
|
||||
--- a/arch/arm/mach-cns3xxx/Makefile
|
||||
+++ b/arch/arm/mach-cns3xxx/Makefile
|
||||
@@ -1,5 +1,5 @@
|
||||
obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o devices.o
|
||||
obj-$(CONFIG_PCI) += pcie.o
|
||||
obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
|
||||
-obj-$(CONFIG_SMP) += platsmp.o headsmp.o
|
||||
+obj-$(CONFIG_SMP) += platsmp.o headsmp.o cns3xxx_fiq.o
|
||||
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
|
||||
+++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
|
||||
@@ -294,6 +294,7 @@
|
||||
#define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100)
|
||||
#define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100)
|
||||
|
||||
+#define MISC_FIQ_CPU(x) MISC_MEM_MAP(0xA58 - (x) * 0x4)
|
||||
/*
|
||||
* Power management and clock control
|
||||
*/
|
||||
--- a/arch/arm/mach-cns3xxx/include/mach/irqs.h
|
||||
+++ b/arch/arm/mach-cns3xxx/include/mach/irqs.h
|
||||
@@ -14,6 +14,7 @@
|
||||
#define IRQ_LOCALTIMER 29
|
||||
#define IRQ_LOCALWDOG 30
|
||||
#define IRQ_TC11MP_GIC_START 32
|
||||
+#define FIQ_START 0
|
||||
|
||||
#include <mach/cns3xxx.h>
|
||||
|
||||
--- a/arch/arm/mm/Kconfig
|
||||
+++ b/arch/arm/mm/Kconfig
|
||||
@@ -773,7 +773,7 @@ config NEEDS_SYSCALL_FOR_CMPXCHG
|
||||
|
||||
config DMA_CACHE_RWFO
|
||||
bool "Enable read/write for ownership DMA cache maintenance"
|
||||
- depends on CPU_V6K && SMP
|
||||
+ depends on CPU_V6K && SMP && !ARCH_CNS3XXX
|
||||
default y
|
||||
help
|
||||
The Snoop Control Unit on ARM11MPCore does not detect the
|
@ -1,74 +0,0 @@
|
||||
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
|
||||
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
|
||||
@@ -247,6 +247,10 @@ static void __init cns3420_init(void)
|
||||
|
||||
cns3xxx_ahci_init();
|
||||
cns3xxx_sdhci_init();
|
||||
+ cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
|
||||
+ NR_IRQS_CNS3XXX);
|
||||
+ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
|
||||
+ NR_IRQS_CNS3XXX + 32);
|
||||
|
||||
pm_power_off = cns3xxx_power_off;
|
||||
}
|
||||
@@ -262,7 +266,7 @@ static struct map_desc cns3420_io_desc[]
|
||||
|
||||
static void __init cns3420_map_io(void)
|
||||
{
|
||||
- cns3xxx_map_io();
|
||||
+ cns3xxx_common_init();
|
||||
cns3xxx_pcie_iotable_init();
|
||||
iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc));
|
||||
|
||||
--- a/arch/arm/mach-cns3xxx/core.c
|
||||
+++ b/arch/arm/mach-cns3xxx/core.c
|
||||
@@ -82,7 +82,7 @@ static struct map_desc cns3xxx_io_desc[]
|
||||
},
|
||||
};
|
||||
|
||||
-void __init cns3xxx_map_io(void)
|
||||
+void __init cns3xxx_common_init(void)
|
||||
{
|
||||
iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
|
||||
}
|
||||
--- a/arch/arm/mach-cns3xxx/core.h
|
||||
+++ b/arch/arm/mach-cns3xxx/core.h
|
||||
@@ -22,7 +22,7 @@ void __init cns3xxx_l2x0_init(void);
|
||||
static inline void cns3xxx_l2x0_init(void) {}
|
||||
#endif /* CONFIG_CACHE_L2X0 */
|
||||
|
||||
-void __init cns3xxx_map_io(void);
|
||||
+void __init cns3xxx_common_init(void);
|
||||
void __init cns3xxx_init_irq(void);
|
||||
int __init cns3xxx_pcie_init(void);
|
||||
void cns3xxx_power_off(void);
|
||||
--- a/arch/arm/Kconfig
|
||||
+++ b/arch/arm/Kconfig
|
||||
@@ -361,6 +361,8 @@ config ARCH_CNS3XXX
|
||||
bool "Cavium Networks CNS3XXX family"
|
||||
select ARM_GIC
|
||||
select CPU_V6K
|
||||
+ select ARCH_REQUIRE_GPIOLIB
|
||||
+ select GENERIC_IRQ_CHIP
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select MIGHT_HAVE_CACHE_L2X0
|
||||
select MIGHT_HAVE_PCI
|
||||
--- a/arch/arm/mach-cns3xxx/Makefile
|
||||
+++ b/arch/arm/mach-cns3xxx/Makefile
|
||||
@@ -1,4 +1,4 @@
|
||||
-obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o devices.o
|
||||
+obj-$(CONFIG_ARCH_CNS3XXX) += core.o gpio.o pm.o devices.o
|
||||
obj-$(CONFIG_PCI) += pcie.o
|
||||
obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
|
||||
obj-$(CONFIG_SMP) += platsmp.o headsmp.o cns3xxx_fiq.o
|
||||
--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
|
||||
+++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
|
||||
@@ -627,7 +627,7 @@ int cns3xxx_cpu_clock(void);
|
||||
|
||||
#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_CNS3XXX)
|
||||
#undef NR_IRQS
|
||||
-#define NR_IRQS NR_IRQS_CNS3XXX
|
||||
+#define NR_IRQS (NR_IRQS_CNS3XXX + 64)
|
||||
#endif
|
||||
|
||||
#endif /* __MACH_BOARD_CNS3XXX_H */
|
Loading…
Reference in New Issue