sunxi: Backport patches from kernel 4.11 for A64
This backports some more patches from kernel 4.11 adding more devices to the device tree of the A64 SoC. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>v19.07.3_mercusys_ac12_duma
Hauke Mehrtens
7 years ago
parent
34a422794d
commit
3b88f74bbe
@ -0,0 +1,84 @@
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From a004ee350177ece3c059831ea49293d62aea7ca6 Mon Sep 17 00:00:00 2001
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From: Icenowy Zheng <icenowy@aosc.xyz>
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Date: Tue, 22 Nov 2016 23:58:29 +0800
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Subject: arm64: dts: allwinner: add USB1-related nodes of Allwinner A64
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Allwinner A64 have two HCI USB controllers, a OTG controller and a USB
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PHY device which have two ports. One of the port is wired to both a HCI
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USB controller and the OTG controller, which is currently not supported.
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The another one is only wired to a HCI controller, and the device node of
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OHCI/EHCI controller of the port can be added now.
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Also the A64 USB PHY device node is also added for the HCI controllers to
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work.
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Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 46 +++++++++++++++++++++++++++
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1 file changed, 46 insertions(+)
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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@@ -42,8 +42,10 @@
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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+#include <dt-bindings/clock/sun50i-a64-ccu.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/sun4i-a10.h>
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+#include <dt-bindings/reset/sun50i-a64-ccu.h>
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/ {
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interrupt-parent = <&gic>;
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@@ -120,6 +122,50 @@
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#size-cells = <1>;
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ranges;
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+ usbphy: phy@01c19400 {
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+ compatible = "allwinner,sun50i-a64-usb-phy";
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+ reg = <0x01c19400 0x14>,
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+ <0x01c1b800 0x4>;
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+ reg-names = "phy_ctrl",
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+ "pmu1";
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+ clocks = <&ccu CLK_USB_PHY0>,
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+ <&ccu CLK_USB_PHY1>;
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+ clock-names = "usb0_phy",
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+ "usb1_phy";
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+ resets = <&ccu RST_USB_PHY0>,
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+ <&ccu RST_USB_PHY1>;
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+ reset-names = "usb0_reset",
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+ "usb1_reset";
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+ status = "disabled";
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+ #phy-cells = <1>;
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+ };
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+
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+ ehci1: usb@01c1b000 {
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+ compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
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+ reg = <0x01c1b000 0x100>;
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+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_OHCI1>,
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+ <&ccu CLK_BUS_EHCI1>,
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+ <&ccu CLK_USB_OHCI1>;
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+ resets = <&ccu RST_BUS_OHCI1>,
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+ <&ccu RST_BUS_EHCI1>;
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+ phys = <&usbphy 1>;
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+ phy-names = "usb";
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+ status = "disabled";
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+ };
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+
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+ ohci1: usb@01c1b400 {
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+ compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
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+ reg = <0x01c1b400 0x100>;
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+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_OHCI1>,
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+ <&ccu CLK_USB_OHCI1>;
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+ resets = <&ccu RST_BUS_OHCI1>;
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+ phys = <&usbphy 1>;
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+ phy-names = "usb";
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+ status = "disabled";
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+ };
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+
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ccu: clock@01c20000 {
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compatible = "allwinner,sun50i-a64-ccu";
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reg = <0x01c20000 0x400>;
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@ -0,0 +1,40 @@
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From ac93c09cdbaf1229c21f67a5db1c3c6df7d503e5 Mon Sep 17 00:00:00 2001
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From: Icenowy Zheng <icenowy@aosc.xyz>
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Date: Tue, 22 Nov 2016 23:58:30 +0800
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Subject: arm64: dts: allwinner: sort the nodes in sun50i-a64-pine64.dts
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In this dts file, uart0 node is put before i2c1.
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Move the uart0 node to the end to satisfy alphebetical order.
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Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 12 ++++++------
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1 file changed, 6 insertions(+), 6 deletions(-)
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
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@@ -57,12 +57,6 @@
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};
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};
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-&uart0 {
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- pinctrl-names = "default";
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- pinctrl-0 = <&uart0_pins_a>;
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- status = "okay";
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-};
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-
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins>;
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@@ -72,3 +66,9 @@
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&i2c1_pins {
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bias-pull-up;
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};
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+
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+&uart0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart0_pins_a>;
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+ status = "okay";
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+};
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@ -0,0 +1,47 @@
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From d49f9dbc8f0c4521fa56477d051a3bd1158f2595 Mon Sep 17 00:00:00 2001
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From: Icenowy Zheng <icenowy@aosc.xyz>
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Date: Tue, 22 Nov 2016 23:58:31 +0800
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Subject: arm64: dts: allwinner: enable EHCI1, OHCI1 and USB PHY nodes in
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Pine64
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Pine64 have two USB Type-A ports, which are wired to the two ports of
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A64 USB PHY, and the lower port is the EHCI/OHCI1 port.
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Enable the necessary nodes to enable the lower USB port to work.
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Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 12 ++++++++++++
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1 file changed, 12 insertions(+)
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
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@@ -57,6 +57,10 @@
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};
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};
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+&ehci1 {
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+ status = "okay";
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+};
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+
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins>;
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@@ -67,8 +71,16 @@
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bias-pull-up;
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};
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+&ohci1 {
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+ status = "okay";
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+};
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+
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins_a>;
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status = "okay";
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};
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+
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+&usbphy {
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+ status = "okay";
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+};
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@ -0,0 +1,42 @@
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From 972a3ecdf27f3ebdd1ce0dccd1b548ef3c04b8ed Mon Sep 17 00:00:00 2001
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From: Icenowy Zheng <icenowy@aosc.xyz>
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Date: Wed, 23 Nov 2016 00:59:01 +0800
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Subject: arm64: dts: add MUSB node to Allwinner A64 dtsi
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Allwinner A64 SoC has a MUSB controller like the one in A33, so add
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a node for it, just use the compatible of A33 MUSB.
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Host mode is tested to work properly on Pine64 and will be added into
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the device tree of Pine64 in next patch.
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Peripheral mode is also tested on Pine64, by changing dr_mode property
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of usb_otg node and use a non-standard USB Type-A to Type-A cable.
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Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 13 +++++++++++++
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1 file changed, 13 insertions(+)
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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@@ -122,6 +122,19 @@
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#size-cells = <1>;
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ranges;
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+ usb_otg: usb@01c19000 {
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+ compatible = "allwinner,sun8i-a33-musb";
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+ reg = <0x01c19000 0x0400>;
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+ clocks = <&ccu CLK_BUS_OTG>;
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+ resets = <&ccu RST_BUS_OTG>;
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+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "mc";
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+ phys = <&usbphy 0>;
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+ phy-names = "usb";
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+ extcon = <&usbphy 0>;
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+ status = "disabled";
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+ };
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+
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usbphy: phy@01c19400 {
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compatible = "allwinner,sun50i-a64-usb-phy";
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reg = <0x01c19400 0x14>,
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@ -0,0 +1,32 @@
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From f57e8384c5d2417fd8707c577d8e622fc1570b6c Mon Sep 17 00:00:00 2001
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From: Icenowy Zheng <icenowy@aosc.xyz>
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Date: Wed, 23 Nov 2016 00:59:02 +0800
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Subject: arm64: dts: enable the MUSB controller of Pine64 in host-only mode
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A64 has a MUSB controller wired to the USB PHY 0, which is connected
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to the upper USB Type-A port of Pine64.
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As the port is a Type-A female port, enable it in host-only mode in the
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device tree, which makes devices with USB Type-A male port can work on
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this port (which is originally designed by Pine64 team).
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Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 5 +++++
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1 file changed, 5 insertions(+)
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
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@@ -81,6 +81,11 @@
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status = "okay";
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};
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+&usb_otg {
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+ dr_mode = "host";
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+ status = "okay";
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+};
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+
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&usbphy {
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status = "okay";
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};
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@ -0,0 +1,31 @@
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From 4f9758302ccaf753cd4ba6a5eb740392a4d24773 Mon Sep 17 00:00:00 2001
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From: Chen-Yu Tsai <wens@csie.org>
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Date: Tue, 24 Jan 2017 10:32:29 +0800
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Subject: arm64: dts: allwinner: Remove no longer used pinctrl/sun4i-a10.h
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header
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All dts files for the sunxi platform have been switched to the generic
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pinconf bindings. As a result, the sunxi specific pinctrl macros are
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no longer used.
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Remove the #include entry with the following command:
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sed -i -e '/pinctrl\/sun4i-a10.h/D' \
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arch/arm64/boot/dts/allwinner/*.dts?
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Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 -
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1 file changed, 1 deletion(-)
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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@@ -44,7 +44,6 @@
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#include <dt-bindings/clock/sun50i-a64-ccu.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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-#include <dt-bindings/pinctrl/sun4i-a10.h>
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#include <dt-bindings/reset/sun50i-a64-ccu.h>
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/ {
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@ -0,0 +1,69 @@
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From f3dff3478a8a7b09f9a92023955a151584658893 Mon Sep 17 00:00:00 2001
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From: Andre Przywara <andre.przywara@arm.com>
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Date: Thu, 6 Oct 2016 02:25:22 +0100
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Subject: arm64: allwinner: a64: Add MMC nodes
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The A64 has 3 MMC controllers, one of them being especially targeted to
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eMMC. Among other things, it has a data strobe signal and a 8 bits data
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width.
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The two other are more usual controllers that will have a 4 bits width at
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most and no data strobe signal, which limits it to more usual SD or MMC
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peripherals.
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Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Tested-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
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Acked-by: Chen-Yu Tsai <wens@csie.org>
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---
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arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 39 +++++++++++++++++++++++++++
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1 file changed, 39 insertions(+)
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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@@ -121,6 +121,45 @@
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#size-cells = <1>;
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ranges;
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+ mmc0: mmc@1c0f000 {
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+ compatible = "allwinner,sun50i-a64-mmc";
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+ reg = <0x01c0f000 0x1000>;
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+ clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
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+ clock-names = "ahb", "mmc";
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+ resets = <&ccu RST_BUS_MMC0>;
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+ reset-names = "ahb";
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+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ mmc1: mmc@1c10000 {
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+ compatible = "allwinner,sun50i-a64-mmc";
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+ reg = <0x01c10000 0x1000>;
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+ clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
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+ clock-names = "ahb", "mmc";
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+ resets = <&ccu RST_BUS_MMC1>;
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+ reset-names = "ahb";
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+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ mmc2: mmc@1c11000 {
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+ compatible = "allwinner,sun50i-a64-emmc";
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+ reg = <0x01c11000 0x1000>;
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+ clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
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+ clock-names = "ahb", "mmc";
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+ resets = <&ccu RST_BUS_MMC2>;
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+ reset-names = "ahb";
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+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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usb_otg: usb@01c19000 {
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compatible = "allwinner,sun8i-a33-musb";
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reg = <0x01c19000 0x0400>;
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@ -0,0 +1,50 @@
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From a3e8f4926248b3c12933aacec4432e9b6de004bb Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime.ripard@free-electrons.com>
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Date: Mon, 9 Jan 2017 16:39:15 +0100
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Subject: arm64: allwinner: a64: Add MMC pinctrl nodes
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The A64 only has a single set of pins for each MMC controller. Since we
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already have boards that require all of them, let's add them to the DTSI.
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Reviewed-by: Andre Przywara <andre.przywara@arm.com>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Tested-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
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Acked-by: Chen-Yu Tsai <wens@csie.org>
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---
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arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 25 +++++++++++++++++++++++++
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1 file changed, 25 insertions(+)
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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@@ -243,6 +243,31 @@
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function = "i2c1";
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};
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+ mmc0_pins: mmc0-pins {
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+ pins = "PF0", "PF1", "PF2", "PF3",
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+ "PF4", "PF5";
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+ function = "mmc0";
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+ drive-strength = <30>;
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+ bias-pull-up;
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+ };
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+
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+ mmc1_pins: mmc1-pins {
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+ pins = "PG0", "PG1", "PG2", "PG3",
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+ "PG4", "PG5";
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+ function = "mmc1";
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+ drive-strength = <30>;
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+ bias-pull-up;
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+ };
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+
|
||||
+ mmc2_pins: mmc2-pins {
|
||||
+ pins = "PC1", "PC5", "PC6", "PC8", "PC9",
|
||||
+ "PC10","PC11", "PC12", "PC13",
|
||||
+ "PC14", "PC15", "PC16";
|
||||
+ function = "mmc2";
|
||||
+ drive-strength = <30>;
|
||||
+ bias-pull-up;
|
||||
+ };
|
||||
+
|
||||
uart0_pins_a: uart0@0 {
|
||||
pins = "PB8", "PB9";
|
||||
function = "uart0";
|
||||
@ -0,0 +1,62 @@
|
||||
From ebe3ae29c6314217edf40d9ee23c36d610ff0fb8 Mon Sep 17 00:00:00 2001
|
||||
From: Andre Przywara <andre.przywara@arm.com>
|
||||
Date: Tue, 10 Jan 2017 01:22:31 +0000
|
||||
Subject: arm64: allwinner: pine64: add MMC support
|
||||
|
||||
All Pine64 boards connect an micro-SD card slot to the first MMC
|
||||
controller.
|
||||
Enable the respective DT node and specify the (always-on) regulator
|
||||
and card-detect pin.
|
||||
As a micro-SD slot does not feature a write-protect switch, we disable
|
||||
this feature.
|
||||
|
||||
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
|
||||
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
Acked-by: Chen-Yu Tsai <wens@csie.org>
|
||||
---
|
||||
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 20 ++++++++++++++++++++
|
||||
1 file changed, 20 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
|
||||
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
|
||||
@@ -44,6 +44,8 @@
|
||||
|
||||
#include "sun50i-a64.dtsi"
|
||||
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+
|
||||
/ {
|
||||
model = "Pine64";
|
||||
compatible = "pine64,pine64", "allwinner,sun50i-a64";
|
||||
@@ -55,6 +57,13 @@
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
+
|
||||
+ reg_vcc3v3: vcc3v3 {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc3v3";
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ };
|
||||
};
|
||||
|
||||
&ehci1 {
|
||||
@@ -71,6 +80,17 @@
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
+&mmc0 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&mmc0_pins>;
|
||||
+ vmmc-supply = <®_vcc3v3>;
|
||||
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
|
||||
+ cd-inverted;
|
||||
+ disable-wp;
|
||||
+ bus-width = <4>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&ohci1 {
|
||||
status = "okay";
|
||||
};
|
||||
@ -0,0 +1,35 @@
|
||||
From e7ba733d32cc9487b62b07219ad911c77764a681 Mon Sep 17 00:00:00 2001
|
||||
From: Andre Przywara <andre.przywara@arm.com>
|
||||
Date: Tue, 10 Jan 2017 01:22:32 +0000
|
||||
Subject: arm64: allwinner: a64: add UART1 pin nodes
|
||||
|
||||
On many boards UART1 connects to a Bluetooth chip, so add the pinctrl
|
||||
nodes for the only pins providing access to that UART. That includes
|
||||
those pins for hardware flow control (RTS/CTS).
|
||||
|
||||
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
|
||||
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
Acked-by: Chen-Yu Tsai <wens@csie.org>
|
||||
---
|
||||
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 10 ++++++++++
|
||||
1 file changed, 10 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
||||
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
||||
@@ -272,6 +272,16 @@
|
||||
pins = "PB8", "PB9";
|
||||
function = "uart0";
|
||||
};
|
||||
+
|
||||
+ uart1_pins: uart1_pins {
|
||||
+ pins = "PG6", "PG7";
|
||||
+ function = "uart1";
|
||||
+ };
|
||||
+
|
||||
+ uart1_rts_cts_pins: uart1_rts_cts_pins {
|
||||
+ pins = "PG8", "PG9";
|
||||
+ function = "uart1";
|
||||
+ };
|
||||
};
|
||||
|
||||
uart0: serial@1c28000 {
|
||||
@ -0,0 +1,52 @@
|
||||
From 791a9e001d3ba3b552888b0bf3c592a50b71f57e Mon Sep 17 00:00:00 2001
|
||||
From: Icenowy Zheng <icenowy@aosc.xyz>
|
||||
Date: Tue, 4 Apr 2017 17:50:58 +0800
|
||||
Subject: arm64: allwinner: a64: add r_ccu node
|
||||
|
||||
A64 SoC have a CCU (r_ccu) in PRCM block.
|
||||
|
||||
Add the device node for it.
|
||||
|
||||
The mux 3 of R_CCU is an internal oscillator, which is 16MHz according
|
||||
to the user manual, and has only 30% accuracy based on our experience
|
||||
on older SoCs. The real mesaured value of it on two Pine64 boards is
|
||||
around 11MHz, which is around 70% of 16MHz.
|
||||
|
||||
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
|
||||
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
---
|
||||
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 17 +++++++++++++++++
|
||||
1 file changed, 17 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
||||
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
||||
@@ -98,6 +98,14 @@
|
||||
clock-output-names = "osc32k";
|
||||
};
|
||||
|
||||
+ iosc: internal-osc-clk {
|
||||
+ #clock-cells = <0>;
|
||||
+ compatible = "fixed-clock";
|
||||
+ clock-frequency = <16000000>;
|
||||
+ clock-accuracy = <300000000>;
|
||||
+ clock-output-names = "iosc";
|
||||
+ };
|
||||
+
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
@@ -389,5 +397,14 @@
|
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
+
|
||||
+ r_ccu: clock@1f01400 {
|
||||
+ compatible = "allwinner,sun50i-a64-r-ccu";
|
||||
+ reg = <0x01f01400 0x100>;
|
||||
+ clocks = <&osc24M>, <&osc32k>, <&iosc>;
|
||||
+ clock-names = "hosc", "losc", "iosc";
|
||||
+ #clock-cells = <1>;
|
||||
+ #reset-cells = <1>;
|
||||
+ };
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,35 @@
|
||||
From ec4279053a6434f685246e022be95d2a62f8c608 Mon Sep 17 00:00:00 2001
|
||||
From: Icenowy Zheng <icenowy@aosc.xyz>
|
||||
Date: Tue, 4 Apr 2017 17:51:00 +0800
|
||||
Subject: arm64: allwinner: a64: add R_PIO pinctrl node
|
||||
|
||||
Allwinner A64 have a dedicated pin controller to manage the PL pin bank.
|
||||
As the driver and the required clock support are added, add the device
|
||||
node for it.
|
||||
|
||||
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
|
||||
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
---
|
||||
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 12 ++++++++++++
|
||||
1 file changed, 12 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
||||
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
||||
@@ -406,5 +406,17 @@
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
+
|
||||
+ r_pio: pinctrl@01f02c00 {
|
||||
+ compatible = "allwinner,sun50i-a64-r-pinctrl";
|
||||
+ reg = <0x01f02c00 0x400>;
|
||||
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>;
|
||||
+ clock-names = "apb", "hosc", "losc";
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <3>;
|
||||
+ interrupt-controller;
|
||||
+ #interrupt-cells = <3>;
|
||||
+ };
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,29 @@
|
||||
From 0d98479738b950e30bb4f782d60099d44076ad67 Mon Sep 17 00:00:00 2001
|
||||
From: Icenowy Zheng <icenowy@aosc.io>
|
||||
Date: Wed, 5 Apr 2017 22:30:34 +0800
|
||||
Subject: arm64: allwinner: a64: add pmu0 regs for USB PHY
|
||||
|
||||
The USB PHY in A64 has a "pmu0" region, which controls the EHCI/OHCI
|
||||
controller pair that can be connected to the PHY0.
|
||||
|
||||
Add the MMIO region for PHY node.
|
||||
|
||||
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
|
||||
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
---
|
||||
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
||||
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
||||
@@ -184,8 +184,10 @@
|
||||
usbphy: phy@01c19400 {
|
||||
compatible = "allwinner,sun50i-a64-usb-phy";
|
||||
reg = <0x01c19400 0x14>,
|
||||
+ <0x01c1a800 0x4>,
|
||||
<0x01c1b800 0x4>;
|
||||
reg-names = "phy_ctrl",
|
||||
+ "pmu0",
|
||||
"pmu1";
|
||||
clocks = <&ccu CLK_USB_PHY0>,
|
||||
<&ccu CLK_USB_PHY1>;
|
||||
@ -0,0 +1,32 @@
|
||||
From f74994a94063bc85ac1d6ad677ed06b5279c101f Mon Sep 17 00:00:00 2001
|
||||
From: Chen-Yu Tsai <wens@csie.org>
|
||||
Date: Wed, 31 May 2017 15:58:24 +0800
|
||||
Subject: arm64: allwinner: a64: Add PLL_PERIPH0 clock to the R_CCU
|
||||
|
||||
The AR100 clock within the R_CCU (PRCM) has the PLL_PERIPH0 as one of
|
||||
its parents.
|
||||
|
||||
This adds the reference in the device tree describing this relationship.
|
||||
This patch uses a raw number for the clock index to ease merging by
|
||||
avoiding cross tree dependencies.
|
||||
|
||||
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
|
||||
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
---
|
||||
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 5 +++--
|
||||
1 file changed, 3 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
||||
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
||||
@@ -403,8 +403,9 @@
|
||||
r_ccu: clock@1f01400 {
|
||||
compatible = "allwinner,sun50i-a64-r-ccu";
|
||||
reg = <0x01f01400 0x100>;
|
||||
- clocks = <&osc24M>, <&osc32k>, <&iosc>;
|
||||
- clock-names = "hosc", "losc", "iosc";
|
||||
+ clocks = <&osc24M>, <&osc32k>, <&iosc>,
|
||||
+ <&ccu 11>;
|
||||
+ clock-names = "hosc", "losc", "iosc", "pll-periph";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
Loading…
Reference in New Issue