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@ -16,7 +16,7 @@
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
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@@ -570,7 +572,9 @@ static void _tw32_flush(struct tg3 *tp,
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@@ -571,7 +573,9 @@ static void _tw32_flush(struct tg3 *tp,
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static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
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{
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tp->write32_mbox(tp, off, val);
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@ -27,7 +27,7 @@
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tp->read32_mbox(tp, off);
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}
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@@ -580,7 +584,8 @@ static void tg3_write32_tx_mbox(struct t
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@@ -581,7 +585,8 @@ static void tg3_write32_tx_mbox(struct t
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writel(val, mbox);
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if (tg3_flag(tp, TXD_MBOX_HWBUG))
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writel(val, mbox);
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@ -37,7 +37,7 @@
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readl(mbox);
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}
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@@ -1088,7 +1093,8 @@ static void tg3_switch_clocks(struct tg3
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@@ -1089,7 +1094,8 @@ static void tg3_switch_clocks(struct tg3
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#define PHY_BUSY_LOOPS 5000
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@ -47,7 +47,7 @@
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{
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u32 frame_val;
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unsigned int loops;
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@@ -1104,7 +1110,7 @@ static int tg3_readphy(struct tg3 *tp, i
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@@ -1105,7 +1111,7 @@ static int tg3_readphy(struct tg3 *tp, i
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*val = 0x0;
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@ -56,7 +56,7 @@
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MI_COM_PHY_ADDR_MASK);
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frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
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MI_COM_REG_ADDR_MASK);
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@@ -1141,7 +1147,13 @@ static int tg3_readphy(struct tg3 *tp, i
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@@ -1142,7 +1148,13 @@ static int tg3_readphy(struct tg3 *tp, i
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return ret;
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}
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@ -71,7 +71,7 @@
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{
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u32 frame_val;
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unsigned int loops;
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@@ -1159,7 +1171,7 @@ static int tg3_writephy(struct tg3 *tp,
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@@ -1160,7 +1172,7 @@ static int tg3_writephy(struct tg3 *tp,
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tg3_ape_lock(tp, tp->phy_ape_lock);
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@ -80,7 +80,7 @@
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MI_COM_PHY_ADDR_MASK);
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frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
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MI_COM_REG_ADDR_MASK);
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@@ -1194,6 +1206,11 @@ static int tg3_writephy(struct tg3 *tp,
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@@ -1195,6 +1207,11 @@ static int tg3_writephy(struct tg3 *tp,
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return ret;
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}
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@ -92,7 +92,7 @@
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static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
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{
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int err;
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@@ -1778,6 +1795,11 @@ static int tg3_poll_fw(struct tg3 *tp)
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@@ -1779,6 +1796,11 @@ static int tg3_poll_fw(struct tg3 *tp)
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int i;
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u32 val;
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@ -104,7 +104,7 @@
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
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/* Wait up to 20ms for init done. */
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for (i = 0; i < 200; i++) {
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@@ -3443,6 +3465,13 @@ static int tg3_halt_cpu(struct tg3 *tp,
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@@ -3444,6 +3466,13 @@ static int tg3_halt_cpu(struct tg3 *tp,
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tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
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udelay(10);
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} else {
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@ -118,7 +118,7 @@
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for (i = 0; i < 10000; i++) {
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tw32(offset + CPU_STATE, 0xffffffff);
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tw32(offset + CPU_MODE, CPU_MODE_HALT);
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@@ -3910,8 +3939,9 @@ static int tg3_power_down_prepare(struct
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@@ -3911,8 +3940,9 @@ static int tg3_power_down_prepare(struct
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tg3_frob_aux_power(tp, true);
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/* Workaround for unstable PLL clock */
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@ -130,7 +130,7 @@
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u32 val = tr32(0x7d00);
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val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
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@@ -4439,6 +4469,15 @@ relink:
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@@ -4440,6 +4470,15 @@ relink:
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if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
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tg3_phy_copper_begin(tp);
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@ -146,7 +146,7 @@
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tg3_readphy(tp, MII_BMSR, &bmsr);
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if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
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(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
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@@ -4457,6 +4496,26 @@ relink:
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@@ -4458,6 +4497,26 @@ relink:
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else
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tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
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@ -173,7 +173,7 @@
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tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
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if (tp->link_config.active_duplex == DUPLEX_HALF)
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tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
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@@ -8435,6 +8494,16 @@ static int tg3_chip_reset(struct tg3 *tp
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@@ -8436,6 +8495,16 @@ static int tg3_chip_reset(struct tg3 *tp
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tw32(0x5000, 0x400);
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}
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@ -190,7 +190,7 @@
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tw32(GRC_MODE, tp->grc_mode);
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if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
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@@ -10068,6 +10137,11 @@ static void tg3_timer(unsigned long __op
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@@ -10084,6 +10153,11 @@ static void tg3_timer(unsigned long __op
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tg3_flag(tp, 57765_CLASS))
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tg3_chk_missed_msi(tp);
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@ -202,7 +202,7 @@
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if (!tg3_flag(tp, TAGGED_STATUS)) {
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/* All of this garbage is because when using non-tagged
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* IRQ status the mailbox/status_block protocol the chip
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@@ -12941,7 +13015,8 @@ static int tg3_ioctl(struct net_device *
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@@ -12957,7 +13031,8 @@ static int tg3_ioctl(struct net_device *
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return -EAGAIN;
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spin_lock_bh(&tp->lock);
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@ -212,7 +212,7 @@
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spin_unlock_bh(&tp->lock);
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data->val_out = mii_regval;
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@@ -12957,7 +13032,8 @@ static int tg3_ioctl(struct net_device *
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@@ -12973,7 +13048,8 @@ static int tg3_ioctl(struct net_device *
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return -EAGAIN;
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spin_lock_bh(&tp->lock);
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@ -222,7 +222,7 @@
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spin_unlock_bh(&tp->lock);
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return err;
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@@ -13810,6 +13886,14 @@ static void tg3_get_5720_nvram_info(stru
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@@ -13826,6 +13902,14 @@ static void tg3_get_5720_nvram_info(stru
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/* Chips other than 5700/5701 use the NVRAM for fetching info. */
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static void tg3_nvram_init(struct tg3 *tp)
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{
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@ -237,7 +237,7 @@
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tw32_f(GRC_EEPROM_ADDR,
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(EEPROM_ADDR_FSM_RESET |
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(EEPROM_DEFAULT_CLOCK_PERIOD <<
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@@ -14302,10 +14386,19 @@ static int tg3_phy_probe(struct tg3 *tp)
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@@ -14318,10 +14402,19 @@ static int tg3_phy_probe(struct tg3 *tp)
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* subsys device table.
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*/
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p = tg3_lookup_by_subsys(tp);
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@ -259,7 +259,7 @@
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if (!tp->phy_id ||
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tp->phy_id == TG3_PHY_ID_BCM8002)
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tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
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@@ -15353,6 +15446,11 @@ static int tg3_get_invariants(struct tg3
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@@ -15369,6 +15462,11 @@ static int tg3_get_invariants(struct tg3
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}
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}
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@ -271,7 +271,7 @@
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/* Get eeprom hw config before calling tg3_set_power_state().
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* In particular, the TG3_FLAG_IS_NIC flag must be
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* determined before calling tg3_set_power_state() so that
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@@ -15686,12 +15784,19 @@ static int tg3_get_device_address(struct
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@@ -15702,12 +15800,19 @@ static int tg3_get_device_address(struct
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struct net_device *dev = tp->dev;
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u32 hi, lo, mac_offset;
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int addr_ok = 0;
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@ -291,7 +291,7 @@
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mac_offset = 0x7c;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
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tg3_flag(tp, 5780_CLASS)) {
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@@ -16052,6 +16157,8 @@ static int tg3_test_dma(struct tg3 *tp)
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@@ -16068,6 +16173,8 @@ static int tg3_test_dma(struct tg3 *tp)
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tp->dma_rwctrl |= 0x001b000f;
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}
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}
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@ -300,7 +300,7 @@
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
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@@ -16396,6 +16503,18 @@ static int tg3_init_one(struct pci_dev *
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@@ -16412,6 +16519,18 @@ static int tg3_init_one(struct pci_dev *
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else
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tp->msg_enable = TG3_DEF_MSG_ENABLE;
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@ -321,7 +321,7 @@
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* setting below.
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--- a/drivers/net/ethernet/broadcom/tg3.h
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+++ b/drivers/net/ethernet/broadcom/tg3.h
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@@ -3030,6 +3030,11 @@ enum TG3_FLAGS {
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@@ -3032,6 +3032,11 @@ enum TG3_FLAGS {
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TG3_FLAG_57765_PLUS,
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TG3_FLAG_57765_CLASS,
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TG3_FLAG_5717_PLUS,
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Gabor Juhos
11 years ago