ar71xx: add v4.14 support
adds v4.14 patches for testing but leaves v4.9 as default for now. Signed-off-by: John Crispin <john@phrozen.org>v19.07.3_mercusys_ac12_duma
John Crispin
6 years ago
parent
e5f56c07d7
commit
318e19ba67
@ -0,0 +1,485 @@
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CONFIG_AG71XX=y
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CONFIG_AG71XX_AR8216_SUPPORT=y
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# CONFIG_AG71XX_DEBUG is not set
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# CONFIG_AG71XX_DEBUG_FS is not set
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CONFIG_AR8216_PHY=y
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CONFIG_AR8216_PHY_LEDS=y
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CONFIG_ARCH_BINFMT_ELF_STATE=y
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CONFIG_ARCH_CLOCKSOURCE_DATA=y
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CONFIG_ARCH_DISCARD_MEMBLOCK=y
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CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
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# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set
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CONFIG_ARCH_HAS_RESET_CONTROLLER=y
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# CONFIG_ARCH_HAS_SG_CHAIN is not set
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
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CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
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CONFIG_ARCH_SUPPORTS_UPROBES=y
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CONFIG_ARCH_SUSPEND_POSSIBLE=y
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CONFIG_ARCH_USE_BUILTIN_BSWAP=y
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CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
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CONFIG_AT803X_PHY=y
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CONFIG_ATH79=y
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# CONFIG_ATH79_DEV_AP9X_PCI is not set
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# CONFIG_ATH79_DEV_DSA is not set
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# CONFIG_ATH79_DEV_ETH is not set
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# CONFIG_ATH79_DEV_GPIO_BUTTONS is not set
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# CONFIG_ATH79_DEV_LEDS_GPIO is not set
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# CONFIG_ATH79_DEV_M25P80 is not set
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# CONFIG_ATH79_DEV_SPI is not set
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# CONFIG_ATH79_DEV_USB is not set
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# CONFIG_ATH79_MACH_A60 is not set
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# CONFIG_ATH79_MACH_ALFA_AP120C is not set
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# CONFIG_ATH79_MACH_ALFA_AP96 is not set
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# CONFIG_ATH79_MACH_ALFA_NX is not set
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# CONFIG_ATH79_MACH_ALL0258N is not set
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# CONFIG_ATH79_MACH_ALL0315N is not set
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# CONFIG_ATH79_MACH_ANTMINER_S1 is not set
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# CONFIG_ATH79_MACH_ANTMINER_S3 is not set
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# CONFIG_ATH79_MACH_ANTROUTER_R1 is not set
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# CONFIG_ATH79_MACH_AP121 is not set
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# CONFIG_ATH79_MACH_AP121F is not set
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# CONFIG_ATH79_MACH_AP132 is not set
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# CONFIG_ATH79_MACH_AP136 is not set
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# CONFIG_ATH79_MACH_AP143 is not set
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# CONFIG_ATH79_MACH_AP147 is not set
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# CONFIG_ATH79_MACH_AP152 is not set
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# CONFIG_ATH79_MACH_AP531B0 is not set
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# CONFIG_ATH79_MACH_AP81 is not set
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# CONFIG_ATH79_MACH_AP90Q is not set
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# CONFIG_ATH79_MACH_AP91_5G is not set
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# CONFIG_ATH79_MACH_AP96 is not set
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# CONFIG_ATH79_MACH_ARCHER_C25_V1 is not set
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# CONFIG_ATH79_MACH_ARCHER_C58_V1 is not set
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# CONFIG_ATH79_MACH_ARCHER_C59_V1 is not set
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# CONFIG_ATH79_MACH_ARCHER_C59_V2 is not set
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# CONFIG_ATH79_MACH_ARCHER_C60_V1 is not set
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# CONFIG_ATH79_MACH_ARCHER_C60_V2 is not set
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# CONFIG_ATH79_MACH_ARCHER_C7 is not set
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# CONFIG_ATH79_MACH_ARDUINO_YUN is not set
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# CONFIG_ATH79_MACH_AW_NR580 is not set
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# CONFIG_ATH79_MACH_BHR_4GRV2 is not set
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# CONFIG_ATH79_MACH_BHU_BXU2000N2_A is not set
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# CONFIG_ATH79_MACH_BSB is not set
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# CONFIG_ATH79_MACH_C55 is not set
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# CONFIG_ATH79_MACH_C60 is not set
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# CONFIG_ATH79_MACH_CAP324 is not set
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# CONFIG_ATH79_MACH_CAP4200AG is not set
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# CONFIG_ATH79_MACH_CARAMBOLA2 is not set
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# CONFIG_ATH79_MACH_CF_E316N_V2 is not set
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# CONFIG_ATH79_MACH_CF_E320N_V2 is not set
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# CONFIG_ATH79_MACH_CF_E355AC is not set
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# CONFIG_ATH79_MACH_CF_E375AC is not set
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# CONFIG_ATH79_MACH_CF_E380AC_V1 is not set
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# CONFIG_ATH79_MACH_CF_E380AC_V2 is not set
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# CONFIG_ATH79_MACH_CF_E520N is not set
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# CONFIG_ATH79_MACH_CF_E530N is not set
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# CONFIG_ATH79_MACH_CPE505N is not set
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# CONFIG_ATH79_MACH_CPE510 is not set
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# CONFIG_ATH79_MACH_CPE830 is not set
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# CONFIG_ATH79_MACH_CPE870 is not set
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# CONFIG_ATH79_MACH_CR3000 is not set
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# CONFIG_ATH79_MACH_CR5000 is not set
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# CONFIG_ATH79_MACH_DAP_1330_A1 is not set
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# CONFIG_ATH79_MACH_DAP_2695_A1 is not set
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# CONFIG_ATH79_MACH_DB120 is not set
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# CONFIG_ATH79_MACH_DGL_5500_A1 is not set
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# CONFIG_ATH79_MACH_DHP_1565_A1 is not set
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# CONFIG_ATH79_MACH_DIR_505_A1 is not set
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# CONFIG_ATH79_MACH_DIR_600_A1 is not set
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# CONFIG_ATH79_MACH_DIR_615_C1 is not set
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# CONFIG_ATH79_MACH_DIR_615_I1 is not set
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# CONFIG_ATH79_MACH_DIR_825_B1 is not set
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# CONFIG_ATH79_MACH_DIR_825_C1 is not set
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# CONFIG_ATH79_MACH_DIR_869_A1 is not set
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# CONFIG_ATH79_MACH_DLAN_HOTSPOT is not set
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# CONFIG_ATH79_MACH_DLAN_PRO_1200_AC is not set
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# CONFIG_ATH79_MACH_DLAN_PRO_500_WP is not set
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# CONFIG_ATH79_MACH_DOMYWIFI_DW33D is not set
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# CONFIG_ATH79_MACH_DR342 is not set
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# CONFIG_ATH79_MACH_DR344 is not set
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# CONFIG_ATH79_MACH_DR531 is not set
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# CONFIG_ATH79_MACH_DRAGINO2 is not set
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# CONFIG_ATH79_MACH_E1700AC_V2 is not set
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# CONFIG_ATH79_MACH_E2100L is not set
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# CONFIG_ATH79_MACH_E558_V2 is not set
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# CONFIG_ATH79_MACH_E600G_V2 is not set
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# CONFIG_ATH79_MACH_E750A_V4 is not set
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# CONFIG_ATH79_MACH_E750G_V8 is not set
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# CONFIG_ATH79_MACH_EAP120 is not set
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# CONFIG_ATH79_MACH_EAP300V2 is not set
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# CONFIG_ATH79_MACH_EAP7660D is not set
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# CONFIG_ATH79_MACH_EL_M150 is not set
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# CONFIG_ATH79_MACH_EL_MINI is not set
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# CONFIG_ATH79_MACH_ENS202EXT is not set
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# CONFIG_ATH79_MACH_EPG5000 is not set
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# CONFIG_ATH79_MACH_ESR1750 is not set
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# CONFIG_ATH79_MACH_ESR900 is not set
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# CONFIG_ATH79_MACH_EW_BALIN is not set
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# CONFIG_ATH79_MACH_EW_DORIN is not set
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# CONFIG_ATH79_MACH_F9K1115V2 is not set
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# CONFIG_ATH79_MACH_FRITZ300E is not set
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# CONFIG_ATH79_MACH_FRITZ4020 is not set
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# CONFIG_ATH79_MACH_FRITZ450E is not set
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# CONFIG_ATH79_MACH_GL_AR150 is not set
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# CONFIG_ATH79_MACH_GL_AR300 is not set
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# CONFIG_ATH79_MACH_GL_AR300M is not set
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# CONFIG_ATH79_MACH_GL_AR750 is not set
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# CONFIG_ATH79_MACH_GL_AR750S is not set
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# CONFIG_ATH79_MACH_GL_DOMINO is not set
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# CONFIG_ATH79_MACH_GL_INET is not set
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# CONFIG_ATH79_MACH_GL_MIFI is not set
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# CONFIG_ATH79_MACH_GL_USB150 is not set
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# CONFIG_ATH79_MACH_GS_OOLITE_V1 is not set
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# CONFIG_ATH79_MACH_GS_OOLITE_V5_2 is not set
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# CONFIG_ATH79_MACH_HIVEAP_121 is not set
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# CONFIG_ATH79_MACH_HIWIFI_HC6361 is not set
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# CONFIG_ATH79_MACH_HORNET_UB is not set
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# CONFIG_ATH79_MACH_JA76PF is not set
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# CONFIG_ATH79_MACH_JWAP003 is not set
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# CONFIG_ATH79_MACH_JWAP230 is not set
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# CONFIG_ATH79_MACH_KOALA is not set
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# CONFIG_ATH79_MACH_LAN_TURTLE is not set
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# CONFIG_ATH79_MACH_LIMA is not set
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# CONFIG_ATH79_MACH_MC_MAC1200R is not set
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# CONFIG_ATH79_MACH_MR12 is not set
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# CONFIG_ATH79_MACH_MR16 is not set
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# CONFIG_ATH79_MACH_MR1750 is not set
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# CONFIG_ATH79_MACH_MR18 is not set
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# CONFIG_ATH79_MACH_MR600 is not set
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# CONFIG_ATH79_MACH_MR900 is not set
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# CONFIG_ATH79_MACH_MYNET_N600 is not set
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# CONFIG_ATH79_MACH_MYNET_N750 is not set
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# CONFIG_ATH79_MACH_MYNET_REXT is not set
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# CONFIG_ATH79_MACH_MZK_W04NU is not set
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# CONFIG_ATH79_MACH_MZK_W300NH is not set
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# CONFIG_ATH79_MACH_N5Q is not set
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# CONFIG_ATH79_MACH_NBG460N is not set
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# CONFIG_ATH79_MACH_NBG6716 is not set
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# CONFIG_ATH79_MACH_OM2P is not set
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# CONFIG_ATH79_MACH_OM5P is not set
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# CONFIG_ATH79_MACH_OM5P_AC is not set
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# CONFIG_ATH79_MACH_OM5P_ACv2 is not set
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# CONFIG_ATH79_MACH_OMY_G1 is not set
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# CONFIG_ATH79_MACH_OMY_X1 is not set
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# CONFIG_ATH79_MACH_ONION_OMEGA is not set
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# CONFIG_ATH79_MACH_PB42 is not set
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# CONFIG_ATH79_MACH_PB44 is not set
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# CONFIG_ATH79_MACH_PQI_AIR_PEN is not set
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# CONFIG_ATH79_MACH_QIHOO_C301 is not set
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# CONFIG_ATH79_MACH_R36A is not set
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# CONFIG_ATH79_MACH_R602N is not set
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# CONFIG_ATH79_MACH_R6100 is not set
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# CONFIG_ATH79_MACH_RAMBUTAN is not set
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# CONFIG_ATH79_MACH_RB2011 is not set
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# CONFIG_ATH79_MACH_RB4XX is not set
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# CONFIG_ATH79_MACH_RB750 is not set
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# CONFIG_ATH79_MACH_RB91X is not set
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# CONFIG_ATH79_MACH_RB922 is not set
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# CONFIG_ATH79_MACH_RB95X is not set
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# CONFIG_ATH79_MACH_RBSPI is not set
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# CONFIG_ATH79_MACH_RBSXTLITE is not set
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# CONFIG_ATH79_MACH_RE355 is not set
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# CONFIG_ATH79_MACH_RE450 is not set
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# CONFIG_ATH79_MACH_RME_EG200 is not set
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# CONFIG_ATH79_MACH_RUT9XX is not set
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# CONFIG_ATH79_MACH_RW2458N is not set
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# CONFIG_ATH79_MACH_SC1750 is not set
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# CONFIG_ATH79_MACH_SC300M is not set
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# CONFIG_ATH79_MACH_SC450 is not set
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# CONFIG_ATH79_MACH_SMART_300 is not set
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# CONFIG_ATH79_MACH_SOM9331 is not set
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# CONFIG_ATH79_MACH_SR3200 is not set
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# CONFIG_ATH79_MACH_T830 is not set
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# CONFIG_ATH79_MACH_TELLSTICK_ZNET_LITE is not set
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# CONFIG_ATH79_MACH_TEW_632BRP is not set
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# CONFIG_ATH79_MACH_TEW_673GRU is not set
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# CONFIG_ATH79_MACH_TEW_712BR is not set
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# CONFIG_ATH79_MACH_TEW_732BR is not set
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# CONFIG_ATH79_MACH_TEW_823DRU is not set
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# CONFIG_ATH79_MACH_TL_MR11U is not set
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# CONFIG_ATH79_MACH_TL_MR13U is not set
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# CONFIG_ATH79_MACH_TL_MR3020 is not set
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# CONFIG_ATH79_MACH_TL_MR3X20 is not set
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# CONFIG_ATH79_MACH_TL_MR6400 is not set
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# CONFIG_ATH79_MACH_TL_WA701ND_V2 is not set
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# CONFIG_ATH79_MACH_TL_WA7210N_V2 is not set
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# CONFIG_ATH79_MACH_TL_WA801ND_V3 is not set
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# CONFIG_ATH79_MACH_TL_WA830RE_V2 is not set
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# CONFIG_ATH79_MACH_TL_WA850RE_V2 is not set
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# CONFIG_ATH79_MACH_TL_WA855RE_V1 is not set
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# CONFIG_ATH79_MACH_TL_WA901ND is not set
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# CONFIG_ATH79_MACH_TL_WA901ND_V2 is not set
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# CONFIG_ATH79_MACH_TL_WA901ND_V4 is not set
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# CONFIG_ATH79_MACH_TL_WAX50RE is not set
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# CONFIG_ATH79_MACH_TL_WDR3320_V2 is not set
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# CONFIG_ATH79_MACH_TL_WDR3500 is not set
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# CONFIG_ATH79_MACH_TL_WDR4300 is not set
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# CONFIG_ATH79_MACH_TL_WDR6500_V2 is not set
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# CONFIG_ATH79_MACH_TL_WPA8630 is not set
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# CONFIG_ATH79_MACH_TL_WR1041N_V2 is not set
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# CONFIG_ATH79_MACH_TL_WR1043ND is not set
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# CONFIG_ATH79_MACH_TL_WR1043ND_V2 is not set
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# CONFIG_ATH79_MACH_TL_WR1043ND_V4 is not set
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# CONFIG_ATH79_MACH_TL_WR1043N_V5 is not set
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# CONFIG_ATH79_MACH_TL_WR2543N is not set
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# CONFIG_ATH79_MACH_TL_WR703N is not set
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# CONFIG_ATH79_MACH_TL_WR720N_V3 is not set
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# CONFIG_ATH79_MACH_TL_WR741ND is not set
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# CONFIG_ATH79_MACH_TL_WR741ND_V4 is not set
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# CONFIG_ATH79_MACH_TL_WR802N_V1 is not set
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# CONFIG_ATH79_MACH_TL_WR802N_V2 is not set
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# CONFIG_ATH79_MACH_TL_WR810N is not set
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# CONFIG_ATH79_MACH_TL_WR810N_V2 is not set
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# CONFIG_ATH79_MACH_TL_WR840N_V2 is not set
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# CONFIG_ATH79_MACH_TL_WR841N_V1 is not set
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# CONFIG_ATH79_MACH_TL_WR841N_V8 is not set
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# CONFIG_ATH79_MACH_TL_WR841N_V9 is not set
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# CONFIG_ATH79_MACH_TL_WR902AC_V1 is not set
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# CONFIG_ATH79_MACH_TL_WR940N_V4 is not set
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# CONFIG_ATH79_MACH_TL_WR941ND is not set
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# CONFIG_ATH79_MACH_TL_WR941ND_V6 is not set
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# CONFIG_ATH79_MACH_TL_WR942N_V1 is not set
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# CONFIG_ATH79_MACH_TS_D084 is not set
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# CONFIG_ATH79_MACH_TUBE2H is not set
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# CONFIG_ATH79_MACH_UBNT is not set
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# CONFIG_ATH79_MACH_UBNT_UNIFIAC is not set
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# CONFIG_ATH79_MACH_UBNT_XM is not set
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# CONFIG_ATH79_MACH_WAM250 is not set
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# CONFIG_ATH79_MACH_WEIO is not set
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# CONFIG_ATH79_MACH_WHR_HP_G300N is not set
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# CONFIG_ATH79_MACH_WI2A_AC200I is not set
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# CONFIG_ATH79_MACH_WIFI_PINEAPPLE_NANO is not set
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# CONFIG_ATH79_MACH_WLAE_AG300N is not set
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# CONFIG_ATH79_MACH_WLR8100 is not set
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# CONFIG_ATH79_MACH_WNDAP360 is not set
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# CONFIG_ATH79_MACH_WNDR3700 is not set
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# CONFIG_ATH79_MACH_WNDR4300 is not set
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# CONFIG_ATH79_MACH_WNR2000 is not set
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# CONFIG_ATH79_MACH_WNR2000_V3 is not set
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# CONFIG_ATH79_MACH_WNR2000_V4 is not set
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# CONFIG_ATH79_MACH_WNR2200 is not set
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# CONFIG_ATH79_MACH_WP543 is not set
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# CONFIG_ATH79_MACH_WPE72 is not set
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# CONFIG_ATH79_MACH_WPJ342 is not set
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# CONFIG_ATH79_MACH_WPJ344 is not set
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# CONFIG_ATH79_MACH_WPJ531 is not set
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# CONFIG_ATH79_MACH_WPJ558 is not set
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# CONFIG_ATH79_MACH_WPJ563 is not set
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# CONFIG_ATH79_MACH_WRT160NL is not set
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# CONFIG_ATH79_MACH_WRT400N is not set
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# CONFIG_ATH79_MACH_WRTNODE2Q is not set
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# CONFIG_ATH79_MACH_WZR_450HP2 is not set
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# CONFIG_ATH79_MACH_WZR_HP_AG300H is not set
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# CONFIG_ATH79_MACH_WZR_HP_G300NH is not set
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# CONFIG_ATH79_MACH_WZR_HP_G300NH2 is not set
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# CONFIG_ATH79_MACH_WZR_HP_G450H is not set
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# CONFIG_ATH79_MACH_XD3200 is not set
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# CONFIG_ATH79_MACH_Z1 is not set
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# CONFIG_ATH79_MACH_ZBT_WE1526 is not set
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# CONFIG_ATH79_MACH_ZCN_1523H is not set
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# CONFIG_ATH79_NVRAM is not set
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# CONFIG_ATH79_PCI_ATH9K_FIXUP is not set
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# CONFIG_ATH79_ROUTERBOOT is not set
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CONFIG_ATH79_WDT=y
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CONFIG_CEVT_R4K=y
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CONFIG_CLKDEV_LOOKUP=y
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CONFIG_CLONE_BACKWARDS=y
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CONFIG_CMDLINE="rootfstype=squashfs noinitrd"
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CONFIG_CMDLINE_BOOL=y
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# CONFIG_CMDLINE_OVERRIDE is not set
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# CONFIG_COMMON_CLK_BOSTON is not set
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CONFIG_COMMON_CLK=y
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CONFIG_CPU_BIG_ENDIAN=y
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CONFIG_CPU_GENERIC_DUMP_TLB=y
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CONFIG_CPU_HAS_PREFETCH=y
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CONFIG_CPU_HAS_RIXI=y
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CONFIG_CPU_HAS_SYNC=y
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CONFIG_CPU_MIPS32=y
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CONFIG_CPU_MIPS32_R2=y
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CONFIG_CPU_MIPSR2=y
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CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
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CONFIG_CPU_R4K_CACHE_TLB=y
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CONFIG_CPU_R4K_FPU=y
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CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
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CONFIG_CPU_SUPPORTS_HIGHMEM=y
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CONFIG_CPU_SUPPORTS_MSA=y
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CONFIG_CRYPTO_RNG2=y
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CONFIG_CRYPTO_WORKQUEUE=y
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CONFIG_CSRC_R4K=y
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CONFIG_DMA_NONCOHERENT=y
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CONFIG_EARLY_PRINTK=y
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CONFIG_ETHERNET_PACKET_MANGLE=y
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CONFIG_FIXED_PHY=y
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CONFIG_GENERIC_ATOMIC64=y
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_CMOS_UPDATE=y
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CONFIG_GENERIC_IO=y
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CONFIG_GENERIC_IRQ_CHIP=y
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CONFIG_GENERIC_IRQ_SHOW=y
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CONFIG_GENERIC_PCI_IOMAP=y
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CONFIG_GENERIC_SCHED_CLOCK=y
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||||
CONFIG_GENERIC_SMP_IDLE_THREAD=y
|
||||
CONFIG_GENERIC_TIME_VSYSCALL=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIOLIB_IRQCHIP=y
|
||||
CONFIG_GPIO_74X164=y
|
||||
CONFIG_GPIO_ATH79=y
|
||||
CONFIG_GPIO_GENERIC=y
|
||||
# CONFIG_GPIO_LATCH is not set
|
||||
CONFIG_GPIO_NXP_74HC153=y
|
||||
CONFIG_GPIO_PCF857X=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_HANDLE_DOMAIN_IRQ=y
|
||||
CONFIG_HARDWARE_WATCHPOINTS=y
|
||||
CONFIG_HAS_DMA=y
|
||||
CONFIG_HAS_IOMEM=y
|
||||
CONFIG_HAS_IOPORT_MAP=y
|
||||
# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
|
||||
# CONFIG_HAVE_ARCH_BITREVERSE is not set
|
||||
CONFIG_HAVE_ARCH_JUMP_LABEL=y
|
||||
CONFIG_HAVE_ARCH_KGDB=y
|
||||
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
|
||||
CONFIG_HAVE_ARCH_TRACEHOOK=y
|
||||
# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
|
||||
CONFIG_HAVE_CBPF_JIT=y
|
||||
CONFIG_HAVE_CC_STACKPROTECTOR=y
|
||||
CONFIG_HAVE_CLK=y
|
||||
CONFIG_HAVE_CLK_PREPARE=y
|
||||
CONFIG_HAVE_CONTEXT_TRACKING=y
|
||||
CONFIG_HAVE_C_RECORDMCOUNT=y
|
||||
CONFIG_HAVE_DEBUG_KMEMLEAK=y
|
||||
CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
|
||||
CONFIG_HAVE_DMA_API_DEBUG=y
|
||||
CONFIG_HAVE_DMA_CONTIGUOUS=y
|
||||
CONFIG_HAVE_DYNAMIC_FTRACE=y
|
||||
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
|
||||
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
|
||||
CONFIG_HAVE_FUNCTION_TRACER=y
|
||||
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
|
||||
CONFIG_HAVE_IDE=y
|
||||
CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
|
||||
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
|
||||
CONFIG_HAVE_KVM=y
|
||||
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
|
||||
CONFIG_HAVE_MEMBLOCK=y
|
||||
CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
|
||||
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
|
||||
CONFIG_HAVE_NET_DSA=y
|
||||
CONFIG_HAVE_OPROFILE=y
|
||||
CONFIG_HAVE_PERF_EVENTS=y
|
||||
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
|
||||
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
|
||||
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
|
||||
CONFIG_HZ_PERIODIC=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_ALGOBIT=y
|
||||
CONFIG_I2C_BOARDINFO=y
|
||||
CONFIG_I2C_GPIO=y
|
||||
CONFIG_IMAGE_CMDLINE_HACK=y
|
||||
CONFIG_INITRAMFS_ROOT_GID=0
|
||||
CONFIG_INITRAMFS_ROOT_UID=0
|
||||
CONFIG_INITRAMFS_SOURCE="../../root"
|
||||
CONFIG_INTEL_XWAY_PHY=y
|
||||
CONFIG_IP17XX_PHY=y
|
||||
CONFIG_IRQ_DOMAIN=y
|
||||
CONFIG_IRQ_FORCED_THREADING=y
|
||||
CONFIG_IRQ_MIPS_CPU=y
|
||||
CONFIG_IRQ_WORK=y
|
||||
CONFIG_LEDS_GPIO=y
|
||||
CONFIG_MARVELL_PHY=y
|
||||
CONFIG_MDIO_BITBANG=y
|
||||
CONFIG_MDIO_BOARDINFO=y
|
||||
CONFIG_MDIO_GPIO=y
|
||||
CONFIG_MICREL_PHY=y
|
||||
CONFIG_MIPS=y
|
||||
CONFIG_MIPS_ASID_BITS=8
|
||||
CONFIG_MIPS_ASID_SHIFT=0
|
||||
CONFIG_MIPS_CLOCK_VSYSCALL=y
|
||||
# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
|
||||
CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
|
||||
# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
|
||||
CONFIG_MIPS_L1_CACHE_SHIFT=5
|
||||
CONFIG_MIPS_MACHINE=y
|
||||
CONFIG_MIPS_SPRAM=y
|
||||
CONFIG_MODULES_USE_ELF_REL=y
|
||||
CONFIG_MTD_CFI_ADV_OPTIONS=y
|
||||
CONFIG_MTD_CFI_GEOMETRY=y
|
||||
# CONFIG_MTD_CFI_I2 is not set
|
||||
# CONFIG_MTD_CFI_INTELEXT is not set
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_CYBERTAN_PARTS=y
|
||||
CONFIG_MTD_M25P80=y
|
||||
# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
|
||||
# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
|
||||
CONFIG_MTD_MYLOADER_PARTS=y
|
||||
CONFIG_MTD_PHYSMAP=y
|
||||
CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-2
|
||||
CONFIG_MTD_REDBOOT_PARTS=y
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
CONFIG_MTD_SPLIT_EVA_FW=y
|
||||
CONFIG_MTD_SPLIT_FIRMWARE=y
|
||||
CONFIG_MTD_SPLIT_LZMA_FW=y
|
||||
CONFIG_MTD_SPLIT_MINOR_FW=y
|
||||
CONFIG_MTD_SPLIT_SEAMA_FW=y
|
||||
CONFIG_MTD_SPLIT_TPLINK_FW=y
|
||||
CONFIG_MTD_SPLIT_UIMAGE_FW=y
|
||||
CONFIG_MTD_SPLIT_WRGG_FW=y
|
||||
CONFIG_MTD_TPLINK_PARTS=y
|
||||
CONFIG_NEED_DMA_MAP_STATE=y
|
||||
CONFIG_NEED_PER_CPU_KM=y
|
||||
CONFIG_NET_DSA=y
|
||||
CONFIG_NET_DSA_MV88E6060=y
|
||||
CONFIG_NET_DSA_MV88E6063=y
|
||||
CONFIG_NET_DSA_TAG_TRAILER=y
|
||||
CONFIG_NET_SWITCHDEV=y
|
||||
CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
|
||||
# CONFIG_NO_IOPORT_MAP is not set
|
||||
# CONFIG_OF is not set
|
||||
# CONFIG_PCI_AR724X is not set
|
||||
CONFIG_PCI_DRIVERS_LEGACY=y
|
||||
CONFIG_PERF_USE_VMALLOC=y
|
||||
CONFIG_PGTABLE_LEVELS=2
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_RATIONAL=y
|
||||
# CONFIG_RCU_STALL_COMMON is not set
|
||||
CONFIG_RTL8306_PHY=y
|
||||
CONFIG_RTL8366RB_PHY=y
|
||||
CONFIG_RTL8366S_PHY=y
|
||||
CONFIG_RTL8366_SMI=y
|
||||
CONFIG_RTL8367_PHY=y
|
||||
# CONFIG_SCHED_INFO is not set
|
||||
# CONFIG_SCSI_DMA is not set
|
||||
# CONFIG_SERIAL_8250_FSL is not set
|
||||
CONFIG_SERIAL_8250_NR_UARTS=1
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=1
|
||||
# CONFIG_SOC_AR71XX is not set
|
||||
# CONFIG_SOC_AR724X is not set
|
||||
# CONFIG_SOC_AR913X is not set
|
||||
# CONFIG_SOC_AR933X is not set
|
||||
# CONFIG_SOC_AR934X is not set
|
||||
# CONFIG_SOC_QCA953X is not set
|
||||
# CONFIG_SOC_QCA955X is not set
|
||||
# CONFIG_SOC_QCA956X is not set
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_ATH79=y
|
||||
CONFIG_SPI_BITBANG=y
|
||||
CONFIG_SPI_GPIO=y
|
||||
CONFIG_SPI_MASTER=y
|
||||
# CONFIG_SPI_RB4XX is not set
|
||||
# CONFIG_SPI_VSC7385 is not set
|
||||
CONFIG_SRCU=y
|
||||
CONFIG_SWCONFIG=y
|
||||
CONFIG_SWCONFIG_LEDS=y
|
||||
CONFIG_SWPHY=y
|
||||
CONFIG_SYSCTL_EXCEPTION_TRACE=y
|
||||
CONFIG_SYS_HAS_CPU_MIPS32_R2=y
|
||||
CONFIG_SYS_HAS_EARLY_PRINTK=y
|
||||
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
|
||||
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
|
||||
CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
|
||||
CONFIG_SYS_SUPPORTS_MIPS16=y
|
||||
CONFIG_SYS_SUPPORTS_ZBOOT=y
|
||||
CONFIG_SYS_SUPPORTS_ZBOOT_UART_PROM=y
|
||||
CONFIG_TICK_CPU_ACCOUNTING=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
@ -0,0 +1,20 @@
|
||||
--- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
|
||||
+++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
|
||||
@@ -14,6 +14,7 @@
|
||||
struct ath79_spi_platform_data {
|
||||
unsigned bus_num;
|
||||
unsigned num_chipselect;
|
||||
+ int *cs_gpios;
|
||||
};
|
||||
|
||||
#endif /* _ATH79_SPI_PLATFORM_H */
|
||||
--- a/drivers/spi/spi-ath79.c
|
||||
+++ b/drivers/spi/spi-ath79.c
|
||||
@@ -231,6 +231,7 @@ static int ath79_spi_probe(struct platfo
|
||||
if (pdata) {
|
||||
master->bus_num = pdata->bus_num;
|
||||
master->num_chipselect = pdata->num_chipselect;
|
||||
+ master->cs_gpios = pdata->cs_gpios;
|
||||
}
|
||||
|
||||
sp->bitbang.master = master;
|
||||
@ -0,0 +1,92 @@
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ath79/gpio.c
|
||||
@@ -0,0 +1,59 @@
|
||||
+/*
|
||||
+ * Atheros AR71XX/AR724X/AR913X GPIO API support
|
||||
+ *
|
||||
+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
|
||||
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
+ *
|
||||
+ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ */
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/gpio.h>
|
||||
+#include <asm/mach-ath79/ar71xx_regs.h>
|
||||
+#include <asm/mach-ath79/ath79.h>
|
||||
+#include "common.h"
|
||||
+
|
||||
+void __iomem *ath79_gpio_base;
|
||||
+EXPORT_SYMBOL_GPL(ath79_gpio_base);
|
||||
+
|
||||
+static void __iomem *ath79_gpio_get_function_reg(void)
|
||||
+{
|
||||
+ u32 reg = 0;
|
||||
+
|
||||
+ if (soc_is_ar71xx() ||
|
||||
+ soc_is_ar724x() ||
|
||||
+ soc_is_ar913x() ||
|
||||
+ soc_is_ar933x())
|
||||
+ reg = AR71XX_GPIO_REG_FUNC;
|
||||
+ else if (soc_is_ar934x())
|
||||
+ reg = AR934X_GPIO_REG_FUNC;
|
||||
+ else
|
||||
+ BUG();
|
||||
+
|
||||
+ return ath79_gpio_base + reg;
|
||||
+}
|
||||
+
|
||||
+void ath79_gpio_function_setup(u32 set, u32 clear)
|
||||
+{
|
||||
+ void __iomem *reg = ath79_gpio_get_function_reg();
|
||||
+
|
||||
+ __raw_writel((__raw_readl(reg) & ~clear) | set, reg);
|
||||
+ /* flush write */
|
||||
+ __raw_readl(reg);
|
||||
+}
|
||||
+
|
||||
+void ath79_gpio_function_enable(u32 mask)
|
||||
+{
|
||||
+ ath79_gpio_function_setup(mask, 0);
|
||||
+}
|
||||
+
|
||||
+void ath79_gpio_function_disable(u32 mask)
|
||||
+{
|
||||
+ ath79_gpio_function_setup(0, mask);
|
||||
+}
|
||||
--- a/arch/mips/include/asm/mach-ath79/ath79.h
|
||||
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
|
||||
@@ -118,6 +118,7 @@ static inline int soc_is_qca955x(void)
|
||||
void ath79_ddr_wb_flush(unsigned int reg);
|
||||
void ath79_ddr_set_pci_windows(void);
|
||||
|
||||
+extern void __iomem *ath79_gpio_base;
|
||||
extern void __iomem *ath79_pll_base;
|
||||
extern void __iomem *ath79_reset_base;
|
||||
|
||||
--- a/arch/mips/ath79/dev-common.c
|
||||
+++ b/arch/mips/ath79/dev-common.c
|
||||
@@ -156,4 +156,5 @@ void __init ath79_gpio_init(void)
|
||||
}
|
||||
|
||||
platform_device_register(&ath79_gpio_device);
|
||||
+ ath79_gpio_base = ioremap(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
|
||||
}
|
||||
--- a/arch/mips/ath79/common.h
|
||||
+++ b/arch/mips/ath79/common.h
|
||||
@@ -24,6 +24,9 @@ unsigned long ath79_get_sys_clk_rate(con
|
||||
|
||||
void ath79_ddr_ctrl_init(void);
|
||||
|
||||
+void ath79_gpio_function_enable(u32 mask);
|
||||
+void ath79_gpio_function_disable(u32 mask);
|
||||
+void ath79_gpio_function_setup(u32 set, u32 clear);
|
||||
void ath79_gpio_init(void);
|
||||
|
||||
#endif /* __ATH79_COMMON_H */
|
||||
@ -0,0 +1,18 @@
|
||||
HACK: register the GPIO driver earlier to ensure that gpio_request calls
|
||||
from mach files succeed.
|
||||
|
||||
--- a/drivers/gpio/gpio-ath79.c
|
||||
+++ b/drivers/gpio/gpio-ath79.c
|
||||
@@ -322,7 +322,11 @@ static struct platform_driver ath79_gpio
|
||||
.remove = ath79_gpio_remove,
|
||||
};
|
||||
|
||||
-module_platform_driver(ath79_gpio_driver);
|
||||
+static int __init ath79_gpio_init(void)
|
||||
+{
|
||||
+ return platform_driver_register(&ath79_gpio_driver);
|
||||
+}
|
||||
+postcore_initcall(ath79_gpio_init);
|
||||
|
||||
MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X GPIO API support");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
@ -0,0 +1,42 @@
|
||||
From 8b7a76e72fc819753878cd5684e243f33f847c79 Mon Sep 17 00:00:00 2001
|
||||
From: Markos Chandras <markos.chandras@imgtec.com>
|
||||
Date: Wed, 21 Aug 2013 11:47:22 +0100
|
||||
Subject: [PATCH] MIPS: ath79: Avoid using unitialized 'reg' variable
|
||||
|
||||
Fixes the following build error:
|
||||
arch/mips/include/asm/mach-ath79/ath79.h:139:20: error: 'reg' may be used
|
||||
uninitialized in this function [-Werror=maybe-uninitialized]
|
||||
arch/mips/ath79/common.c:62:6: note: 'reg' was declared here
|
||||
In file included from arch/mips/ath79/common.c:20:0:
|
||||
arch/mips/ath79/common.c: In function 'ath79_device_reset_clear':
|
||||
arch/mips/include/asm/mach-ath79/ath79.h:139:20:
|
||||
error: 'reg' may be used uninitialized in this function
|
||||
[-Werror=maybe-uninitialized]
|
||||
arch/mips/ath79/common.c:90:6: note: 'reg' was declared here
|
||||
|
||||
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
|
||||
Acked-by: Gabor Juhos <juhosg@openwrt.org>
|
||||
---
|
||||
arch/mips/ath79/common.c | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/arch/mips/ath79/common.c
|
||||
+++ b/arch/mips/ath79/common.c
|
||||
@@ -106,7 +106,7 @@ void ath79_device_reset_set(u32 mask)
|
||||
else if (soc_is_qca955x())
|
||||
reg = QCA955X_RESET_REG_RESET_MODULE;
|
||||
else
|
||||
- BUG();
|
||||
+ panic("Reset register not defined for this SOC");
|
||||
|
||||
spin_lock_irqsave(&ath79_device_reset_lock, flags);
|
||||
t = ath79_reset_rr(reg);
|
||||
@@ -134,7 +134,7 @@ void ath79_device_reset_clear(u32 mask)
|
||||
else if (soc_is_qca955x())
|
||||
reg = QCA955X_RESET_REG_RESET_MODULE;
|
||||
else
|
||||
- BUG();
|
||||
+ panic("Reset register not defined for this SOC");
|
||||
|
||||
spin_lock_irqsave(&ath79_device_reset_lock, flags);
|
||||
t = ath79_reset_rr(reg);
|
||||
@ -0,0 +1,113 @@
|
||||
From 460f382c278fe66059a773c41cbcd0db86d53983 Mon Sep 17 00:00:00 2001
|
||||
From: Mathias Kresin <dev@kresin.me>
|
||||
Date: Thu, 13 Apr 2017 09:47:42 +0200
|
||||
Subject: [PATCH] MIPS: pci-ar724x: get PCIe controller out of reset
|
||||
|
||||
The ar724x pci driver expects the PCIe controller to be brought out of
|
||||
reset by the bootloader.
|
||||
|
||||
At least the AVM Fritz 300E bootloader doesn't take care of releasing
|
||||
the different PCIe controller related resets which causes an endless
|
||||
hang as soon as either the PCIE Reset register (0x180f0018) or the PCI
|
||||
Application Control register (0x180f0000) is read from.
|
||||
|
||||
Do the full "PCIE Root Complex Initialization Sequence" if the PCIe
|
||||
host controller is still in reset during probing.
|
||||
|
||||
The QCA u-boot sleeps 10ms after the PCIE Application Control bit is
|
||||
set to ready. It has been shown that 10ms might not be enough time if
|
||||
PCIe should be used right after setting the bit. During my tests it
|
||||
took up to 20ms till the link was up. Giving the link up to 100ms
|
||||
should work for all cases.
|
||||
|
||||
Signed-off-by: Mathias Kresin <dev@kresin.me>
|
||||
---
|
||||
arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 3 ++
|
||||
arch/mips/pci/pci-ar724x.c | 42 ++++++++++++++++++++++++++
|
||||
2 files changed, 45 insertions(+)
|
||||
|
||||
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
||||
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
||||
@@ -169,6 +169,9 @@
|
||||
#define AR724X_PLL_REG_CPU_CONFIG 0x00
|
||||
#define AR724X_PLL_REG_PCIE_CONFIG 0x10
|
||||
|
||||
+#define AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS BIT(16)
|
||||
+#define AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET BIT(25)
|
||||
+
|
||||
#define AR724X_PLL_FB_SHIFT 0
|
||||
#define AR724X_PLL_FB_MASK 0x3ff
|
||||
#define AR724X_PLL_REF_DIV_SHIFT 10
|
||||
--- a/arch/mips/pci/pci-ar724x.c
|
||||
+++ b/arch/mips/pci/pci-ar724x.c
|
||||
@@ -12,14 +12,18 @@
|
||||
#include <linux/irq.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/init.h>
|
||||
+#include <linux/delay.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <asm/mach-ath79/ath79.h>
|
||||
#include <asm/mach-ath79/ar71xx_regs.h>
|
||||
|
||||
+#define AR724X_PCI_REG_APP 0x0
|
||||
#define AR724X_PCI_REG_RESET 0x18
|
||||
#define AR724X_PCI_REG_INT_STATUS 0x4c
|
||||
#define AR724X_PCI_REG_INT_MASK 0x50
|
||||
|
||||
+#define AR724X_PCI_APP_LTSSM_ENABLE BIT(0)
|
||||
+
|
||||
#define AR724X_PCI_RESET_LINK_UP BIT(0)
|
||||
|
||||
#define AR724X_PCI_INT_DEV0 BIT(14)
|
||||
@@ -325,6 +329,37 @@ static void ar724x_pci_irq_init(struct a
|
||||
apc);
|
||||
}
|
||||
|
||||
+static void ar724x_pci_hw_init(struct ar724x_pci_controller *apc)
|
||||
+{
|
||||
+ u32 ppl, app;
|
||||
+ int wait = 0;
|
||||
+
|
||||
+ /* deassert PCIe host controller and PCIe PHY reset */
|
||||
+ ath79_device_reset_clear(AR724X_RESET_PCIE);
|
||||
+ ath79_device_reset_clear(AR724X_RESET_PCIE_PHY);
|
||||
+
|
||||
+ /* remove the reset of the PCIE PLL */
|
||||
+ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
|
||||
+ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
|
||||
+ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
|
||||
+
|
||||
+ /* deassert bypass for the PCIE PLL */
|
||||
+ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
|
||||
+ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
|
||||
+ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
|
||||
+
|
||||
+ /* set PCIE Application Control to ready */
|
||||
+ app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP);
|
||||
+ app |= AR724X_PCI_APP_LTSSM_ENABLE;
|
||||
+ __raw_writel(app, apc->ctrl_base + AR724X_PCI_REG_APP);
|
||||
+
|
||||
+ /* wait up to 100ms for PHY link up */
|
||||
+ do {
|
||||
+ mdelay(10);
|
||||
+ wait++;
|
||||
+ } while (wait < 10 && !ar724x_pci_check_link(apc));
|
||||
+}
|
||||
+
|
||||
static int ar724x_pci_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct ar724x_pci_controller *apc;
|
||||
@@ -383,6 +418,13 @@ static int ar724x_pci_probe(struct platf
|
||||
apc->pci_controller.io_resource = &apc->io_res;
|
||||
apc->pci_controller.mem_resource = &apc->mem_res;
|
||||
|
||||
+ /*
|
||||
+ * Do the full PCIE Root Complex Initialization Sequence if the PCIe
|
||||
+ * host controller is in reset.
|
||||
+ */
|
||||
+ if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE)
|
||||
+ ar724x_pci_hw_init(apc);
|
||||
+
|
||||
apc->link_up = ar724x_pci_check_link(apc);
|
||||
if (!apc->link_up)
|
||||
dev_warn(&pdev->dev, "PCIe link is down\n");
|
||||
@ -0,0 +1,30 @@
|
||||
--- a/arch/mips/ath79/dev-wmac.c
|
||||
+++ b/arch/mips/ath79/dev-wmac.c
|
||||
@@ -62,10 +62,26 @@ static void __init ar913x_wmac_setup(voi
|
||||
|
||||
static int ar933x_wmac_reset(void)
|
||||
{
|
||||
+ int retries = 20;
|
||||
+
|
||||
ath79_device_reset_set(AR933X_RESET_WMAC);
|
||||
ath79_device_reset_clear(AR933X_RESET_WMAC);
|
||||
|
||||
- return 0;
|
||||
+ while (1) {
|
||||
+ u32 bootstrap;
|
||||
+
|
||||
+ bootstrap = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
|
||||
+ if ((bootstrap & AR933X_BOOTSTRAP_EEPBUSY) == 0)
|
||||
+ return 0;
|
||||
+
|
||||
+ if (retries-- == 0)
|
||||
+ break;
|
||||
+
|
||||
+ udelay(10000);
|
||||
+ }
|
||||
+
|
||||
+ pr_err("ar933x: WMAC reset timed out");
|
||||
+ return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
static int ar933x_r1_get_wmac_revision(void)
|
||||
@ -0,0 +1,31 @@
|
||||
--- a/arch/mips/ath79/dev-wmac.c
|
||||
+++ b/arch/mips/ath79/dev-wmac.c
|
||||
@@ -44,7 +44,7 @@ static struct platform_device ath79_wmac
|
||||
},
|
||||
};
|
||||
|
||||
-static void __init ar913x_wmac_setup(void)
|
||||
+static int ar913x_wmac_reset(void)
|
||||
{
|
||||
/* reset the WMAC */
|
||||
ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
|
||||
@@ -53,10 +53,19 @@ static void __init ar913x_wmac_setup(voi
|
||||
ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
|
||||
mdelay(10);
|
||||
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void __init ar913x_wmac_setup(void)
|
||||
+{
|
||||
+ ar913x_wmac_reset();
|
||||
+
|
||||
ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
|
||||
ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
|
||||
ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
|
||||
ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
|
||||
+
|
||||
+ ath79_wmac_data.external_reset = ar913x_wmac_reset;
|
||||
}
|
||||
|
||||
|
||||
@ -0,0 +1,11 @@
|
||||
--- a/arch/mips/ath79/dev-wmac.c
|
||||
+++ b/arch/mips/ath79/dev-wmac.c
|
||||
@@ -139,6 +139,8 @@ static void ar934x_wmac_setup(void)
|
||||
ath79_wmac_data.is_clk_25mhz = false;
|
||||
else
|
||||
ath79_wmac_data.is_clk_25mhz = true;
|
||||
+
|
||||
+ ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
|
||||
}
|
||||
|
||||
static void qca955x_wmac_setup(void)
|
||||
@ -0,0 +1,20 @@
|
||||
--- a/arch/mips/ath79/setup.c
|
||||
+++ b/arch/mips/ath79/setup.c
|
||||
@@ -40,6 +40,7 @@ static char ath79_sys_type[ATH79_SYS_TYP
|
||||
|
||||
static void ath79_restart(char *command)
|
||||
{
|
||||
+ local_irq_disable();
|
||||
ath79_device_reset_set(AR71XX_RESET_FULL_CHIP);
|
||||
for (;;)
|
||||
if (cpu_wait)
|
||||
--- a/arch/mips/include/asm/mach-ath79/ath79.h
|
||||
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
|
||||
@@ -135,6 +135,7 @@ static inline u32 ath79_pll_rr(unsigned
|
||||
static inline void ath79_reset_wr(unsigned reg, u32 val)
|
||||
{
|
||||
__raw_writel(val, ath79_reset_base + reg);
|
||||
+ (void) __raw_readl(ath79_reset_base + reg); /* flush */
|
||||
}
|
||||
|
||||
static inline u32 ath79_reset_rr(unsigned reg)
|
||||
@ -0,0 +1,28 @@
|
||||
--- a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
|
||||
+++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
|
||||
@@ -36,6 +36,7 @@
|
||||
#define cpu_has_mdmx 0
|
||||
#define cpu_has_mips3d 0
|
||||
#define cpu_has_smartmips 0
|
||||
+#define cpu_has_rixi 0
|
||||
|
||||
#define cpu_has_mips32r1 1
|
||||
#define cpu_has_mips32r2 1
|
||||
@@ -43,6 +44,7 @@
|
||||
#define cpu_has_mips64r2 0
|
||||
|
||||
#define cpu_has_mipsmt 0
|
||||
+#define cpu_has_userlocal 0
|
||||
|
||||
#define cpu_has_64bits 0
|
||||
#define cpu_has_64bit_zero_reg 0
|
||||
@@ -51,5 +53,9 @@
|
||||
|
||||
#define cpu_dcache_line_size() 32
|
||||
#define cpu_icache_line_size() 32
|
||||
+#define cpu_has_vtag_icache 0
|
||||
+#define cpu_has_dc_aliases 1
|
||||
+#define cpu_has_ic_fills_f_dc 0
|
||||
+#define cpu_has_pindexed_dcache 0
|
||||
|
||||
#endif /* __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H */
|
||||
@ -0,0 +1,21 @@
|
||||
--- a/arch/mips/include/asm/mips_machine.h
|
||||
+++ b/arch/mips/include/asm/mips_machine.h
|
||||
@@ -36,6 +36,18 @@ static struct mips_machine machine_##_ty
|
||||
.mach_setup = _setup, \
|
||||
};
|
||||
|
||||
+#define MIPS_MACHINE_NONAME(_type, _id, _setup) \
|
||||
+static const char machine_id_##_type[] __initconst \
|
||||
+ __aligned(1) = _id; \
|
||||
+static struct mips_machine machine_##_type \
|
||||
+ __used __section(.mips.machines.init) = \
|
||||
+{ \
|
||||
+ .mach_type = _type, \
|
||||
+ .mach_id = machine_id_##_type, \
|
||||
+ .mach_name = NULL, \
|
||||
+ .mach_setup = _setup, \
|
||||
+};
|
||||
+
|
||||
extern long __mips_machines_start;
|
||||
extern long __mips_machines_end;
|
||||
|
||||
@ -0,0 +1,124 @@
|
||||
--- a/lib/Kconfig
|
||||
+++ b/lib/Kconfig
|
||||
@@ -247,6 +247,9 @@ config LZMA_COMPRESS
|
||||
config LZMA_DECOMPRESS
|
||||
tristate
|
||||
|
||||
+config RLE_DECOMPRESS
|
||||
+ tristate
|
||||
+
|
||||
#
|
||||
# These all provide a common interface (hence the apparent duplication with
|
||||
# ZLIB_INFLATE; DECOMPRESS_GZIP is just a wrapper.)
|
||||
--- a/lib/Makefile
|
||||
+++ b/lib/Makefile
|
||||
@@ -120,6 +120,7 @@ obj-$(CONFIG_XZ_DEC) += xz/
|
||||
obj-$(CONFIG_RAID6_PQ) += raid6/
|
||||
obj-$(CONFIG_LZMA_COMPRESS) += lzma/
|
||||
obj-$(CONFIG_LZMA_DECOMPRESS) += lzma/
|
||||
+obj-$(CONFIG_RLE_DECOMPRESS) += rle.o
|
||||
|
||||
lib-$(CONFIG_DECOMPRESS_GZIP) += decompress_inflate.o
|
||||
lib-$(CONFIG_DECOMPRESS_BZIP2) += decompress_bunzip2.o
|
||||
--- /dev/null
|
||||
+++ b/include/linux/rle.h
|
||||
@@ -0,0 +1,18 @@
|
||||
+#ifndef _RLE_H_
|
||||
+#define _RLE_H_
|
||||
+
|
||||
+#ifdef CONFIG_RLE_DECOMPRESS
|
||||
+int rle_decode(const unsigned char *src, size_t srclen,
|
||||
+ unsigned char *dst, size_t dstlen,
|
||||
+ size_t *src_done, size_t *dst_done);
|
||||
+#else
|
||||
+static inline int
|
||||
+rle_decode(const unsigned char *src, size_t srclen,
|
||||
+ unsigned char *dst, size_t dstlen,
|
||||
+ size_t *src_done, size_t *dst_done)
|
||||
+{
|
||||
+ return -ENOTSUPP;
|
||||
+}
|
||||
+#endif /* CONFIG_RLE_DECOMPRESS */
|
||||
+
|
||||
+#endif /* _RLE_H_ */
|
||||
--- /dev/null
|
||||
+++ b/lib/rle.c
|
||||
@@ -0,0 +1,78 @@
|
||||
+/*
|
||||
+ * RLE decoding routine
|
||||
+ *
|
||||
+ * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/rle.h>
|
||||
+
|
||||
+int rle_decode(const unsigned char *src, size_t srclen,
|
||||
+ unsigned char *dst, size_t dstlen,
|
||||
+ size_t *src_done, size_t *dst_done)
|
||||
+{
|
||||
+ size_t srcpos, dstpos;
|
||||
+ int ret;
|
||||
+
|
||||
+ srcpos = 0;
|
||||
+ dstpos = 0;
|
||||
+ ret = -EINVAL;
|
||||
+
|
||||
+ /* sanity checks */
|
||||
+ if (!src || !srclen || !dst || !dstlen)
|
||||
+ goto out;
|
||||
+
|
||||
+ while (1) {
|
||||
+ char count;
|
||||
+
|
||||
+ if (srcpos >= srclen)
|
||||
+ break;
|
||||
+
|
||||
+ count = (char) src[srcpos++];
|
||||
+ if (count == 0) {
|
||||
+ ret = 0;
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ if (count > 0) {
|
||||
+ unsigned char c;
|
||||
+
|
||||
+ if (srcpos >= srclen)
|
||||
+ break;
|
||||
+
|
||||
+ c = src[srcpos++];
|
||||
+
|
||||
+ while (count--) {
|
||||
+ if (dstpos >= dstlen)
|
||||
+ break;
|
||||
+
|
||||
+ dst[dstpos++] = c;
|
||||
+ }
|
||||
+ } else {
|
||||
+ count *= -1;
|
||||
+
|
||||
+ while (count--) {
|
||||
+ if (srcpos >= srclen)
|
||||
+ break;
|
||||
+ if (dstpos >= dstlen)
|
||||
+ break;
|
||||
+ dst[dstpos++] = src[srcpos++];
|
||||
+ }
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+out:
|
||||
+ if (src_done)
|
||||
+ *src_done = srcpos;
|
||||
+ if (dst_done)
|
||||
+ *dst_done = dstpos;
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+EXPORT_SYMBOL_GPL(rle_decode);
|
||||
@ -0,0 +1,94 @@
|
||||
--- a/drivers/mtd/maps/physmap.c
|
||||
+++ b/drivers/mtd/maps/physmap.c
|
||||
@@ -31,6 +31,66 @@ struct physmap_flash_info {
|
||||
int vpp_refcnt;
|
||||
};
|
||||
|
||||
+static struct platform_device *physmap_map2pdev(struct map_info *map)
|
||||
+{
|
||||
+ return (struct platform_device *) map->map_priv_1;
|
||||
+}
|
||||
+
|
||||
+static void physmap_lock(struct map_info *map)
|
||||
+{
|
||||
+ struct platform_device *pdev;
|
||||
+ struct physmap_flash_data *physmap_data;
|
||||
+
|
||||
+ pdev = physmap_map2pdev(map);
|
||||
+ physmap_data = pdev->dev.platform_data;
|
||||
+ physmap_data->lock(pdev);
|
||||
+}
|
||||
+
|
||||
+static void physmap_unlock(struct map_info *map)
|
||||
+{
|
||||
+ struct platform_device *pdev;
|
||||
+ struct physmap_flash_data *physmap_data;
|
||||
+
|
||||
+ pdev = physmap_map2pdev(map);
|
||||
+ physmap_data = pdev->dev.platform_data;
|
||||
+ physmap_data->unlock(pdev);
|
||||
+}
|
||||
+
|
||||
+static map_word physmap_flash_read_lock(struct map_info *map, unsigned long ofs)
|
||||
+{
|
||||
+ map_word ret;
|
||||
+
|
||||
+ physmap_lock(map);
|
||||
+ ret = inline_map_read(map, ofs);
|
||||
+ physmap_unlock(map);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static void physmap_flash_write_lock(struct map_info *map, map_word d,
|
||||
+ unsigned long ofs)
|
||||
+{
|
||||
+ physmap_lock(map);
|
||||
+ inline_map_write(map, d, ofs);
|
||||
+ physmap_unlock(map);
|
||||
+}
|
||||
+
|
||||
+static void physmap_flash_copy_from_lock(struct map_info *map, void *to,
|
||||
+ unsigned long from, ssize_t len)
|
||||
+{
|
||||
+ physmap_lock(map);
|
||||
+ inline_map_copy_from(map, to, from, len);
|
||||
+ physmap_unlock(map);
|
||||
+}
|
||||
+
|
||||
+static void physmap_flash_copy_to_lock(struct map_info *map, unsigned long to,
|
||||
+ const void *from, ssize_t len)
|
||||
+{
|
||||
+ physmap_lock(map);
|
||||
+ inline_map_copy_to(map, to, from, len);
|
||||
+ physmap_unlock(map);
|
||||
+}
|
||||
+
|
||||
static int physmap_flash_remove(struct platform_device *dev)
|
||||
{
|
||||
struct physmap_flash_info *info;
|
||||
@@ -153,6 +213,13 @@ static int physmap_flash_probe(struct pl
|
||||
|
||||
simple_map_init(&info->map[i]);
|
||||
|
||||
+ if (physmap_data->lock && physmap_data->unlock) {
|
||||
+ info->map[i].read = physmap_flash_read_lock;
|
||||
+ info->map[i].write = physmap_flash_write_lock;
|
||||
+ info->map[i].copy_from = physmap_flash_copy_from_lock;
|
||||
+ info->map[i].copy_to = physmap_flash_copy_to_lock;
|
||||
+ }
|
||||
+
|
||||
probe_type = rom_probe_types;
|
||||
if (physmap_data->probe_type == NULL) {
|
||||
for (; info->mtd[i] == NULL && *probe_type != NULL; probe_type++)
|
||||
--- a/include/linux/mtd/physmap.h
|
||||
+++ b/include/linux/mtd/physmap.h
|
||||
@@ -25,6 +25,8 @@ struct physmap_flash_data {
|
||||
unsigned int width;
|
||||
int (*init)(struct platform_device *);
|
||||
void (*exit)(struct platform_device *);
|
||||
+ void (*lock)(struct platform_device *);
|
||||
+ void (*unlock)(struct platform_device *);
|
||||
void (*set_vpp)(struct platform_device *, int);
|
||||
unsigned int nr_parts;
|
||||
unsigned int pfow_base;
|
||||
@ -0,0 +1,29 @@
|
||||
--- a/drivers/mtd/chips/jedec_probe.c
|
||||
+++ b/drivers/mtd/chips/jedec_probe.c
|
||||
@@ -148,6 +148,7 @@
|
||||
#define SST39LF160 0x2782
|
||||
#define SST39VF1601 0x234b
|
||||
#define SST39VF3201 0x235b
|
||||
+#define SST39VF6401B 0x236d
|
||||
#define SST39WF1601 0x274b
|
||||
#define SST39WF1602 0x274a
|
||||
#define SST39LF512 0x00D4
|
||||
@@ -1569,6 +1570,18 @@ static const struct amd_flash_info jedec
|
||||
ERASEINFO(0x10000,64),
|
||||
}
|
||||
}, {
|
||||
+ .mfr_id = CFI_MFR_SST,
|
||||
+ .dev_id = SST39VF6401B,
|
||||
+ .name = "SST 39VF6401B",
|
||||
+ .devtypes = CFI_DEVICETYPE_X16,
|
||||
+ .uaddr = MTD_UADDR_0xAAAA_0x5555,
|
||||
+ .dev_size = SIZE_8MiB,
|
||||
+ .cmd_set = P_ID_AMD_STD,
|
||||
+ .nr_regions = 1,
|
||||
+ .regions = {
|
||||
+ ERASEINFO(0x10000,128)
|
||||
+ }
|
||||
+ }, {
|
||||
.mfr_id = CFI_MFR_ST,
|
||||
.dev_id = M29F800AB,
|
||||
.name = "ST M29F800AB",
|
||||
@ -0,0 +1,25 @@
|
||||
--- a/drivers/mtd/Kconfig
|
||||
+++ b/drivers/mtd/Kconfig
|
||||
@@ -178,6 +178,12 @@ menu "Partition parsers"
|
||||
source "drivers/mtd/parsers/Kconfig"
|
||||
endmenu
|
||||
|
||||
+config MTD_CYBERTAN_PARTS
|
||||
+ tristate "Cybertan partitioning support"
|
||||
+ depends on ATH79
|
||||
+ ---help---
|
||||
+ Cybertan partitioning support
|
||||
+
|
||||
config MTD_MYLOADER_PARTS
|
||||
tristate "MyLoader partition parsing"
|
||||
depends on ADM5120 || ATH25 || ATH79
|
||||
--- a/drivers/mtd/Makefile
|
||||
+++ b/drivers/mtd/Makefile
|
||||
@@ -17,6 +17,7 @@ obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63
|
||||
obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm47xxpart.o
|
||||
obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o
|
||||
obj-y += parsers/
|
||||
+obj-$(CONFIG_MTD_CYBERTAN_PARTS) += cybertan_part.o
|
||||
|
||||
# 'Users' - code which presents functionality to userspace.
|
||||
obj-$(CONFIG_MTD_BLKDEVS) += mtd_blkdevs.o
|
||||
@ -0,0 +1,25 @@
|
||||
--- a/drivers/mtd/Kconfig
|
||||
+++ b/drivers/mtd/Kconfig
|
||||
@@ -200,6 +200,12 @@ config MTD_MYLOADER_PARTS
|
||||
You will still need the parsing functions to be called by the driver
|
||||
for your particular device. It won't happen automatically.
|
||||
|
||||
+config MTD_TPLINK_PARTS
|
||||
+ tristate "TP-Link AR7XXX/AR9XXX partitioning support"
|
||||
+ depends on ATH79
|
||||
+ ---help---
|
||||
+ TBD.
|
||||
+
|
||||
comment "User Modules And Translation Layers"
|
||||
|
||||
#
|
||||
--- a/drivers/mtd/Makefile
|
||||
+++ b/drivers/mtd/Makefile
|
||||
@@ -17,6 +17,7 @@ obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63
|
||||
obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm47xxpart.o
|
||||
obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o
|
||||
obj-y += parsers/
|
||||
+obj-$(CONFIG_MTD_TPLINK_PARTS) += tplinkpart.o
|
||||
obj-$(CONFIG_MTD_CYBERTAN_PARTS) += cybertan_part.o
|
||||
|
||||
# 'Users' - code which presents functionality to userspace.
|
||||
@ -0,0 +1,34 @@
|
||||
--- a/drivers/mtd/devices/m25p80.c
|
||||
+++ b/drivers/mtd/devices/m25p80.c
|
||||
@@ -195,6 +195,7 @@ static ssize_t m25p80_read(struct spi_no
|
||||
*/
|
||||
static int m25p_probe(struct spi_device *spi)
|
||||
{
|
||||
+ struct mtd_part_parser_data ppdata = {0,};
|
||||
struct flash_platform_data *data;
|
||||
struct m25p *flash;
|
||||
struct spi_nor *nor;
|
||||
@@ -247,8 +248,11 @@ static int m25p_probe(struct spi_device
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
- return mtd_device_register(&nor->mtd, data ? data->parts : NULL,
|
||||
- data ? data->nr_parts : 0);
|
||||
+ return mtd_device_parse_register(&nor->mtd,
|
||||
+ data ? data->part_probes : NULL,
|
||||
+ &ppdata,
|
||||
+ data ? data->parts : NULL,
|
||||
+ data ? data->nr_parts : 0);
|
||||
}
|
||||
|
||||
|
||||
--- a/include/linux/spi/flash.h
|
||||
+++ b/include/linux/spi/flash.h
|
||||
@@ -24,6 +24,7 @@ struct flash_platform_data {
|
||||
unsigned int nr_parts;
|
||||
|
||||
char *type;
|
||||
+ const char **part_probes;
|
||||
|
||||
/* we'll likely add more ... use JEDEC IDs, etc */
|
||||
};
|
||||
@ -0,0 +1,44 @@
|
||||
--- a/drivers/mtd/redboot.c
|
||||
+++ b/drivers/mtd/redboot.c
|
||||
@@ -77,12 +77,18 @@ static int parse_redboot_partitions(stru
|
||||
static char nullstring[] = "unallocated";
|
||||
#endif
|
||||
|
||||
+ buf = vmalloc(master->erasesize);
|
||||
+ if (!buf)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ restart:
|
||||
if ( directory < 0 ) {
|
||||
offset = master->size + directory * master->erasesize;
|
||||
while (mtd_block_isbad(master, offset)) {
|
||||
if (!offset) {
|
||||
nogood:
|
||||
printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n");
|
||||
+ vfree(buf);
|
||||
return -EIO;
|
||||
}
|
||||
offset -= master->erasesize;
|
||||
@@ -95,10 +101,6 @@ static int parse_redboot_partitions(stru
|
||||
goto nogood;
|
||||
}
|
||||
}
|
||||
- buf = vmalloc(master->erasesize);
|
||||
-
|
||||
- if (!buf)
|
||||
- return -ENOMEM;
|
||||
|
||||
printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n",
|
||||
master->name, offset);
|
||||
@@ -171,6 +173,11 @@ static int parse_redboot_partitions(stru
|
||||
}
|
||||
if (i == numslots) {
|
||||
/* Didn't find it */
|
||||
+ if (offset + master->erasesize < master->size) {
|
||||
+ /* not at the end of the flash yet, maybe next block :) */
|
||||
+ directory++;
|
||||
+ goto restart;
|
||||
+ }
|
||||
printk(KERN_NOTICE "No RedBoot partition table detected in %s\n",
|
||||
master->name);
|
||||
ret = 0;
|
||||
@ -0,0 +1,21 @@
|
||||
--- a/drivers/mtd/nand/Kconfig
|
||||
+++ b/drivers/mtd/nand/Kconfig
|
||||
@@ -569,4 +569,8 @@ config MTD_NAND_MTK
|
||||
Enables support for NAND controller on MTK SoCs.
|
||||
This controller is found on mt27xx, mt81xx, mt65xx SoCs.
|
||||
|
||||
+config MTD_NAND_RB4XX
|
||||
+ tristate "NAND flash driver for RouterBoard 4xx series"
|
||||
+ depends on MTD_NAND && ATH79_MACH_RB4XX
|
||||
+
|
||||
endif # MTD_NAND
|
||||
--- a/drivers/mtd/nand/Makefile
|
||||
+++ b/drivers/mtd/nand/Makefile
|
||||
@@ -33,6 +33,7 @@ obj-$(CONFIG_MTD_NAND_CM_X270) += cmx27
|
||||
obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o
|
||||
obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o
|
||||
obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
|
||||
+obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o
|
||||
obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
|
||||
obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o
|
||||
obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o
|
||||
@ -0,0 +1,21 @@
|
||||
--- a/drivers/mtd/nand/Kconfig
|
||||
+++ b/drivers/mtd/nand/Kconfig
|
||||
@@ -573,4 +573,8 @@ config MTD_NAND_RB4XX
|
||||
tristate "NAND flash driver for RouterBoard 4xx series"
|
||||
depends on MTD_NAND && ATH79_MACH_RB4XX
|
||||
|
||||
+config MTD_NAND_RB750
|
||||
+ tristate "NAND flash driver for the RouterBoard 750"
|
||||
+ depends on MTD_NAND && ATH79_MACH_RB750
|
||||
+
|
||||
endif # MTD_NAND
|
||||
--- a/drivers/mtd/nand/Makefile
|
||||
+++ b/drivers/mtd/nand/Makefile
|
||||
@@ -34,6 +34,7 @@ obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx
|
||||
obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o
|
||||
obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
|
||||
obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o
|
||||
+obj-$(CONFIG_MTD_NAND_RB750) += rb750_nand.o
|
||||
obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
|
||||
obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o
|
||||
obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o
|
||||
@ -0,0 +1,61 @@
|
||||
--- a/drivers/mtd/chips/cfi_cmdset_0002.c
|
||||
+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
|
||||
@@ -40,7 +40,7 @@
|
||||
#include <linux/mtd/xip.h>
|
||||
|
||||
#define AMD_BOOTLOC_BUG
|
||||
-#define FORCE_WORD_WRITE 0
|
||||
+#define FORCE_WORD_WRITE 1
|
||||
|
||||
#define MAX_RETRIES 3
|
||||
|
||||
@@ -51,7 +51,9 @@
|
||||
|
||||
static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
|
||||
static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
|
||||
+#if !FORCE_WORD_WRITE
|
||||
static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
|
||||
+#endif
|
||||
static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
|
||||
static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
|
||||
static void cfi_amdstd_sync (struct mtd_info *);
|
||||
@@ -202,6 +204,7 @@ static void fixup_amd_bootblock(struct m
|
||||
}
|
||||
#endif
|
||||
|
||||
+#if !FORCE_WORD_WRITE
|
||||
static void fixup_use_write_buffers(struct mtd_info *mtd)
|
||||
{
|
||||
struct map_info *map = mtd->priv;
|
||||
@@ -211,6 +214,7 @@ static void fixup_use_write_buffers(stru
|
||||
mtd->_write = cfi_amdstd_write_buffers;
|
||||
}
|
||||
}
|
||||
+#endif /* !FORCE_WORD_WRITE */
|
||||
|
||||
/* Atmel chips don't use the same PRI format as AMD chips */
|
||||
static void fixup_convert_atmel_pri(struct mtd_info *mtd)
|
||||
@@ -1788,6 +1792,7 @@ static int cfi_amdstd_write_words(struct
|
||||
/*
|
||||
* FIXME: interleaved mode not tested, and probably not supported!
|
||||
*/
|
||||
+#if !FORCE_WORD_WRITE
|
||||
static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
|
||||
unsigned long adr, const u_char *buf,
|
||||
int len)
|
||||
@@ -1916,7 +1921,6 @@ static int __xipram do_write_buffer(stru
|
||||
return ret;
|
||||
}
|
||||
|
||||
-
|
||||
static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
|
||||
size_t *retlen, const u_char *buf)
|
||||
{
|
||||
@@ -1991,6 +1995,7 @@ static int cfi_amdstd_write_buffers(stru
|
||||
|
||||
return 0;
|
||||
}
|
||||
+#endif /* !FORCE_WORD_WRITE */
|
||||
|
||||
/*
|
||||
* Wait for the flash chip to become ready to write data
|
||||
@ -0,0 +1,25 @@
|
||||
--- a/drivers/mtd/nand/Kconfig
|
||||
+++ b/drivers/mtd/nand/Kconfig
|
||||
@@ -577,4 +577,12 @@ config MTD_NAND_RB750
|
||||
tristate "NAND flash driver for the RouterBoard 750"
|
||||
depends on MTD_NAND && ATH79_MACH_RB750
|
||||
|
||||
+config MTD_NAND_AR934X
|
||||
+ tristate "NAND flash driver for the Qualcomm Atheros AR934x/QCA955x SoCs"
|
||||
+ depends on (SOC_AR934X || SOC_QCA955X)
|
||||
+
|
||||
+config MTD_NAND_AR934X_HW_ECC
|
||||
+ bool "Hardware ECC support for the AR934X NAND Controller (EXPERIMENTAL)"
|
||||
+ depends on MTD_NAND_AR934X
|
||||
+
|
||||
endif # MTD_NAND
|
||||
--- a/drivers/mtd/nand/Makefile
|
||||
+++ b/drivers/mtd/nand/Makefile
|
||||
@@ -13,6 +13,7 @@ obj-$(CONFIG_MTD_NAND_AMS_DELTA) += ams-
|
||||
obj-$(CONFIG_MTD_NAND_DENALI) += denali.o
|
||||
obj-$(CONFIG_MTD_NAND_DENALI_PCI) += denali_pci.o
|
||||
obj-$(CONFIG_MTD_NAND_DENALI_DT) += denali_dt.o
|
||||
+obj-$(CONFIG_MTD_NAND_AR934X) += ar934x_nfc.o
|
||||
obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o
|
||||
obj-$(CONFIG_MTD_NAND_BF5XX) += bf5xx_nand.o
|
||||
obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o
|
||||
@ -0,0 +1,23 @@
|
||||
--- a/drivers/mtd/nand/Kconfig
|
||||
+++ b/drivers/mtd/nand/Kconfig
|
||||
@@ -577,6 +577,10 @@ config MTD_NAND_RB750
|
||||
tristate "NAND flash driver for the RouterBoard 750"
|
||||
depends on MTD_NAND && ATH79_MACH_RB750
|
||||
|
||||
+config MTD_NAND_RB91X
|
||||
+ tristate "NAND flash driver for the RouterBOARD 91x series"
|
||||
+ depends on MTD_NAND && ATH79_MACH_RB91X
|
||||
+
|
||||
config MTD_NAND_AR934X
|
||||
tristate "NAND flash driver for the Qualcomm Atheros AR934x/QCA955x SoCs"
|
||||
depends on (SOC_AR934X || SOC_QCA955X)
|
||||
--- a/drivers/mtd/nand/Makefile
|
||||
+++ b/drivers/mtd/nand/Makefile
|
||||
@@ -36,6 +36,7 @@ obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nan
|
||||
obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
|
||||
obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o
|
||||
obj-$(CONFIG_MTD_NAND_RB750) += rb750_nand.o
|
||||
+obj-$(CONFIG_MTD_NAND_RB91X) += rb91x_nand.o
|
||||
obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
|
||||
obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o
|
||||
obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o
|
||||
@ -0,0 +1,28 @@
|
||||
--- a/drivers/net/ethernet/atheros/Kconfig
|
||||
+++ b/drivers/net/ethernet/atheros/Kconfig
|
||||
@@ -5,7 +5,7 @@
|
||||
config NET_VENDOR_ATHEROS
|
||||
bool "Atheros devices"
|
||||
default y
|
||||
- depends on PCI
|
||||
+ depends on (PCI || ATH79)
|
||||
---help---
|
||||
If you have a network (Ethernet) card belonging to this class, say Y.
|
||||
|
||||
@@ -78,4 +78,6 @@ config ALX
|
||||
To compile this driver as a module, choose M here. The module
|
||||
will be called alx.
|
||||
|
||||
+source drivers/net/ethernet/atheros/ag71xx/Kconfig
|
||||
+
|
||||
endif # NET_VENDOR_ATHEROS
|
||||
--- a/drivers/net/ethernet/atheros/Makefile
|
||||
+++ b/drivers/net/ethernet/atheros/Makefile
|
||||
@@ -2,6 +2,7 @@
|
||||
# Makefile for the Atheros network device drivers.
|
||||
#
|
||||
|
||||
+obj-$(CONFIG_AG71XX) += ag71xx/
|
||||
obj-$(CONFIG_ATL1) += atlx/
|
||||
obj-$(CONFIG_ATL2) += atlx/
|
||||
obj-$(CONFIG_ATL1E) += atl1e/
|
||||
@ -0,0 +1,31 @@
|
||||
Index: linux-4.14.61/drivers/net/dsa/Kconfig
|
||||
===================================================================
|
||||
--- linux-4.14.61.orig/drivers/net/dsa/Kconfig
|
||||
+++ linux-4.14.61/drivers/net/dsa/Kconfig
|
||||
@@ -3,6 +3,14 @@ menu "Distributed Switch Architecture dr
|
||||
|
||||
source "drivers/net/dsa/b53/Kconfig"
|
||||
|
||||
+config NET_DSA_MV88E6063
|
||||
+ bool "Marvell 88E6063 ethernet switch chip support"
|
||||
+ depends on NET_DSA
|
||||
+ select NET_DSA_TAG_TRAILER
|
||||
+ ---help---
|
||||
+ This enables support for the Marvell 88E6063 ethernet switch
|
||||
+ chip
|
||||
+
|
||||
config NET_DSA_BCM_SF2
|
||||
tristate "Broadcom Starfighter 2 Ethernet switch support"
|
||||
depends on HAS_IOMEM && NET_DSA && OF_MDIO
|
||||
Index: linux-4.14.61/drivers/net/dsa/Makefile
|
||||
===================================================================
|
||||
--- linux-4.14.61.orig/drivers/net/dsa/Makefile
|
||||
+++ linux-4.14.61/drivers/net/dsa/Makefile
|
||||
@@ -7,6 +7,7 @@ obj-$(CONFIG_FIXED_PHY) += dsa_loop_bdi
|
||||
endif
|
||||
obj-$(CONFIG_NET_DSA_MT7530) += mt7530.o
|
||||
obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o
|
||||
+obj-$(CONFIG_NET_DSA_MV88E6063) += mv88e6063.o
|
||||
obj-$(CONFIG_NET_DSA_QCA8K) += qca8k.o
|
||||
obj-$(CONFIG_NET_DSA_SMSC_LAN9303) += lan9303-core.o
|
||||
obj-$(CONFIG_NET_DSA_SMSC_LAN9303_I2C) += lan9303_i2c.o
|
||||
@ -0,0 +1,12 @@
|
||||
--- a/drivers/Makefile
|
||||
+++ b/drivers/Makefile
|
||||
@@ -77,8 +77,8 @@ obj-$(CONFIG_SCSI) += scsi/
|
||||
obj-y += nvme/
|
||||
obj-$(CONFIG_ATA) += ata/
|
||||
obj-$(CONFIG_TARGET_CORE) += target/
|
||||
-obj-$(CONFIG_MTD) += mtd/
|
||||
obj-$(CONFIG_SPI) += spi/
|
||||
+obj-$(CONFIG_MTD) += mtd/
|
||||
obj-$(CONFIG_SPMI) += spmi/
|
||||
obj-$(CONFIG_HSI) += hsi/
|
||||
obj-y += net/
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue