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@ -10,7 +10,7 @@
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obj-$(CONFIG_MIPS_PCI_VIRTIO) += pci-virtio-guest.o
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--- /dev/null
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+++ b/arch/mips/pci/pci-ar2315.c
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@@ -0,0 +1,345 @@
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@@ -0,0 +1,447 @@
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+/*
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License
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@ -64,12 +64,114 @@
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+#include <ar231x.h>
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+#include <ar2315_regs.h>
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+
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+/*
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+ * PCI Bus Interface Registers
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+ */
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+#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
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+
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+#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
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+
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+#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
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+
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+#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
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+#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* Mem or Config cycles */
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+#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
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+#define AR2315_PCIMISC_RST_MODE 0x00000030
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+#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
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+#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
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+#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
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+#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
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+#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
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+#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
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+#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
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+#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
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+ * disable */
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+
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+#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
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+
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+#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
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+
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+#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
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+
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+#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
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+#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
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+#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
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+#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
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+
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+#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
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+
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+#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
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+#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
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+#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
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+#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
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+
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+#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
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+
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+#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
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+
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+#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
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+
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+#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
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+
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+#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
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+
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+#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
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+
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+/* PCI interrupt status (write one to clear) */
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+#define AR2315_PCI_ISR (AR2315_PCI + 0x0500)
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+
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+#define AR2315_PCI_INT_TX 0x00000001 /* Desc In Completed */
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+#define AR2315_PCI_INT_TXOK 0x00000002 /* Desc In OK */
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+#define AR2315_PCI_INT_TXERR 0x00000004 /* Desc In ERR */
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+#define AR2315_PCI_INT_TXEOL 0x00000008 /* Desc In End-of-List */
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+#define AR2315_PCI_INT_RX 0x00000010 /* Desc Out Completed */
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+#define AR2315_PCI_INT_RXOK 0x00000020 /* Desc Out OK */
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+#define AR2315_PCI_INT_RXERR 0x00000040 /* Desc Out ERR */
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+#define AR2315_PCI_INT_RXEOL 0x00000080 /* Desc Out EOL */
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+#define AR2315_PCI_INT_TXOOD 0x00000200 /* Desc In Out-of-Desc */
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+#define AR2315_PCI_INT_DESCMASK 0x0000FFFF /* Desc Mask */
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+#define AR2315_PCI_INT_EXT 0x02000000 /* Extern PCI INTA */
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+#define AR2315_PCI_INT_ABORT 0x04000000 /* PCI bus abort event */
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+
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+/* PCI interrupt mask */
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+#define AR2315_PCI_IMR (AR2315_PCI + 0x0504)
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+
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+/* Global PCI interrupt enable */
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+#define AR2315_PCI_IER (AR2315_PCI + 0x0508)
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+
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+#define AR2315_PCI_IER_DISABLE 0x00 /* disable pci interrupts */
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+#define AR2315_PCI_IER_ENABLE 0x01 /* enable pci interrupts */
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+
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+#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
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+#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
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+#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
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+#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
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+#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
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+#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
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+
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+/*
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+ * PCI interrupts, which share IP5
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+ * Keep ordered according to AR2315_PCI_INT_XXX bits
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+ */
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+#define AR2315_PCI_IRQ_BASE 0x50
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+#define AR2315_PCI_IRQ_EXT (AR2315_PCI_IRQ_BASE+0)
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+#define AR2315_PCI_IRQ_ABORT (AR2315_PCI_IRQ_BASE+1)
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+#define AR2315_PCI_IRQ_COUNT 2
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+#define AR2315_PCI_IRQ_SHIFT 25 /* in AR2315_PCI_INT_STATUS */
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+
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+/* Arbitrary size of memory region to access the configuration space */
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+#define AR2315_PCI_CFG_SIZE 0x00100000
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+
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+#define AR2315_PCI_HOST_SLOT 3
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+#define AR2315_PCI_HOST_DEVID ((0xff18 << 16) | PCI_VENDOR_ID_ATHEROS)
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+
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+/* ??? access BAR */
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+#define AR2315_PCI_HOST_MBAR0 0x10000000
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+/* RAM access BAR */
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+#define AR2315_PCI_HOST_MBAR1 AR2315_PCI_HOST_SDRAM_BASEADDR
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+/* ??? access BAR */
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+#define AR2315_PCI_HOST_MBAR2 0x30000000
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+
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+static void __iomem *ar2315_pci_cfg_mem;
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+
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+static int ar2315_pci_cfg_access(int devfn, int where, int size, u32 *ptr,
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Felix Fietkau
9 years ago